Comparative Cradle-to-Gate Life Cycle Assessment of Planar and Vertical HZO-Based Ferroelectric Memories (FeRAM) on 22 nm FDSOI Node ^†

Abstract

Emerging non-volatile memories based on ferroelectric materials are currently under development to be integrated in the back-end-of-line of advanced complementary metal-oxide-semiconductor (CMOS) nodes. A life cycle assessment (LCA) over 16 impact categories has been carried out to compare planar (2D) and vertical (3D) integration strategies for the manufacturing of Hf_0.5Zr_0.5O₂-based ferroelectric capacitors on a 22 nm CMOS technology node. The LCA demonstrates that the 3D approach allows us to reduce the environmental impacts by up to 20% over several impact categories. The device isolation by a single chemical–mechanical polishing (CMP) step instead of the standard photolithography and plasma etching processes proved to be the main source of reduction on the overall environmental footprint.

1. Introduction

Non-volatile ferroelectric random-access memories (FeRAM) based on Hf_0.5Zr_0.5O₂ (HZO) thin films are receiving significant attention for next-generation high-density storage class memory and artificial intelligence applications [1]. Due to their fast voltage-driven switching mechanism, FeRAM technologies are intrinsically ultra-low-power and offer high endurance. They are thus considered promising alternatives to conventional embedded flash (eFlash) and other emerging technologies, such as magnetic (MRAM) or filament-based resistive (ReRAM) memories [2]. Current development efforts are focused on their reliable integration in the back-end-of-line (BEOL) of advanced complementary metal-oxide-semiconductor (CMOS) nodes [3,4], such as the 22 nm fully depleted silicon-on-insulator (FDSOI) technology [5]. The main objectives of the ongoing manufacturing process optimizations include the following [6]:

• Increasing the density of ferroelectric capacitors (FeCAPs) by transitioning from planar (2D) to vertical (3D) device architectures;
• Simplifying the manufacturing process to increase yields and decrease costs, ideally by reducing the number of patterning steps relying on photolithography and plasma etching.

To the best of our knowledge, no environmental assessment of the manufacturing footprint of HZO-based FeRAM has been published yet. Studying the environmental implications of different integration strategies is essential for evaluating the overall sustainability of FeRAM technology. To address that gap, this paper presents a comparative cradle-to-gate life cycle assessment (LCA) across 16 impact categories of FeRAM technologies based on a 22 nm FDSOI node. The study compares three distinct HZO-based FeCAP integration strategies: a planar (2D) design, a vertical approach with plasma-based patterning (3D-Gen1), and a cost-optimized vertical design relying on a damascene process (3D-Gen2).

2. Goal and Scope Definition

This study aims to compare three integration schemes of FeCAPs in the BEOL of a 22 nm FDSOI node, identifying the main contributors in the manufacturing stage and suggesting approaches to decrease the environmental impacts. As illustrated in Figure 1, the scope of the LCA is limited to the FeCAP fabrication, given that the rest of the manufacturing operations remain unchanged. A cradle-to-gate approach, taking into account the raw material extraction and the production phase, was preferred since the use phase depends on the application.

The LCA was performed for the following functional unit: to produce ferroelectric capacitors on a 300 mm wafer. Here, the functional unit does not reflect a real function as the scope of this study is limited to a comparison of manufacturing processes.

3. Life Cycle Inventory

3.1. Method

The collection of inventory data, where applicable, has been carried out based on CEA-Leti’s cleanroom thanks to a hybrid approach, combining both top-down and bottom-up strategies, as described in [7]. A bottom-up approach was used for the processes, for which chemicals, gases and deionized or ultrapure water (UPW) were collected individually for each process step.

Regarding deposition processes, when not measured directly, we modeled the mass of metal or chemical precursor consumed during the process. In order to take into account the material losses during the deposition, we assumed a transfer percentage from the target or the precursors on the wafer: 10% for PVD, 5% for CVD and 1% for ALD.

3.2. Process Integration

All three integration approaches were realized on 300 mm wafers in the BEOL of 22 nm FDSOI technology between M4 and M5 copper (Cu) lines, as shown in Figure 2. The 2D and 3D-Gen1 manufacturing processes are detailed in [5], and the development results of 3D-Gen2 will be published in 2026. In the 2D approach, the memory stack is deposited on a planar surface, and the devices are isolated by an immersion UV photolithography and plasma etching sequence. Regarding the 3D approach, the memory stack is deposited in vias, which enables two different integration options based on either (i) a traditional plasma-based patterning of FeCAPs (3D-Gen 1) or (ii) a damascene approach (3D-Gen2), where a CMP process removes the metal overburden (W, TiN, HZO) on top of the vias. The damascene process allows us to use only three lithography masks instead of four in 2D and 3D-Gen1, reducing the number of process steps and their related costs.

3.3. Life Cycle Inventory Results

The process steps are gathered into six process categories: deposition (DEP), photolithography (PHO), photoresist stripping (STR), etching (ETCH), chemical–mechanical polishing (CMP) and thermal treatment (TTH).

Table 1. Number of process steps per process category for the three integration schemes.

	2D	3D-Gen1	3D-Gen2
Deposition	12	11	11
Etching	4	4	4
Photolithography	4	4	3
CMP	5	4	3
Resist stripping	5	5	3
Thermal treatment	2	2	2
Total	32	30	26

shows the number of steps per process category. An aggregated life cycle inventory is shown in

Table 2. Comparison of aggregated inventory data between the integration strategies.

	2D	3D-Gen1	3D-Gen2
Ultrapure water	110 L/wafer	105 L/wafer	84 L/wafer
Chemicals (incl. water)	17 kg/wafer	20 kg/wafer	16 kg/wafer
Gas	0.9 kg/wafer	1.1 kg/wafer	0.8 kg/wafer
Energy	202 MJ	307 MJ	243 MJ

to highlight the reduction in ultrapure water (UPW), chemicals, gas and metal consumption in 3D-Gen2 compared to 2D. Ultrapure water (UPW) is mostly consumed during CMP (~60–70%, depending on the integration) and photoresist stripping (~20–30%) steps. Similarly, chemicals are mostly spent during the stripping (~70–80%) and CMP processes (~15–30%).

Hence, the reduction in stripping and CMP processes in 3D-Gen2 leads to an overall reduction in chemical and UPW consumption. Gases are mostly employed in deposition processes (~55–60%), thermal treatment (~15%) and CMP (~15–20%).

3D-Gen1 consumes more gases than the 2D integration due to thicker dielectric layers (longer deposition process) and longer etching processes. Thinner dielectric layers are employed in 3D-Gen2. The etching steps are shorter, which leads to a reduction in gas consumption.

4. Life Cycle Assessment

The LCA was conducted with Simapro software (version 10.2) and the Ecoinvent 3.10 database. When data from life cycle inventory was not available in the Ecoinvent database, a proxy or an isomer from the database was used: CH₂F₂, modeled as trifluoromethane CHF₃, C₄F₈ as perfluoropentane C₅F₁₂, CF₄ as hexafluoroethane C₂F₆, HBr as Br₂, TDMAT as TiCl₄ and N₂O, modeled as NO₂.

The comparative analysis is carried out on all 16 categories. The interpretation and hotspot analysis are carried out on the most relevant impact categories, which contribute cumulatively to at least 80% of the total environmental impact, expressed as a single score, according to the PEF method [8]. As a result of this approach, we will mainly focus on the following seven impact categories: climate change, ionizing radiation, ozone depletion, photochemical ozone formation, resource use—fossils, resource use—minerals and metals and water use.

4.1. Comparison Between FeCAP Integration Approaches

Figure 3 shows the relative LCA results for the three process flows over the 16 impact categories. The 3D-Gen2 strategy leads to a significant reduction in environmental impact in all categories, except for the ozone depletion. This is due to the higher consumption of C₄F₈ in 3D-Gen2 during dry etching of thicker dielectric layers (vias). Since no data was available for C₄F₈, C5F12 was used as a proxy. These two molecules have both a zero ozone depletion potential and a similar global warming potential (10,200 and 9220 for C₄F₈ and C₅F₁₂ respectively) [9].

4.2. Main Contributors to the 3D-Gen2 Integration Scheme

The main contributors are summarized in

Table A1. Main contributors and related process categories for the 3D-Gen2 manufacturing.

Impact Category	LCA Results of 3D-Gen2	Main Contributors in 3D-Gen2	Related Process Categories
Climate change	24.6 kgCO2eq	Electricity (FR) (22%) H2O2 production (15%) N2O emissions (12%) and NF3 emissions (9%)	Deposition and CMP Stripping PECVD
Ionizing radiation	33.2 kBq U-235 eq	Electricity (FR) (95%)	Deposition CMP
Ozone depletion	2.4 × 10−6 kg CFC11 eq	Production of C2H2F4 for fabrication of C5F12 (proxy for C4F8) (26%) Production of C2F6 (proxy for CF4) (21%) Seawater reverse osmosis for UPW production (11%)	Plasma etching CMP
Photochemical ozone formation	0.1 kg NMVOC eq	Solvent waste treatment (48%) Electricity (FR) (21%) H2O2 production (9%)	Photolithography Deposition and CMP Stripping
Resource use, fossils	893 MJ	Electricity (FR) (79%)	Deposition CMP
Resource use, minerals and metals	3.2 × 10−4 kg Sb eq	Electricity (FR) (81%)	Deposition CMP
Water use	15.2 m3 depriv.	H2O2 production (43%) Softened water in gas abatement systems (21%) Electricity (FR) (15%)	Stripping Etching and deposition

(Appendix A). Deposition and CMP are the process categories with the largest environmental impact for three impact categories, due to the long process duration. In our model, this leads to a higher electricity consumption. The emissions of high-GWP gases (N₂O and NF₃, used in the deposition process and in the post-cleaning process, respectively) are the main contributors to climate change. The production of H₂O₂ solution, mainly used for resist stripping, contributes to several impact categories.

4.3. Sensitivity Analysis

Several publications already showed that the production location and the energy mix have a significant impact on the overall environmental burden [7]. This parameter is not investigated here since the objective is to compare forms of process integration.

Periodic cleaning of the deposition chamber is essential to prevent particle/chemical contamination and maintain process repeatability. Namely, NF₃ is widely used to clean chemical vapor deposition (CVD) chambers with the remote plasma method. In the 3D-Gen2 integration flow, we considered that six CVD steps require chamber cleaning (five plasma enhanced PECVD and one CVD). In this case, we assumed that chamber cleaning is repeated after each deposition step. We can consider this as a worst-case scenario, as less chamber cleaning would be applied in an actual industrial environment to optimize wafer throughput on dedicated manufacturing tools. NF₃ is effectively used in a remote plasma clean system: 98% of NF₃ is consumed during the cleaning, and 95% of residual emissions are destroyed by the abatement system, according to the IPCC’s assumptions. In Figure 4, the LCA results of 3D-Gen2 are shown according to the number of wafers treated per chamber clean (N). Even if NF₃ is effectively consumed in the cleaning step, the number of wafers processed between two cleaning effects significantly affects the overall environmental impact. Climate change can be reduced by 12% if the chamber cleaning is performed after six wafers instead of one wafer.

The three integrations were fabricated with the same photolithography masks. In the future, a specific mask set will be designed to increase the FeCAP density and thus to decrease the bit cell area. We will investigate, in a second phase, the number of chips per 300 mm wafer, which should vary between 2D and 3D-Gen2 integrations and influence the environmental footprint per chip.

4.4. Comparison with the CMOS Manufacturing

Ferroelectric memories (FeRAM) based on a one-transistor, one-capacitor (1T1C) architecture must be fabricated in the BEOL to be connected to the CMOS transistor circuits below. The FeCAP fabrication involves only three or four lithography masks, whereas the 22 nm CMOS technology involve 54 masks, according to the Negaoctet database from Bureau Veritas CODDE (2023 version). Comparing the environmental impact of the FeCAP from our study and the 22 nm CMOS fabrication from Negaoctet shows that the FeCAP step adds less than 5% to the environmental impact of the CMOS manufacturing in the following categories: climate change, ecotoxicity freshwater, ionizing radiation, resource use (fossils) and water use. It should be noted that for the category resource use (minerals and metals), the impact of the FeCAP is approximately three times higher than the CMOS value, which does not seem to be possible. Since the main contributor to this category is the electricity production, a simple comparison of the two databases has been conducted on the production of one MJ of electricity mix at a low voltage in France. The value in the category “resource use, minerals and metals” is about 46 times lower than the Ecoinvent value. The Negaoctet value in this category is therefore probably not reliable. In the other categories, the relative impact of the FeCAP compared to CMOS is proportional to the number of photolithography masks.

The imec.netzero database [10] provides the carbon footprint of the 28 nm CMOS fabrication in France. Compared to their data, the FeCAP manufacturing accounts for 8% of the environmental impact of CMOS.

5. Conclusions

A life cycle assessment has been conducted on the fabrication of ferroelectric capacitors and following three integration schemes in the BEOL of a 22 nm CMOS node. This study demonstrates that the reduction in process steps is, in this case, effective to lower environmental impacts. Specifically, the damascene-based 3D-Gen2 integration approach reduces environmental impacts by up to 20% across several categories compared to the 2D integration. Introducing CMP to isolate the FeCAP devices instead of the photolithography and plasma etching processes is the primary reason for this smaller environmental footprint. This damascene approach could be applied to other capacitive memories such as AlScN-memory devices. In addition to infrastructure and process optimization, this work demonstrates that a clever device integration is a powerful lever to decrease the environmental burden of semiconductor devices.