Search Results (54)

This paper proposes a hybrid energy-harvesting chip that utilizes both radio-frequency (RF) energy and solar energy for low-power applications and extended service life. The key contributions include a wide input power range, a compact chip area, and a high maximum power conversion efficiency (PCE). Solar energy is a clean and readily available source. The hybrid energy harvesting system has gained popularity by combining RF and solar energy to improve overall energy availability and efficiency. The proposed chip comprises a matching network, rectifier, charge pump, DC combiner, overvoltage protection circuit, and low-dropout voltage regulator (LDO). The matching network ensures maximum power delivery from the antenna to the rectifier. The rectifier circuit utilizes a cross-coupled differential drive rectifier to convert radio frequency energy into DC voltage, incorporating boosting functionality. In addition, a solar harvester is employed to provide an additional energy source to extend service time and stabilize the output by combining it with the radio-frequency source using a DC combiner. The overvoltage protection circuit safeguards against high voltage passing from the DC combiner to the LDO. Finally, the LDO facilitates the production of a stable output voltage. The entire circuit is simulated using the Taiwan Semiconductor Manufacturing Company 0.18 µm 1P6M complementary metal–oxide–semiconductor standard process developed by the Taiwan Semiconductor Research Institute. The simulation results indicated a rectifier conversion efficiency of approximately 41.6% for the proposed radio-frequency-energy-harvesting system. It can operate with power levels ranging from −1 to 20 dBm, and the rectifier circuit’s output voltage is within the range of 1.7–1.8 V. A 0.2 W monocrystalline silicon solar panel (70 × 30 mm²) was used to generate a supplied voltage of 1 V. The overvoltage protection circuit limited the output voltage to 3.6 V. Finally, the LDO yielded a stable output voltage of 3.3 V. Full article

The technological advances in internet of things (IoT) devices have raised the demand for cost-efficient and sustainable energy sources. Piezoelectric energy harvesters (PEHs) are promising low-cost and eco-friendly energy sources but require robust power management circuits (PMCs) for voltage conversion and regulation. This work presents a complementary metal–oxide–semiconductor (CMOS)-based PMC, integrating a reconfigurable AC-DC rectifier and a low-dropout (LDO) voltage regulator designed using 0.18 µm Taiwan semiconductor manufacturing company (TSMC) CMOS technology. This design includes an intermediate coupling stage to reduce voltage drop and improve the transfer efficiency of the PMC. In addition, we develop numerical simulations of the PMC performance, achieving a voltage conversion efficiency (VCE) between 72.8% and 43.21% using input voltages from 0.7 V to 2.8 V with a 50 kΩ load resistance. Compared to previous designs, the proposed circuit demonstrates improved stability, reduced area (66.28 mm²), and extended operating voltage range, allowing its potential application for ultra-low-power IoT nodes. This PMC contributes to the development of autonomous systems with reduced battery dependency and enhanced sustainability. Full article

This article introduces an innovative, fully integrated low-dropout (LDO) specifically designed for low-power applications, capable of handling a wide range of load currents. By employing dynamic biasing to enhance noise performance, the LDO shows a noise equal to 14 $\mathsf{\mu }\mathrm{V}/\sqrt{\mathrm{Hz}}$ at f < 1 kHz. The LDO demonstrates remarkable efficiency with a load regulation (LDR) of 3.8 mV/A and a line regulation (LNR) of 0.71 mV/V. It boasts a rapid settling time of 1 $\mathsf{\mu }$s during load transitions up to 100 mA and a minimal quiescent current of 5 $\mathsf{\mu }$A. The regulator consistently provides a 2.6 V output for input voltages between 2.8 V and 4.8 V, with a dropout voltage of 67 mV, supporting load currents from 0 mA to 100 mA over a temperature range of −25 °C to +125 °C. The design is based on a 150 nm CMOS process to ensure high sensitivity and high performance, making it an ideal choice for battery-operated systems. Full article

A programmable gain amplifier (PGA) is commonly used to optimize the input dynamic range of high-performance systems such as headphones and biomedical sensors. But PGA is rather sensitive to electromagnetic interference (EMI), which limits the precision of these systems. Many capacitor-less low-dropout regulator (LDO) schemes with high power supply rejection have been proposed to act as the independent power supply for PGA, which consumes additional power and area. This paper proposed a PGA with a high power supply rejection ratio (PSRR) and low power consumption, which serves as the analog front-end amplifier in the 20-bit sigma-delta ADC. The PGA is a two-stage amplifier with hybrid compensation. The first stage is the recycling folded cascode amplifier with the gain-boost technique, while the second stage is the class-AB output stage. The PGA was implemented in the 0.18 μm CMOS technology and achieved a 9.44 MHz unity-gain bandwidth (UGBW) and a 57.8° phase margin when driving the capacitor of 5.9 pF. An optimum figure-of-merit (FoM) value of 905.67 has been achieved with the proposed PGA. As the front-end amplifier of a high-precision ADC, it delivers a DC gain of 162.1 dB, the equivalent input noise voltage of 301.6 nV and an offset voltage of 1.61 μV. Within the frequency range below 60 MHz, the measured PSRR of ADC is below −70 dB with an effective number of bits (ENOB), namely 20 bits. Full article

Digital low-dropout (LDO) regulators are popular in research today as compact power supply solutions. This paper provides a unique approach to analyze digital LDO feedback mechanics and stability, to reduce voltage ripple and extend operating speed over the state-of-the-art. A novel error-subtracting counter is proposed to exponentially improve the response time of any digital LDO, to keep the loop stable outside the typical operating limits, and to increase power-supply rejection (PSR). This leverages the fact that digital LDOs are fundamentally one-bit relaxation oscillators in steady-state. Theory and simulations show how the analog-to-digital (ADC) and digital-to-analog converters (DAC) in these systems affect stability. When compromised, a digital LDO produces uncontrolled sub-clock oscillations at the output that the proposed error-subtracting counter removes. Full article

This work presents a novel, fully integrated low-dropout (LDO) regulator optimized for low-power applications with a wide load current range. By utilizing dynamic biasing to improve transient response, the LDO regulator achieves impressive performance with 0.26 $\mathsf{\mu }$V/mA load regulation (LDR) and 19.92 $\mathsf{\mu }$V/V line regulation (LNR). It also features a fast 8.6 $\mathsf{\mu }$s settling time during load transitions up to 30 mA and a low quiescent current of 6.3 $\mathsf{\mu }$A. The LDO regulator maintains a 1.8 V output for input voltages ranging from 2.1 V to 3.3 V, with a dropout voltage of 100 mV and supports load currents from 0.3 mA to 30 mA over a temperature range of −40 °C to +85 °C. The design, implemented in a standard 180 nm CMOS process, offers high accuracy and efficiency, making it a well-suited solution for battery-powered systems. Full article

Wireless sensor network (WSN) is an important component of healthcare. The design of the power management unit for WSN poses significant challenges, as it not only needs to achieve good current efficiency but also requires high power supply rejection (PSR) and good load transient performance. This paper presents a low-dropout regulator (LDO) with a low quiescent current and fast transient response to adequately meet the power supply requirements of WSN systems. To ensure system stability and reduce voltage spikes during load transients, an adaptive frequency compensation network is integrated into the circuit. Additionally, the LDO incorporates a level shifter that facilitates the bi-directional transmission of voltage signals across different power systems. The proposed LDO is designed and simulated in a 180 nm BCD process. It operates under a wide input voltage range from 0.8 V to 5.5 V, supports maximum load currents of up to 500 mA, and allows output voltages to vary from 0.8 V to 3.6 V by adjusting the feedback resistance. As a result of implementing the adaptive frequency compensation circuit, the overshoot and undershoot voltages at an output voltage of 1 V are measured to be only 23 mV and 5 mV, respectively. Moreover, the LDO achieves a PSR of −83 dB for bias voltage and −91 dB for input voltage at 1 kHz. The level shifter’s highest working frequency can reach 20 MHz under supply voltages (V_in = 1.65 V to 5.5 V; V_out = 3.6 V), thereby enabling high-speed data transmission. Finally, the LDO consumes a quiescent current of 42 μA while incorporating a bandgap reference circuit and other auxiliary circuits. Full article

In this paper, we propose an ultrascaled WS₂ field-effect transistor equipped with a Pd/Pt sensitive gate for high-performance and low-power hydrogen gas sensing applications. The proposed nanosensor is simulated by self-consistently solving a quantum transport equation with electrostatics at the ballistic limit. The gas sensing principle is based on the gas-induced change in the metal gate work function. The hydrogen gas nanosensor leverages the high sensitivity of two-dimensional WS2 to its sur-rounding electrostatic environment. The computational investigation encompasses the nanosensor’s behavior in terms of potential profile, charge density, current spectrum, local density of states (LDOS), transfer characteristics, and sensitivity. Additionally, the downscaling-sensitivity trade-off is analyzed by considering the impact of drain-to-source voltage and the electrostatics parameters on subthreshold performance. The simulation results indicate that the downscaling-sensitivity trade-off can be optimized through enhancements in electrostatics, such as utilizing high-k dielectrics and reducing oxide thickness, as well as applying a low drain-to-source voltage, which also contributes to improved energy efficiency. The proposed nanodevice meets the prerequisites for cutting-edge gas nanosensors, offering high sensing performance, improved scaling capability, low power consumption, and complementary metal–oxide–semiconductor compatibility, making it a compelling candidate for the next generation of ultrascaled FET-based gas nanosensors. Full article

An ultra-low quiescent current output-capacitor-less low dropout (OCL-LDO) regulator for power-sensitive applications is proposed in this paper. To improve the gain of the OCL-LDO feedback loop, the error amplifier employs a combination of a cross-coupled input stage for boosting the equivalent input transconductance and a negative resistance technique to improve the gain. Meanwhile, in order to address the issue of transient response of the ultra-low quiescent current OCL-LDO, a sub-threshold slew-rate enhancement circuit is proposed in this paper, which consists of a transient signal input stage and a slew-rate current increase branch. The proposed OCL-LDO is fabricated in a 0.18 $\mu$m CMOS process with an effective area of 0.049 mm². According to the measurement results, the proposed OCL-LDO has a maximum load current of 100 mA and a minimum quiescent current of 640 nA at an input voltage of 1.2 V and an output voltage of 1 V. The overshoot and undershoot voltages are 197 mV and 201 mV, respectively, and the PSR of the OCL-LDO is −72.4 dB at 1 kHz when the load current is 100 $\mu$A. In addition, the OCL-LDO has a load regulation of 7.6 $\mu$V/mA and a line regulation of 0.87 mV/V. Full article

Overshoot and undershoot caused by the current load impact the accuracy of the required output voltage and circuit performance. The transient response issue in existing low-dropout (LDO) regulators is a dynamic specification that must be addressed at the design stage. This transient response is influenced by system parameters such as stability and gain. The LDO regulator suggested in this study is designed to minimize the change in output voltage by considerably enhancing the gain using a dynamic dual buffer structure. A dynamic dual buffer is utilized to effectively control undershoot and overshoot. Under the conditions that the input voltage range is from 3.3 to 4.5 V, the maximum load current is 300 mA, the output voltage is 3 V, and the output of the proposed LDO regulator with the dynamic dual buffer structure has undershoot and overshoot voltages of 41 mV and 31 mV, respectively. That is, the output voltage of the proposed LDO regulator effectively provided and discharged an additional current suited for the undershoot/overshoot conditions to enhance the transient response characteristics. Furthermore, the electrostatic discharge (ESD) robustness characteristics of the proposed LDO regulator improved because of the silicon-controlled rectifier underlying the ESD protection device embedded in the output node and power line. Full article

This paper proposes a fast transient load response capacitor-less low-dropout regulator (CL-LDO) for digital analog hybrid circuits in the 180 nm process, capable of converting input voltages from 1.2 V to 1.8 V into an output voltage of 1 V. The design incorporates a rail-to-rail input and push–pull output (RIPO) amplifier to enhance the gain while satisfying the requirement for low power consumption. A super source follower buffer (SSFB) with internal stability is introduced to ensure loop stability. The proposed structure ensures the steady-state performance of the LDO without an on-chip capacitor. The auxiliary circuit, or transient enhancement circuit, does not compromise the steady-state stability and effectively enhances the transient performance during sudden load current steps. The proposed LDO consumes a quiescent current of 47 µA and achieves 25 µV/mA load regulation with a load current ranging from 0 to 20 mA. The simulation results demonstrate that a settling time of 0.2 µs is achieved for load steps ranging from 0 mA to 20 mA, while a settling time of 0.5 µs is attained for load steps ranging from 20 mA to 0 mA, with an edge time of 0.1 µs. Full article

This paper presents a compact Micro-Electro-Mechanical System (MEMS) microphone digital readout system. The system is characterized by a low-dropout regulator (LDO) and a pre-amplifier and programmable-gain amplifier (PPA)-less voltage controlled oscillator (VCO)-based $\Delta$$\Sigma$ modulation technique, which improve compactness and design scalability. Specifically, to improve signal accuracy and maintain loop stability without a gain-tuning range trade-off, an active low pass filter (ALPF) and a current mode feed-forward path (CMFFP) are incorporated in a VCO-based delta-sigma modulation loop. By means of VCOs and SCG phase variation robustness and current source array feedback (CSAFB), the system achieves a high power supply rejection ratio (PSRR) and gain tuning without the need to design an extra regulator and PPA. The design was fabricated using a 180 nm Bipolar-CMOS-DMOS (BCD) process and measured at a 1.2 V supply voltage. According to the measurement results, the signal-to-noise and distortion ratio (SNDR) achieves 62 dB@1 kHz with 40 dB gain and a 10 kHz bandwidth. Furthermore, PSRR@1 kHz is below −55 dB, and power dissipation is within 57 µW. Full article

Low dropout (LDO) regulators are crucial components in power management systems for portable, i.e., battery-powered, devices. However, the design of LDO regulators presents a challenging trade-off between dynamic performance, power consumption, and area efficiency. This paper proposes a novel LDO regulator design that addresses these challenges by employing the reverse nested Miller compensation (RNMC) with current buffers embedded within the own class AB high gain error amplifier (EA) topology, and a time response enhancement circuit (TREC). High-gain (>120 dB) class AB EA renders good regulation performance with enhanced dynamic performance. The proposed compensation scheme improves the gain bandwidth product (GBW) and stability of the regulator, while the TREC reduces overshoot and undershoot during load transients without additional steady-state power consumption. Post-layout simulations confirm the robustness of the proposed 180 nm CMOS design across a wide range of operating conditions, achieving a regulated output voltage of 1.8 V with 100 mV dropout, good load and line regulating performance, and excellent load transient response with reduced undershoot and overshoot at minimum power ($I_q$ = 13.8 μA) and area (314 μm × 150 μm) consumption. The proposed LDO regulator thus offers a compelling compromise between power consumption, area efficiency, and dynamic performance, making it highly suitable for portable applications. Full article

This paper proposes a self-supplied power management system to efficiently rectify and regulate the AC voltage received from wireless power transmission techniques to power or recharge biomedical devices. The proposed power management system comprises three integrated functional units, namely, a fully cross-coupled rectifier, a self-biased reference voltage, and a capacitor-less low-dropout regulator (LDO). To reduce the current complexity of designing capacitor-less LDOs, a new architecture based on a pair of diode-connected transistors at the load of the LDO is devised which alleviates the need for a large load capacitor. The proposed power management system is implemented in a 65-nm CMOS process with an active chip area of 0.0810 mm². Experimental results indicate that this system is capable of rectifying an AC signal up to 5 V at a frequency of 6.78 MHz. This rectified signal is then regulated to a fixed DC voltage of 1.75 V, while the load current can vary between 0 and 75 mA, with a maximum voltage dropout of 170 mV. Advantageously, the proposed power management system is significantly robust to temperature, as a 55 °C change in ambient temperature leads to only a 9% degradation in its overall performance. Furthermore, the ability of the power management system to drive low-power consumer electronics is demonstrated, and its superiority is evidenced by a performance comparison with the latest integrated power management systems presented in the literature. Full article

A double-edge-triggered digital low dropout regulator (DLDO) is proposed with a built-in adaptive voltage-controlled oscillator (VCO) clock (AVC) for a system-on-chip (SoC) application. To achieve a fast transient response, the main comparator generates the comparison result at the rising edge of the AVC, and this result is sampled by the coarse or fine bidirectional shifter register at the falling edge of the AVC. Furthermore, the clock frequency can be boosted from 8 MHz at the steady state to 50 MHz by the AVC when the output current suffers from a sudden change, and it can also be adjusted in real-time according to the output voltage, which avoids the oscillation phenomenon and decreases the power consumption during the recovery process. To further lower the power consumption, the self-clock comparator replaces the conventional static comparator in the transient detector. The post-simulation results show that the proposed DLDO consumes a quiescent current of 95.13 μA in the steady state, and drives a maximum load current of 25 mA at the supply power of 0.6 V with an active area of 0.053-mm² in a 180 nm CMOS process. When the load current jumps from 0.5 mA to 25 mA at the edge of 100 ps, the undershoot voltage and overshoot voltage are only 335 mV with the recovery time of 2.7 μs and 47.6 mV with the recovery time of 2.1 μs at the total on-chip capacitor of 50 pF, respectively, resulting in two competitive figures of merits (FoMs) than the previous works. Full article