Hybrid Radio-Frequency-Energy- and Solar-Energy-Harvesting-Integrated Circuit for Internet of Things and Low-Power Applications

Abstract

This paper proposes a hybrid energy-harvesting chip that utilizes both radio-frequency (RF) energy and solar energy for low-power applications and extended service life. The key contributions include a wide input power range, a compact chip area, and a high maximum power conversion efficiency (PCE). Solar energy is a clean and readily available source. The hybrid energy harvesting system has gained popularity by combining RF and solar energy to improve overall energy availability and efficiency. The proposed chip comprises a matching network, rectifier, charge pump, DC combiner, overvoltage protection circuit, and low-dropout voltage regulator (LDO). The matching network ensures maximum power delivery from the antenna to the rectifier. The rectifier circuit utilizes a cross-coupled differential drive rectifier to convert radio frequency energy into DC voltage, incorporating boosting functionality. In addition, a solar harvester is employed to provide an additional energy source to extend service time and stabilize the output by combining it with the radio-frequency source using a DC combiner. The overvoltage protection circuit safeguards against high voltage passing from the DC combiner to the LDO. Finally, the LDO facilitates the production of a stable output voltage. The entire circuit is simulated using the Taiwan Semiconductor Manufacturing Company 0.18 µm 1P6M complementary metal–oxide–semiconductor standard process developed by the Taiwan Semiconductor Research Institute. The simulation results indicated a rectifier conversion efficiency of approximately 41.6% for the proposed radio-frequency-energy-harvesting system. It can operate with power levels ranging from −1 to 20 dBm, and the rectifier circuit’s output voltage is within the range of 1.7–1.8 V. A 0.2 W monocrystalline silicon solar panel (70 × 30 mm²) was used to generate a supplied voltage of 1 V. The overvoltage protection circuit limited the output voltage to 3.6 V. Finally, the LDO yielded a stable output voltage of 3.3 V.

1. Introduction

Energy consumption and the use of wireless mobile networks have skyrocketed over the past two decades due to population growth and economic development [1]. Consequently, affordable and low-power radio-frequency (RF) integrated circuits are in high demand because of their central role in wireless communication systems [2]. These circuits are designed in the form of integrated, multifunctional systems-on-a-chip. Research on this topic has mainly focused on understanding the design fundamentals of RF integrated circuits and exploring the outcomes of combining these circuits with other charging sources to gain insights into their operation, particularly when used as wireless transceiver integrated circuits [3]. Previous studies have analyzed various components of RF-integrated circuits, such as voltage-controlled oscillators, mixers, and low-noise amplifiers. Studies have also examined the challenges involved in the testing of hybrid energy-harvesting systems (HEHSs) [4].

A complementary metal–oxide–semiconductor (CMOS) power management system was presented with wide-range RF for ultra-high-frequency wireless energy harvesting. This system uses a power-aware rectifier and operates based on an adaptive DC–DC conversion ratio to scavenge energy efficiently and avoid sudden power loss due to environmental disturbance. At high input power (greater than −9 dBm), the proposed architecture improved efficiency by approximately 15% compared with a system comprising a conventional rectifier followed by a linear regulator [5]. In a subsequent study, a Dickson voltage multiplier was adopted as the RF voltage rectifier, and a buck–boost converter was used as the DC combiner. The output DC voltage was programmable, and the harvesting system was fabricated using a 0.18 µm CMOS process [6].

A technical comparison with alternative converter topologies is provided here to clarify the rationale behind the selected approach. Alternative techniques such as boost, flyback, and single-ended primary inductor converter (SEPIC) topologies utilize inductors to form their respective converter structures. Inductors are typically more suitable for off-chip applications, particularly in large-scale energy-harvesting systems. However, they are difficult to implement in standard CMOS processes due to their large on-chip area requirements and high parameter variation. According to a search conducted in the IEEE Xplore Digital Library, only one conference paper employing the flyback converter for energy harvesting applications was published in 2014 [7]. In contrast, 194 papers have been published on RF energy-harvesting systems using boost converters between 2006 and 2025 [8], indicating the widespread adoption of the boost converter in RF energy-harvesting integrated circuits. With regard to the SEPIC converter, a total of 329 papers have been published across various research domains. However, none of them reported the integration of a SEPIC converter with an RF energy-harvesting system [9]. In summary, although the boost converter is considered suitable for RF energy harvesting applications, both flyback and SEPIC converters require further investigation to determine their viability in this context. Nevertheless, this study did not adopt the boost converter due to its large chip area and high variability. Instead, a three-stage cross-coupled differential-drive (CCDD) rectifier circuit was employed, consisting of six NMOSFETs and six PMOSFETs [10].

A recent study proposed a hybrid RF/solar energy-scavenging system composed of a highly efficient dual-band RF energy harvester coupled with a solar cell. A Schottky diode (SMS-7630) was used as a rectifying element, and a monocrystalline solar cell (SLMD121H10L) was used for harvesting solar energy [11]. In a subsequent study, a solar cell and antenna, which is capable of harvesting ambient electromagnetic energy, were combined in a hybrid energy-harvesting circuit [12]. A hybrid RF–solar energy harvester was engineered on the basis of a newly designed RF energy harvester and an off-the-shelf solar panel with a boost converter [13]. A flexible and wearable hybrid RF–solar energy-harvesting system was proposed for powering wearable electronic devices. This harvesting system comprises a flexible transparent antenna, a flexible transparent rectifying circuit, and an amorphous silicon solar cell [14]. A power harvester with a Schottky diode and a photodiode was designed to cooperatively harvest ambient RF and solar energy [15]. The next generation of devices can sustain themselves without a battery by harvesting energy. An energy-harvesting design and analysis model is thus presented to collect solar and RF energy and store it for wireless sensor network applications. The viability of the model was assessed using two microcontroller-based implementations [16]. The following section describes the circuit implementation of the HEHS. Simulation results are presented in Section 3, and the conclusions are presented in Section 4.

2. Circuit Implementation of Hybrid Energy-Harvesting System

Figure 1 illustrates the architecture of the proposed HEHS, comprising a matching network, an RF–DC rectifier, a charge pump, a DC voltage combiner, an overvoltage protection (OVP) circuit, and a low-dropout linear voltage regulator (LDO) [17]. The HEHS receives RF signals through the antenna at a frequency of 0.915 GHz, Powercast Model TX91501, Taipei City, Taiwan. First, the balun (Murata, Kyoto, Japan) and matching network convert the RF signal into a differential signal to maximize power transformation. The RF–DC rectifier circuit converts the RF signal into a DC voltage. Meanwhile, an additional energy source (solar) is fed to the HEHS to serve as a secondary supply voltage. The charge pump circuit converts the applied solar energy into a DC voltage. The two converted DC voltages are merged by the DC voltage combiner. An OVP circuit is connected to the output of the DC voltage combiner to offer protection from overvoltage. Finally, the LDO generates a stable DC voltage for applications related to the Internet of Things and low-power applications. In this system, the RF energy is always low because it is received through the antenna; by contrast, the solar energy is stable and of greater use to the system.

2.1. Balun’s Function

The RF antenna only transmits a single-ended signal; therefore, a balun converts the received single-ended signal into a differential signal. Figure 2 highlights the position of the balun used in the HEHS: between the antenna and the matching network. A loss of conversion efficiency of approximately 10% is incurred at the balun (Figure 2). Furthermore, the input impedance is prone to variations because of the microstrip line and also because the balun is expected to provide information on the impedance ratio. The actual impact of the balun on the chip must be measured online, and the simulated input impedance of the antenna must be 50 Ω.

2.2. Matching Network

A matching network is crucial because it guarantees that the system’s input impedance matches the antenna’s impedance of 50 Ω. The RF energy-harvesting system operates at a frequency of 0.915 GHz, which must be appropriately matched with the impedance of 50 Ω. The matching network is completed using capacitors and inductors (Murata Manufacturing, Kyoto, Japan). The matching network ensures optimal power transfer from the antenna to the rectifier and facilitates an increase in the voltage to minimize energy loss and enhance overall conversion efficiency. Figure 3 shows an ideal impedance conversion component that couples the load Y_L to the input impedance Z_in. For simplification, all components are assumed to be loss-free [2]. If the input voltage v_S is sinusoidal, then the input signal can be expressed in terms of the peak voltage V_s as follows:

$$v_s=V_s\cdot \cos \omega t$$

(1)

The input and output powers can be expressed as follows:

$$P_{in}={\displaystyle \frac{1}{2}}\times {\left|{\displaystyle \frac{Z_{in}}{R_s+Z_{in}}}\times v_s\right|}^2\times {\Re }_e\left\{Y_{in}\right\}={\displaystyle \frac{1}{2}}{\left|{\displaystyle \frac{1}{1+Y_{in}{R}_s}}\right|}^2{v}_s^2{\Re }_e\left\{Y_{in}\right\}$$

(2)

$$P_{out}={\displaystyle \frac{1}{2}}{v}_{out}^2{\Re }_e\left\{Y_L\right\}$$

(3)

where v_s and v_out represent magnitudes of the input and output voltages, respectively; R_S represents the internal resistance of the input source; Y_in represents input conductance; Y_L represents load conductance; and ℜ_e is the real part operator.

Suppose the input impedance Z_in is matched to the internal resistance R_s (Z_in = 1/Y_in = R_s), and the input power is completely transmitted to the output power (P_in = P_out). In that case, the relationship between v_out and v_s can be expressed as follows:

$${\displaystyle \frac{1}{8}}{v}_s^2{\Re }_e\left\{Y_{in}\right\}={\displaystyle \frac{1}{2}}{v}_{out}^2{\Re }_e\left\{Y_L\right\}\Rightarrow {\displaystyle \frac{v_{out}}{v_s}}={\displaystyle \frac{1}{2}}\sqrt{{\displaystyle \frac{{\Re }_e\left\{Y_{in}\right\}}{{\Re }_e\left\{Y_L\right\}}}}$$

(4)

As shown in Figure 3, the input impedance Z_in can be expressed as follows:

$$\begin{array}{c}{Z}_{in}=j{X}_2+{\displaystyle \frac{1}{Y_{in}^{\text{'}}}}=j{X}_2+{\displaystyle \frac{1}{j{B}_1+\left(G_L+j{B}_L\right)}}\\ ={\displaystyle \frac{G_L-j\left(B_1+B_L\right)+j{X}_2\left[G_L^2+{\left(B_1+B_L\right)}^2\right]}{G_L^2+{\left(B_1+B_L\right)}^2}}\end{array}$$

(5)

and

$${\displaystyle \frac{v_{out}}{v_s}}={\displaystyle \frac{1}{2}}\sqrt{{\displaystyle \frac{{\Re }_e\left\{Y_{in}\right\}}{{\Re }_e\left\{Y_L\right\}}}}={\displaystyle \frac{1}{2}}\sqrt{{\displaystyle \frac{\raisebox{1ex}{$G_L^2+{\left(B_1+B_L\right)}^2$}\!\left/ \!\raisebox{-1ex}{$G_L$}\right.}{G_L}}}={\displaystyle \frac{1}{2}}\sqrt{1+{\left({\displaystyle \frac{B_1+B_L}{G_L}}\right)}^2}$$

(6)

where jX₂ and jB₁ represent the impedance of the series inductor (L_s) and the susceptance of the parallel capacitor (C_p), respectively, in the L-section matching network. Similarly, G_L and jB_L denote the conductance of the parallel resistor (R_L) and the susceptance of the parallel capacitor (C_L), respectively, in the load.

Figure 4 illustrates the matching network, which is located between the antenna and the N-channel metal–oxide–semiconductor (NMOS) rectifier. The impedance of the Industrial, Scientific, and Medical (ISM) 0.915-GHz antenna is approximately 50 Ω, whereas the input impedance of the three-stage modified NMOS rectifier is equal to 50 × (0.427 − j × 3.102) Ω. A matching network of (28.71 − j × 154.2) Ω is added to guarantee that the input impedance Z_in of the rectifier with the matching network is approximately 50 Ω. The matching network, composed of an inductor (LQG15HS_02, Murata Manufacturing) and a capacitor (GRM15, Murata Manufacturing), is simulated using ADS software (2023 Product, Keysight, Santa Rosa, CA, USA).

2.3. RF-DC Bridge Rectifier

The “full-wave bridge rectifier” is the most common full-wave rectification circuit that rectifies the desired DC voltage using the input signal’s positive and negative half-cycle signals [18]. In the full-wave bridge rectifier, transistors are connected in a diode manner. During positive half-cycle operation, current flows from V_in+ to the load capacitance C_L through the NMOS transistor, whereas during negative half-cycle operation, current flows from V_in− to the load capacitance through the positive-channel metal–oxide–semiconductor (PMOS) transistor. Therefore, the DC voltage can be effectively rectified regardless of whether the rectifier circuit operates in a positive or negative half-cycle. The output voltage can be expressed as follows:

$$V_{out}=2\left(V_{in}-V_{th}\right)$$

(7)

where V_in represents the peak magnitude of the RF signal, and V_th represents the threshold voltage of the metal–oxide–semiconductor field-effect transistor (MOSFET).

Figure 5 illustrates an external V_th cancellation rectifier circuit whose conversion efficiency has been increased by adding a critical voltage V_b between the gate and drain terminals of the transistor [19]. The output voltage V_out can then be expressed as follows:

$$V_{out}=2\left(V_{in}+V_b-V_{th}\right)$$

(8)

If V_b equals V_th, then the output voltage V_out is twice the input voltage V_in. Through careful changes to the critical voltage V_b, the threshold voltage V_th can be cancelled to improve the voltage conversion efficiency. However, introducing an external bias voltage to complete the cancellation of V_th is not ideal. Figure 6 presents a circuit design for the self-cancellation of the threshold voltage V_th [20]. As shown in Equation (8), when the critical bias voltage V_b is equal to the threshold voltage V_th, the output voltage V_out becomes 2 × V_in. The critical bias voltage V_b can be implemented using the storage capacitors C_1a or C_2a. The voltages stored in C_1a and C_2a provide the necessary cancellation voltages V_b1 and V_b2, which are used to eliminate the threshold voltages V_th1 and V_th2 of transistors M₁ and M₂, respectively. The self-cancellation of V_th is achieved with the aid of two off-chip resistors, R₁ and R₂.

Figure 7 shows a single-stage cross-coupled differential drive (CCDD) rectifier circuit [21], which is composed of the CMOS full-wave bridge rectifier and the circuit for the self-cancellation of V_th. The advantages of the proposed CCDD rectifier (CCDDR) are that the input signal can be utilized effectively in each cycle, and the critical voltage can be reduced. When the RF+ terminal is connected to a high-level signal and the RF− terminal connected to a low-level signal, the transistors M_P1 and M_N2 conduct electricity not only to provide a charging current from RF+ to RF− but also to increase the output voltage V_out (Figure 8a). Conversely, when RF− is at a high potential and RF+ at a low potential, the transistors M_P2 and M_N1 conduct electricity to provide a charging path from RF− to RF+, thereby increasing the output voltage V_out. C₁ and C₂ are used as voltage compensation for the transistor gate, and C₃ is a regulated capacitor that supplies a stable voltage to the V_out terminal (Figure 8b).

Figure 9 depicts the equivalent circuit when RF+ is positive for a half-cycle. The peak voltages of the RF+ and RF− signals, the capacitance voltages of C₁ and C₂, and the required minimum voltages of PMOS and NMOS are represented as +V_p, −V_P, +V_CP, −V_CP, |V_th,p|, and V_th,n, respectively. According to Kirchhoff’s voltage law, the charged voltage of V_C3 can be expressed as follows:

$$\left\{\begin{array}{c}{V}_{C3}\left(+\right)=V_P-V_{CP}-\left|V_{th,p}\right|\\ V_{C3}\left(-\right)=-V_P-V_{CP}+V_{th,n}\end{array}\right.$$

(9)

$$V_{C3}=V_{C3}\left(+\right)-V_{C3}\left(-\right)=2V_P-\left(\left|V_{th,p}\right|+V_{th,n}\right)$$

(10)

During the conduction process, the MOSFET operates as a switch in the linear region. The on-switching impedances of the PMOSFET (M_P1) and NMOSFET (M_N2) can be expressed as shown in Equations (11) and (12).

$$r_{ON\_MP1}={\displaystyle \frac{1}{{\mu }_p{C}_{ox}\left(\raisebox{1ex}{$W$}\!\left/ \!\raisebox{-1ex}{$L$}\right.\right)\left[\left(\left|V_{gsp}\right|-\left|V_{th,p}\right|\right)-\left|V_{dsp}\right|\right]}}$$

(11)

$$r_{ON\_MN2}={\displaystyle \frac{1}{{\mu }_n{C}_{ox}\left(\raisebox{1ex}{$W$}\!\left/ \!\raisebox{-1ex}{$L$}\right.\right)\left[\left(V_{gsn}-V_{th,n}\right)-V_{dsn}\right]}}$$

(12)

where μ_p and μ_n represent carrier mobility of PMOS and NMOS, respectively; C_ox represents the parasitic capacitance of the gate oxide; W and L represent gate width and length of MOSFET, respectively; V_gs represents the voltage difference between the gate and the source; V_ds represents the voltage difference between the drain and the source; and V_th represents the threshold voltage of the transistor.

Figure 10 depicts a multi-order CCDD rectifier circuit, which is composed of many single-stage CCDD rectifier circuits arranged in cascade topology. The purpose of a multi-order CCDD rectifier circuit is to provide the load with enough voltage for the intended application. In general, the output voltage increases with the order of the CCDD rectifier circuit. However, an increase in the order is accompanied by an increase in the number of switch transistors used, resulting in higher losses in the form of leakage voltages. Therefore, the selection of a useful rectifier circuit is based on the system’s conversion efficiency and output voltage. According to Equation (10), the output voltage of the N-order CCDD rectifier circuit can be expressed as follows:

$$V_{out,N}=2N{V}_p-N\left(V_{th,p}+V_{th,n}\right)$$

(13)

This study employs a three-stage CCDD rectifier circuit having six NMOSFETs and six PMOSFETs (in Figure 11) [10]. The circuit contains six nominal N-type transistors and six nominal P-type transistors in the diode-connected form as well as nine metal–insulation–metal capacitors. All transistors and capacitors are identical. The bottom plate, marked with a bold line, exhibits a large parasitic capacitance and is grounded to reduce loss. If the RF signal is received through the ISM-0.915-GHz antenna, it is fed into the CCDD rectifier through the balun and impedance matching network. The load capacitor C₉ of the third CCDD rectifier stores enough DC voltage to complete signal conversion and suppress ripple voltage [22].

2.4. Solar Energy (PV Cell)

A photovoltaic cell, commonly called a solar cell, is a semiconductor device that converts sunlight directly into electricity. Figure 12 illustrates a photovoltaic cell composed of two semiconductor layers: an N-type layer with an abundance of electrons and a P-type layer with an abundance of holes. Incoming photons strike the photovoltaic cell and are absorbed, resulting in the excitation of electrons in the N-type layer and their migration across the junction to the P-type layer. The movement of electrons toward the front surface of the photovoltaic cell creates an imbalance of electrical charge between the front and back surfaces of the cell, resembling the negative and positive terminals of a battery and creating a voltage potential. Electrical conductors on the photovoltaic cell absorb the electrons. When these conductors are connected in an electrical circuit to an external load, such as a battery, electricity flows through the circuit [23]. Figure 13 shows the most popular equivalent circuit of a solar photovoltaic cell. It includes a current source I_PH, one diode with voltage V_D and current I_D, and two resistors: one in series (R_SE) and one in parallel (R_P) [24]. Multiple photovoltaic cells can be connected in parallel or in series to increase the output power and voltage. Solar panels differ in terms of their manufacturing technology and the corresponding efficiencies. The conversion efficiency of the solar panels available in the market ranges from 16% to 23%. This study used the poly-passivated emitter (Poly PERC, Shajing, Shenzhen, China) and rear contact solar panel, which has a lower conversion efficiency than the N-type-integrated back contact panel.

2.5. Dickson Charge Pump

Figure 14 displays a schematic of the Dickson charge pump employed in this study. This pump not only enhances the input power of the solar cell but also generates the required output voltage through multiplication. The N-type MOSFET is configured in a diode-connected form. During the charging phase, the input voltage V_in is supplied to the first stage of the charge pump to charge the first capacitor C₁. In the transfer phase, C₁ retains its voltage, and the second capacitor C₂ gets charged. In the next cycle, the charging process is repeated, and the stored voltage is increased. Finally, the output voltage V_out is obtained from the last load capacitor C_L [22].

2.6. DC Voltage Combiner

Figure 15 displays a schematic of a DC voltage combiner circuit, which includes two energy sources: RF energy (RF_in) and solar energy (PV_in). The combination of the two voltages is achieved through the use of a noninverting summing amplifier, which comprises an operational amplifier with two input resistors, R₁ and R₂, connected to its noninverting input terminal (+). The inverting input terminal (−) is typically connected to the ground or a reference voltage (V_ref). The two input resistors, R₁ and R₂, are connected to two input voltage sources, V₁ and V₂, respectively. The noninverting input terminal draws negligible current because it is connected to a high-input impedance, resulting in virtual grounding at the noninverting and inverting terminals (i.e., V_A = V_B). The output voltage (V_o) is the sum of the weighted input voltages, determined by the ratio of the feedback resistance (R_f) to the respective input resistances (R₁ or R₂). Based on these weighting factors, the summing amplifier combines the input voltage sources, RF_in (V₁) and PV_in (V₂), to produce a summed output voltage [25].

$$V_o=\left(1+{\displaystyle \frac{R_f}{R}}\right)\times \left({\displaystyle \frac{R_2}{R_1+R_2}}{V}_1+{\displaystyle \frac{R_1}{R_1+R_2}}{V}_2\right)$$

(14)

where V₁ represents an RF energy source (RF_in) and V₂ represents a solar energy source (PV_in). Figure 16 presents a circuit diagram of the adopted two-stage operational amplifier with compensation. The C_C is chosen large enough to position the dominant pole properly, and the R_Z moves the right half plane to zero [26].

2.7. Overvoltage Protection (OVP) Circuit

The OVP circuit is a critical component of the RF- and solar-energy-harvesting system. When the output voltage of the RF–DC or DC–DC converter is too high in the near-field energy region, the OVP circuit helps prevent the breaking or burning of the harvesting chip. Figure 17 shows a schematic of an OVP circuit [17]; the diode-connected form of the transistor M₇ is utilized to fix the voltage V_B, and the voltage V_A is decided using the division between the two transistors M₁ and M₂. An increase in the output voltage V_dc will create a voltage difference between V_A and V_B, elevating the amplifier output voltage. Consequently, the M_O transistor switches on and conducts the current to the ground, further stabilizing V_A until V_A = V_B. The M_O current is fixed to stabilize the rectifier output voltage V_dc. The differential output voltage V_O is used to control the conduction current I_O of the output transistor M_O. The larger the DC voltage V_dc, the larger the conduction current I_O. Thus, a stable DC output voltage is generated. The two bias voltages V_A and V_B could be expressed as follows:

$$V_A=V_{dc}-\left(\left|V_{OD1}\right|+\left|V_{th,p1}\right|\right)-\left(\left|V_{OD2}\right|+\left|V_{th,p2}\right|\right)$$

(15)

$$V_B=V_{OD7}+V_{th,n7}$$

(16)

where V_ODi, V_th,ni, and V_th,pi represent the overdrive voltage of the ith MOSFET, threshold voltage of the ith NMOS, and the threshold voltage of the ith PMOS, respectively. Initially, the two bias voltages were identical (i.e., V_A = V_B). The DC output voltage of the DC voltage combiner can be expressed as follows:

$$V_{dc}=\left|V_{gsp1}\right|+\left|V_{gsp2}\right|+V_{gsn7}$$

(17)

where V_gspi and V_gsni represent the gate-source voltages of the ith diode-connected PMOS and NMOS, respectively.

2.8. Low-Dropout Linear Voltage Regulator

In hybrid energy-harvesting systems, a stable and clean output voltage with minimal power loss and low energy consumption is crucial, and the low-dropout regulator (LDO) plays a vital role in achieving this objective. An LDO circuit is proposed in [14], which consists of a CMOS reference voltage, a current source, an error amplifier, a feedback network, frequency compensation, and a load. The operating principle of the LDO circuit is as follows: the positive terminal (+) of the error amplifier is connected to a precise CMOS reference voltage (V_REF), while the negative terminal (−) is connected to the feedback voltage (V_FB) from the output. By comparing V_REF and V_FB, the error amplifier generates an amplified error signal to adjust the gate voltage of the pass transistor. When the feedback voltage exceeds the reference voltage, the error amplifier produces a higher gate voltage, which reduces the output current of the pass transistor. As a result, the output voltage decreases along with the output current through the load, which includes equivalent resistors [27].

3. Simulation Results

The solar energy system operates at high voltage, and its leakage current may damage the proposed RF harvesting chip. This poses a challenge to integrating both systems into a single chip. As a result, this study is presented as a simulation-based work. Experimental measurements are not included due to these integration challenges. Further efforts are needed to mitigate these issues, particularly through the development of appropriate protection circuitry. Figure 18 shows the DC and AC leakage voltages of the solar energy harvesting system. It can be observed that the leakage voltages ranges from 10.3725 V to 12.7125 V. These leakage voltages damage the RF chip, as its maximum supply voltage is approximately 1.8 V under the 0.18 μm CMOS process. Future work will focus on designing a protection circuit between the RF chip and the solar chip.

As shown in Figure 4, a matching network of (28.71 − j × 154.2) Ω is added to the system to guarantee that the input impedance Z_in of the rectifier is approximately 50 Ω. The matching network was simulated using ADS software. Figure 19 illustrates the parameter S₁₁ of the matching network. The input return loss S₁₁ at the center frequency of 0.915 GHz is approximately −30.161 dB, lower than −25 dB. The simulated input return loss satisfies the required specification.

As shown in Figure 11, the RF input signal is received through the ISM–0.915–GHz antenna and fed into the three–stage CCDD rectifier through the balun and matching network. Let us regard the input RF signal as a cosine waveform (i.e., RF_in = V_P cosωt, with a peak amplitude V_P and an input frequency f = ω/2π = 1/T). The load capacitor C₉ stores enough voltage to complete the signal conversion and suppress the ripple voltage. When the rectifier circuit operates in a positive half–cycle (t = 0, T, 2T, …), the transistors M_P1, M_N2, M_P3, M_N4, M_P5, and M_N6 conduct electricity, and the forward current flows into C₃, C₆, and C₉. The DC output voltage V_out is obtained at C₉. When the rectifier circuit operates in a negative half–cycle (t = T/2, 3T/2, …), the transistors M_N1, M_P2, M_N3, M_P4, M_N5, and M_P6 conduct electricity, and a backward current flows into C₃, C₆, and C₉. An output voltage V_out is obtained at C₉. The conversion efficiency of the differential three-stage CCDD rectifier circuit is twice that of a single-ended rectifier circuit. All transistors and capacitors continue to operate as described above regardless of the number of stages of the voltage doubler and rectifier. If the number of stages is three, the approximate output voltage is calculated as follows: V_out = 6 × V_P − 3 × (|V_th,p| + V_th,n) (V). Figure 20 shows the simulated conversion efficiency of the adopted differential three-stage CCDD rectifier circuit. The maximum conversion efficiency was approximately 41.68% at an input RF power of −5.1 dB.

Furthermore, a Dickson charge pump is utilized to boost the input power of the solar cell and to generate the required output voltage through multiplication. Figure 21 presents the simulation results of operating a Dickson charge pump. When the input voltage is approximately 1.0 V, the output voltage is approximately 1.8 V at a phase frequency of 150 MHz. Next, a DC voltage combiner is used to merge the outputs of the two sources, namely, RF energy and solar energy. The output voltage (V_o), given by the sum of the weighted input voltages, is determined from Equation (14). Figure 22 shows the simulation results of operating a summing amplifier. If the output voltages of both RF and solar power are 1.8 V each, they can be combined using the summing amplifier to yield a combined output voltage V_o of approximately 3.552 V at identical resistances (R_f = R and R₁ = R₂).

Figure 23 illustrates the simulation results of an OVP circuit. A higher input RF or solar voltage corresponds to a larger voltage output by the DC voltage combiner. Once the output voltage reaches the rated voltage of 3.6 V, the excess voltage is dissipated by the proposed OVP circuit. The conductional current I_o of the output transistor M_o surges sharply to stabilize the output voltage of 3.6 V.

Finally, an LDO is employed to obtain a stable and clean output voltage with low power loss and low power consumption. Figure 24 shows the simulated output voltage of an LDO. In this simulation, the reference voltage V_REF is approximately 1.75074 V, and the feedback voltage V_FB is approximately 1.74286 V. The LDO circuit generates a steady output voltage of approximately 3.2996 V.

After the designed functions were verified, the custom design was fabricated on a chip. Figure 25 presents the completed layout of the proposed hybrid RF- and solar-energy-harvesting chip, composed of the CCDD rectifier, Dickson charge pump, DC voltage combiner, OVP circuit, LDO circuit, and reference voltage circuit. The chip area is approximately 0.225 × 0.225 mm².

Table 1. Summary of performance and its comparison with those of other RF-DC rectifiers, RF energy-harvesting ICs, and hybrid energy-harvesting ICs.

Reference (Year)	[28] (2019)	[29] (2019)	[30] (2025)	[31] (2019)	[32] (2021)	This Work
Technology	180 nm	180 nm	65 nm	65 nm	65 nm	180 nm
Harvesting sources	RF	RF	RF	PV + RF + TEG	PV + TEG + WiFi	RF + Solar
RF frequency (MHz)	2300	900	953	-	2400	915
Input power range (dBm)	−20~+15	−20~+0	−25~0	-	0.5 V	−5~+20
Rectifier topology	2-stage CCR	3-, 4-, and 7-stage CCDDR	Fully self-biased	2-stage CCCP	CCCP	3-stage CCDDR
Peak PCE (rectifier)	7.6%	42.3%	60.5%	41.9% (RF) 76.1% (DC Adder)	69.0% (Combiner)	41.6% (RF) 78% (Solar)
RF output voltage (V)	0.6/1.7	1.3	1.4	0.5	0.92	1.8
Solar output voltage (V)	-	-	-	0.5	6.30	1.8
Hybrid harvester (V)	-	-	-	1.0	-	3.2996
Chip area (mm2)	1.109	-	-	0.086	-	0.050625
Remarks	Poor	Average	Good	Good	Excellent	Good

summarizes the evaluation results of the proposed HEHS compared with other RF–DC rectifiers and hybrid energy-harvesting integrated circuits. The chip area, measuring 0.050625 mm², is the smallest among all the previously reported designs selected for comparison [28,29,30,31,32]. The input power range (dBm) achieved in this study is also superior to that of the selected designs, and the maximum power conversion efficiency (PCE) obtained is comparable to those reported in previous studies [30,32]. Moreover, the output voltages of the RF, solar, and hybrid energy harvesters reported in this study exceed those of all the selected references. Although several RF–DC rectifiers have been studied in recent years, research on system integration, such as RF energy-harvesting integrated circuits (ICs), remains limited. The proposed hybrid energy-harvesting IC features low power consumption and a compact chip area. Labor costs can be significantly reduced by eliminating the need for future battery replacements. At close range, the proposed IC can be used to trickle-charge low-power devices such as GPS modules, tracking tags, wearable sensors, and consumer electronics. At longer ranges, the transmitted power can support battery-based or battery-free remote sensors for factory automation, structural health monitoring, and industrial control. It is worth noting that a recent trend in hybrid energy-harvesting systems focuses on the integration of photovoltaic (PV) cells, RF energy, and thermoelectric generators (TEGs), which can be fabricated using a 65 nm process [30,31,32]. The peak PCEs of the aforementioned hybrid energy-harvesting chips are comparable to those in this study: 76.1% using a DC adder, 69.0% with a power combiner, and 78% with a DC voltage combiner. These systems can convert otherwise wasted power into additional electrical energy using the cross-coupled charge pump (CCCP) operation, thereby enhancing conversion efficiency or supplementing the main power source to extend service life. In future work, the power conversion efficiency of the hybrid energy-harvesting chip could be further improved by reducing the power consumption of each proposed circuit and integrating it with various power sources.

4. Conclusions

This study presents a hybrid energy-harvesting chip that combines an ISM-0.915-GHz RF energy acquisition system with a solar photovoltaic cell. A CCDD rectifier is employed to convert the RF signal into DC voltage. The input solar voltage is then boosted from 1.0 to 1.8 V using a Dickson charge pump. A DC voltage combiner is used to combine the RF energy with solar energy. An OVP circuit is connected at the rectifier’s output to protect the LDO and to limit the output voltage to within 3.6 V. Finally, an LDO is utilized to ensure a stable output voltage of 3.2996 V. The simulation results indicate that the RF rectifier circuit achieves a maximum power conversion efficiency of 41.6% and a steady output voltage of 3.2996 V. This study demonstrates the effectiveness of the proposed HEHS in efficiently harvesting and managing RF and solar energies. Its potential applications include charging low-power devices such as IoT devices, wearable electronics, and biomedical systems [33]. Future work will focus on integrating the RF energy-harvesting system with advanced conversion techniques, including maximum power point tracking (MPPT), dipole antenna arrays, rectenna arrays, and harmonic-based applications.