A Fast Transient Response Capacitor-Less LDO with Transient Enhancement Technology

This paper proposes a fast transient load response capacitor-less low-dropout regulator (CL-LDO) for digital analog hybrid circuits in the 180 nm process, capable of converting input voltages from 1.2 V to 1.8 V into an output voltage of 1 V. The design incorporates a rail-to-rail input and push–pull output (RIPO) amplifier to enhance the gain while satisfying the requirement for low power consumption. A super source follower buffer (SSFB) with internal stability is introduced to ensure loop stability. The proposed structure ensures the steady-state performance of the LDO without an on-chip capacitor. The auxiliary circuit, or transient enhancement circuit, does not compromise the steady-state stability and effectively enhances the transient performance during sudden load current steps. The proposed LDO consumes a quiescent current of 47 µA and achieves 25 µV/mA load regulation with a load current ranging from 0 to 20 mA. The simulation results demonstrate that a settling time of 0.2 µs is achieved for load steps ranging from 0 mA to 20 mA, while a settling time of 0.5 µs is attained for load steps ranging from 20 mA to 0 mA, with an edge time of 0.1 µs.


Introduction
Power management ICs (PMICs) are essential components in electronic devices that require efficient power management [1].Low-dropout regulators (LDOs) are preferred over other voltage regulators due to their low noise, low ripple, low quiescent current and high power supply rejection ratio (PSRR) [2][3][4][5].To satisfy the different voltage regulation requirements of various modules in a single system-on-chip (SOC), multiple voltage regulators can be integrated on the same chip.This approach can reduce the power dissipation and improve the overall efficiency of the system.In SoC designs, LDOs are commonly used to supply power to analog or mixed-signal modules, which are particularly sensitive to noise and voltage fluctuations [6][7][8].However, the traditional LDO architecture relies on a large capacitor, which occupies a large area and reduces circuit integration.Removal of this large off-chip capacitor will inevitably degrade the performance requirements of the LDO, especially stability, transient response and PSRR.Therefore, in recent years, capacitor-less LDOs (CL-LDOs) have been widely studied and reported [9][10][11].
A series of techniques have been proposed to improve the transient response of CL-LDO [12][13][14][15][16][17].Using a flipped voltage follower (FVF) to separate the dominant poles in conventional LDO is one of the most popular methods.The FVF and overshoot detection circuit used in [12] reduce the overshoot/undershoot voltages of LDO and achieve fast settling times during load steps.The push-pull amplifier is a kind of architecture that can be used to provide a fast response to load and line transients [13,15].The LDO with Class-AB OTA in [13] provides not only a fast response to load and line transients, but also handles a wide range of load capacitors, while the push-pull output stage-based LDO in [15] can achieve a 2.7 µs settling time with the load current switching from 100 pA to 100 mA.A dynamic biasing technique is widely used, whereby the bias current of the LDO is adjusted based on the load current.This can improve the efficiency of the LDO and reduce the power dissipation.To enhance both the transient and stability, Li et al. proposed a CL-LDO based on dual-active feedback frequency compensation that ultimately guarantees stable operation in a load range of 0 to 100 mA [14].In [17], the authors use modified Miller compensation with the insertion of a sensor amplifier stage to inject more transient current in the biasing circuit.This method feeds the regulator to rapidly charge the power PMOS gate capacitance and improves the fast transient response.
This work proposes a novel CL-LDO circuit with a fast transient response.Section 2 demonstrates the complete architecture with a rail-to-rail input, push-pull output (RIPO) two-stage amplifier and a super source follower buffer (SSFB) and analyzes the stability and transient response.Section 3 presents a design example, validated through simulation results, and compares this work with others.Section 4 summarizes the conclusion.

Conventional Topology of LDO
The traditional LDO topology with an off-chip capacitor depicted in Figure 1 exhibits three poles and a left-half-plane zero without the need for an auxiliary circuit.The stability of this system is ensured by the presence of a left-half-plane zero, which is generated by the output capacitor with a capacitance in the microfarad range and its equivalent resistance.Additionally, Equation (1) establishes that the dominant pole is positioned at the output node.The remaining two poles are positioned at the output of the amplifier and feedback resistance.The removal of this bully output capacitor poses a greater challenge to the stability.To enhance the stability, compensation capacitors are added in the auxiliary circuit.The spike output voltage in the LDO when there are sudden changes in the load current from other cells is also depicted in Figure 1.The unity gain frequency (UGF) is one of the most essential factors of transient performance.To achieve a large UGF, prior studies have proposed an architecture incorporating a buffer as the auxiliary circuit to decouple the high impedance from the EA's output and the large capacitance from the M P 's input.Additionally, the response time T R [12] of the LDO can be approximated as Equation (2): where BW denotes the loop bandwidth, C par represents the parasitic cap, ∆V G refers to the required voltage change and I G represents the slewing current at M P 's gate.The buffer with a low output resistance can offer a high slewing current to rapidly respond to the load step.

Proposed RIPO and SSFB
A rail-to-rail input of the RIPO amplifier is shown in Figure 2a.The PMOS input pair M 1 -M 2 is utilized to achieve the negative supply rail, while the NMOS input pair M 3 -M 4 is employed to reach the positive supply rail.The transistors M 5 to M 8 are used as level shifters for the PMOS input pair, thereby expanding the negative input range to ensure that the PMOS input pair operates in the saturation region.The tail currents of two complementary input pairs are supported by M 9 and M 10 .The positive supply rail extends from Vcm+ to VDD, while the negative supply rail spans from GND to Vcm−.The expressions for Vcm+ and Vcm− are represented by Equation (3) and Equation (4), respectively: where V dsatn and V dsatp are the minimum drain-source voltages that ensure M 9 and M 10 operate as current sources.When VDD > V gs4 + V dsatn + V dsatp = V gs + 2V dsat , the input range is obviously from 0 to VDD.The complete RIPO amplifier circuit is depicted in  The proposed SSFB added as an auxiliary circuit is shown in Figure 3.The core components of the SSFB are M 26 -M 28 , where the M 26 is used as the source follower, while M 27 and M 28 serve to enhance the following capability.The primary signal transmission pathway involves the passage of signals from the gate of M 26 through resistor Rz to reach the output terminal.The node at the gate of M 27 is a high impedance node.Generally, the stability of a buffer solely based on this main signal path is not taken into consideration.However, it should be noted that the proposed buffer also incorporates an inner loop, which may cause stability problems.To deal with the stability issue, compensation is achieved by incorporating capacitor C B and resistors R B R Z .A detailed analysis is provided in Section 2.3.The transistors M 31 and M 36 are used as current sources to supply the static operating currents I bp and I bn , respectively.The ratio of I bp to I bn is set at 1:4, with I bp biased at 0.25 µA and I bn biased at 1 µA.

Stability Analysis
The simplified structure of the whole CL-LDO with RIPO and SSFB is illustrated in Figure 4.The main feedback loop of the LDO consistently employs linear feedback, and this paper uses the unit negative feedback.Considering that the transfer function of the buffer is close to unity except at high frequencies, and considering its large input impedance, we temporarily substitute it with A vbuf ≈ 1 when analyzing the frequency response of CL-LDO.This is discussed separately later.The pole inside EA, which is at an extremely high frequency due to the small parasitic capacitance C O1 and is composed of the output of E A1 and input of E A2 , is disregarded in the frequency response analysis of the proposed CL-LDO.R O2 and C O2 stand for the output resistance of EA and the input parasitic capacitor of the buffer, respectively.C O3 comprises the gate-source capacitor (C gs ) of the power PMOS M P and the output parasitic capacitor of the buffer.Considering that the parasitic capacitance is significantly smaller than C gs by several orders of magnitude, it can be approximated that C O3 is approximately equal to C gs .R O3 is equal to the output resistance of the super source buffer, which is extremely small.C gP consists of the Miller compensation capacitor, C P , and the gate-drain capacitor (C gP ) of M P .The resistance R O denotes the equivalent output resistance, which is influenced by the load current, while C L represents the load capacitor.The A v (s) is given by Equations ( 5)- (9).P 1 is the dominant pole, while P 2 and P 3 are the non-dominant poles.When the load current I load increases, the output resistance decreases due to its inverse proportionality with the load current.Since g mp is proportional to √ I load and R O is proportional to 1/I load , P 1 and P 2 are proportional to √ I load .To guarantee system stability, the phase margin should be above 60 • ; so, P 2 and P 3 should be placed above the double unity gain frequency under all conditions.The approximate output resistance of EA R O2 = r O24 ||r O25 is several megaohms, while the equivalent capacitor at the input of M P is approximately tens of pF.Without the proposed buffer, the non-dominant pole is generated by the resistance R O2 and capacitors C gs and C gd , which are near to the dominant pole, thereby leading to stability issues.However, in this paper, the buffer incorporating a low output resistance separates this low-frequency pole into two high-frequency poles.The frequency response when I load changes is shown in Figure 5.The circuit could keep steady when I load rises to 20 mA without an output capacitor.The stability of the entire proposed loop must be ensured under all conditions, along with the buffer stability, which has been approximately replaced by A vbuf ,.To analyze the loop stability of the buffer, the block diagram in Figure 6 is proposed.The resistor R Z is added to generate a zero with the parasitic capacitor C gp .The presence of this zero ensures the stable operation of the inner loop, even when C gp is large and, in turn, generates another pole for the main feedback loop.The capacitor C B and resistor R B are also added to compensate.Although the Miller gain applied to C B is relatively small, it should be noted that one end of C B is connected to the drain of M 24 .Consequently, to facilitate a simplified analysis within the block diagram, both C B and R B are connected in series and grounded.The gain of the inner loop is approximately given by Equation (10).

Transient Response Analysis
The proposed CL-LDO is expected to exhibit an enhanced transient response and reduced undershoot and overshoot spikes.To enhance the transient response, the dynamic charging transistors are added to deal with large transient steps.As depicted in Figure 7, the gate of PMOS M DCp and NMOS M DCn is directly regulated by the voltages V d of the d node and V b of the b node in the folded cascode amplifier.The ratio of the size of M DCTp to M DCTn is set as 1:2.At steady state, the M DCn and M DCp transistors are biased in the cutoff region by V b and V d because the overdrive voltages of both M 16 and M 18 are lower than the threshold voltages of M DCn and M DCp .In this case, this transient enhancement circuit will not influence the stability even with some offset at the input pairs.However, when a large transient step occurs, the output voltage will increase or decrease instantly.Since V b and V d are naturally sensitive to the transient response, large current I charge and I discharge can be generated to charge or discharge the large gate parasitic capacitor of M P without additional sensing circuits.The deviation of the output voltage V dev that causes V b and V d to bias dynamic charging transistors in open mode is given in Equations ( 11) and (12).
where V th,MDCTp and V th,MDCTn are the threshold of M DCp and M DCn , and where V ov12 and V ov10 are the overdrive voltages of M 12 and M 10 .Here, g mp and g mn stand for the trans-conductance of the input pair consisting of M 1,2 and M 3,4 , while R d and R b denote the equivalent resistance at nodes d and b, respectively.When considering the size of M DCp and M DCn , due to the presence of a small parasitic capacitance, the minimum length is used to ensure a rapid response time.According to the equation, it is evident that V devp,n is controlled by the threshold voltage of M DCp,n .However, if the transistor's size and voltages of the b and d nodes are appropriately designed, V devp,n will be constrained by the gain of this transient enhancement circuit and will remain unaffected by V th,MDCp,n .Additionally, a smaller V devp,n leads to a reduced ∆V OUT .To effectively regulate the overshoot and undershoot voltage at one-tenth of V OUT , it is recommended that V devp,n be set to approximately 100 mV.To control the transient response limitation caused by the finite bandwidth of the main linear regulation loop, a simple operational trans-conductance amplifier (OTA) with a constant small current is incorporated to regulate the high impedance node of the proposed SSFB.By employing this simple OTA for control, the unity gain frequency can be pushed to a higher point and the bandwidth of the main loop can be expanded.The loop frequency response of the whole circuit with added OTA is shown in Section 3 to demonstrate the stability.

Simulation Results and Discussion
The proposed CL-LDO is simulated using a TSMC 0.18 µm standard CMOS process.With a supply voltage range of 1.2 V to 1.8 V and a bias current of 2 µA, this CL-LDO is designed to maintain output voltage regulation at 1 V.We will talk about the precise simulation findings for the stability, load regulation, line regulation, and power supply rejection under various conditions.

Loop Frequency Response
The loop frequency response under different load capacitor and load current combinations is shown in Figure 8. Figure 8a shows the Bode diagram without load capacitor, while Figure 8b shows the load capacitor at 100 pF.Both (a) and (b) show the current load range from 20 mA to 0 mA.As previously analyzed, the bandwidth is pushed from several hundred kilohertz to 1.6 megahertz.On the contrary, the dc gain decreases by approximately 30 dB, which demonstrates the trade-off between gain and speed.It is evident that the load condition has little influence on stability since the node at output is set as the non-dominant pole.The minimum phase margin is 58.12 • when the load current is 0 mA and the load capacitor is 100 pF.Meanwhile, the maximum phase margin is 73.33 • when the load current is 20 mA and without a load capacitor.

Load Transient Response and Load Regulation
The load transient response and load regulation of the proposed CL-LDO are depicted in Figure 9.The load current ranges from 0 A to 20 mA, while the rise and fall times of I Load for emulating the load transient response are set at 100 ns.The simulation results of CL-LDO with and without the transient enhancement circuit are compared and illustrated in Figure 9a.The response time of CL-LDO during load current rise and fall is significantly improved, with a reduction to 0.2 µs and 0.5 µs, respectively, surpassing the performance of the circuit without a transient enhancement circuit.The undershoot voltage drops from 566.5 mV to 238.6 mV, and the overshoot voltage drops from 437.6 mV to 156 mV. Figure 9b shows the load regulation when V IN = 1.8 V and C L = 0 pF.The V OUT suffers from a 530 µV variation when I Load changes from 0 to 20 mA, resulting in a load regulation of 26.5 µV/mA.

Power-Supply Rejection
The PSR of an LDO is given in [18], as shown in Equation (13).
where LG(s) stands for the loop gain, ω 0 is the pole at the output of the LDO, and R L and r ds denote the load resistance and the output impedance of M P , respectively.At low frequency, PSR is obviously equal to 1/(1 + LG(s)).If the ω 0 is the non-dominant pole, the loop gain exhibits a roll-off at −20 dB/decade, resulting in a corresponding decline in the PSR at the same rate from the dominant pole.This degradation will persist until the PSR remains constant when LG(s) is significantly smaller than 1.At a higher frequency, the PSR is primarily influenced by the load capacitor and the M P 's parasitic capacitors, resulting in a reduction in the equivalent resistance.The simulated PSR performance of the proposed CL-LDO at a 20 mA load current and 0 pF load capacitor is shown in Figure 11.The PSR of the proposed CL-LDO is −43 dB at 100 Hz and −9 dB at 1 MHz.The attenuation trend of PSR degrades by −20 dB/decade after the dominant pole, which corresponds to the analysis of Equation ( 13) and the stability analysis.

Performance Comparison
The figure of merit (FOM) in [19,20] is adopted to evaluate the different current efficiencies of the CL-LDOs.The smaller FOM indicates superior performance in terms of the current efficiency and load transient response.The parasitic capacitance of the power transistor is influenced by the minimum channel length (L) in different processes.A process with a shorter minimum L may result in a smaller FOM due to the reduced parasitic capacitance of the transistor.To ensure a fair comparison, the FOM 1 equation, originally proposed in [6] with consideration of the minimum L, is used to compare the transient response.
The performance comparison with previously reported CL-LDOs is summarized in Table 1.In this table, the representative study findings from recent years are compared with this design to demonstrate the improved performance.The I Q row shows that the power consumption of this design is only slightly higher than that proposed in 2020, and significantly lower than other architectures.The Load Reg and T settle rows show that this design can achieve good voltage regulation and a fast response performance when the load current changes.These comparison results demonstrate that even under the relatively backward 180 nm process, the architecture can still have lower power consumption, smaller load regulation and a faster response speed.As a result, this demonstrates a lower FOM 1 , indicating a higher performance benefit.

Conclusions
This paper proposes a new capacitor-less LDO structure for digital analog hybrid circuits.The proposed capacitor-less LDO utilizes RIPO and SSFB to satisfy the design challenge of stability typically associated with the absence of on-chip capacitors.This proposed structure is stable at a load current range of 0 mA to 20 mA, with a maximum allowable CL of 100 pF.With the transient enhancement circuit, this structure achieves a good transient response while ensuring stability.The settling time is about 0.22 µs when the load current steps from 0 mA to 20 mA within 100 ns.
Figure 2b.It is based on the compact cascode amplifier (EA 1 ) with rail-to-rail input, where the gate voltage of EA 2 is sourced from the output of EA 1 .When the voltage of INP, the negative input of EA 1 , increases, the voltages of b and d decrease simultaneously.In this case, both gate voltages of M 24 and M 25 are reversed from INP and in phase at INN.So, the output stage, EA 2 , functions as a push-pull amplifier in the RIPO circuit.The stability analysis of this RIPO amplifier configuration with CC 1 is addressed in Section 2.3.

Figure 3 .
Figure 3. Schematic of super source follower buffer.

Figure 5 .
Figure 5. Frequency response at different I Load values.

Figure 6 .
Figure 6.Block diagram of super source follower buffer.

Figure 8 .
Figure 8. Simulation results of loop frequency response under different I O and (a) C L = 0 pF; (b) C L = 100 pF.

Figure 9 .
Figure 9. (a) Simulated load transient response of the proposed CL-LDO with I Load step between 0 A and 20 mA.(b) Load regulation with C L = 0 pF and V IN = 1.8 V.

Figure
Figure 10a illustrates the line transient response when the V IN step is between 1.2 V and 1.8 V at an edge time of 10 µs of the proposed CL-LDO.The line transient response is simulated at C L = 100 pF and I O = 0 mA.The output voltage exhibits an overshoot of 6.3 mV when the V IN steps up.Conversely, it experiences an undershoot of 7.7 mV when the line regulation, which quantifies the deviation in output voltage, is simulated under identical conditions.The voltage output, as depicted in Figure10b, exhibits a variation of 0.9 mV, resulting in a line regulation of 1.5 mV/V.

Figure 10 .
Figure 10.(a) Simulated line transient response of the proposed CL-LDO with VDD step between 1.2 and 1.8 V. (b) Line regulation with C L = 100 pF and I O = 0 mA.

Figure 11 .
Figure 11.Simulated PSR performance of the proposed CL-LDO.

Table 1 .
Main performance summary and comparison.