Advanced Analog and Mixed-Mode Integrated Circuits

A special issue of Electronics (ISSN 2079-9292). This special issue belongs to the section "Circuit and Signal Processing".

Deadline for manuscript submissions: closed (30 April 2024) | Viewed by 3397

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Guest Editor
Faculty of Electrical Engineering and Computing, University of Zagreb, HR-10000 Zagreb, Croatia
Interests: fractional calculus; analysis methods for fractional order circuits; design methods for fractional order circuits; circuit theory; circuits and systems for signal processing; analog filters; analog integrated circuits; fault analysis in analog filters
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Special Issue Information

Dear Colleagues,

The human–machine interface of most electronic systems has mainly remained analog and presumably always will. The importance of analog circuit theory and design in electrical engineering curricula has led to a worldwide shortage of analog circuit designers. However, in examples of modern electronic systems, which consist primarily of digital circuits, a so-called analog front end, characterized by analog input and output signals, must be present to interface with the outside world. The resulting system becomes a "mixed-mode" system in which digital and analog signals must interact optimally. The analog front end (AFE) is usually the bottleneck in many mixed-mode IC system chips (even though it occupies only a small portion of the chip area).

Therefore, the mission of this Special Issue is to strengthen further research in this vital area of mixed-mode signal processing and to fill the existing knowledge gaps in the field of advanced analog and mixed-mode integrated circuits.

Dr. Dražen Jurišić
Guest Editor

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Keywords

  • mixed-mode systems for signal processing
  • integrated circuits
  • analog front end
  • cadence

Published Papers (3 papers)

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Research

16 pages, 2181 KiB  
Article
Modeling and Mitigating Output-Dependent Modulation in Current-Steering DAC Based on Differential-Quad Switching Scheme
by Yingchao Sun, Zhenwei Zhang, Yi Shan, Lili Lang and Yemin Dong
Electronics 2024, 13(10), 1992; https://doi.org/10.3390/electronics13101992 - 20 May 2024
Viewed by 502
Abstract
This brief presents a comprehensive analysis of the output-dependent modulation (ODM) in a current-steering digital-to-analog converter (CS-DAC) based on the differential-quad switching (DQS) structure. A mathematical model is proposed to accurately describe ODM, which is categorized into two types: output transition errors and [...] Read more.
This brief presents a comprehensive analysis of the output-dependent modulation (ODM) in a current-steering digital-to-analog converter (CS-DAC) based on the differential-quad switching (DQS) structure. A mathematical model is proposed to accurately describe ODM, which is categorized into two types: output transition errors and boundary effect errors. A novel approach of adding isolation devices is introduced and reinterpreted to mitigate the effect of ODM. The simulation results indicate that the inclusion of isolation devices efficiently suppresses the odd harmonics at mid-to-high frequency by a value that is 13 dB lower than before. Experimental validation is conducted on a 16-bit 250 MS/s CS-DAC fabricated in a 180 nm process. Full article
(This article belongs to the Special Issue Advanced Analog and Mixed-Mode Integrated Circuits)
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14 pages, 856 KiB  
Article
A Compact MEMS Microphone Digital Readout System Using LDO and PPA-Less VCO-Based Delta-Sigma Modulation Technique
by Fanyang Li, Tao Yin, Shuwen Wu and Wenren Deng
Electronics 2023, 12(24), 5014; https://doi.org/10.3390/electronics12245014 - 15 Dec 2023
Viewed by 1100
Abstract
This paper presents a compact Micro-Electro-Mechanical System (MEMS) microphone digital readout system. The system is characterized by a low-dropout regulator (LDO) and a pre-amplifier and programmable-gain amplifier (PPA)-less voltage controlled oscillator (VCO)-based ΔΣ modulation technique, which improve compactness and design scalability. Specifically, [...] Read more.
This paper presents a compact Micro-Electro-Mechanical System (MEMS) microphone digital readout system. The system is characterized by a low-dropout regulator (LDO) and a pre-amplifier and programmable-gain amplifier (PPA)-less voltage controlled oscillator (VCO)-based ΔΣ modulation technique, which improve compactness and design scalability. Specifically, to improve signal accuracy and maintain loop stability without a gain-tuning range trade-off, an active low pass filter (ALPF) and a current mode feed-forward path (CMFFP) are incorporated in a VCO-based delta-sigma modulation loop. By means of VCOs and SCG phase variation robustness and current source array feedback (CSAFB), the system achieves a high power supply rejection ratio (PSRR) and gain tuning without the need to design an extra regulator and PPA. The design was fabricated using a 180 nm Bipolar-CMOS-DMOS (BCD) process and measured at a 1.2 V supply voltage. According to the measurement results, the signal-to-noise and distortion ratio (SNDR) achieves 62 dB@1 kHz with 40 dB gain and a 10 kHz bandwidth. Furthermore, PSRR@1 kHz is below −55 dB, and power dissipation is within 57 µW. Full article
(This article belongs to the Special Issue Advanced Analog and Mixed-Mode Integrated Circuits)
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11 pages, 4171 KiB  
Article
A Design of a Dual Delay Line DLL with Wide Input Duty Cycle Range
by Binyu Qin, Leilei Zhao, Chenyu Fang and Peter Poechmueller
Electronics 2023, 12(12), 2696; https://doi.org/10.3390/electronics12122696 - 16 Jun 2023
Cited by 1 | Viewed by 1285
Abstract
This article describes a dual-controller dual-delay line delay lock loop (DC-DL DLL). The proposed DLL adopted a dual delay line structure, each delay line was composed of a coarse adjustment and a fine adjustment unit, and the dual delay lines had corresponding control [...] Read more.
This article describes a dual-controller dual-delay line delay lock loop (DC-DL DLL). The proposed DLL adopted a dual delay line structure, each delay line was composed of a coarse adjustment and a fine adjustment unit, and the dual delay lines had corresponding control units to reduce the mismatch between the delay lines, and it avoided the complicated design of duty cycle correction (DCC) circuit. A frequency divider was added to divide the input clock to achieve a wider input clock duty cycle adjustment. Additionally, a simple clock synthesis circuit was proposed to synthesize the required clock. The DLL design used the 25 nm process with a voltage of 1.2 V. The simulation results showed that at a working frequency of 1.6 GHz, the peak-to-peak jitter of the DC-DL DLL after locking was approximately 17.61 ps, the maximum output duty cycle error was about 1.3%, and the input duty cycle ranged from 20% to 80%, with a power consumption of 10.06 mW. Full article
(This article belongs to the Special Issue Advanced Analog and Mixed-Mode Integrated Circuits)
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