A Double-Edge-Triggered Digital LDO with Built-In Adaptive VCO Clock for Fast Transient Response and Low Power Consumption

Abstract

A double-edge-triggered digital low dropout regulator (DLDO) is proposed with a built-in adaptive voltage-controlled oscillator (VCO) clock (AVC) for a system-on-chip (SoC) application. To achieve a fast transient response, the main comparator generates the comparison result at the rising edge of the AVC, and this result is sampled by the coarse or fine bidirectional shifter register at the falling edge of the AVC. Furthermore, the clock frequency can be boosted from 8 MHz at the steady state to 50 MHz by the AVC when the output current suffers from a sudden change, and it can also be adjusted in real-time according to the output voltage, which avoids the oscillation phenomenon and decreases the power consumption during the recovery process. To further lower the power consumption, the self-clock comparator replaces the conventional static comparator in the transient detector. The post-simulation results show that the proposed DLDO consumes a quiescent current of 95.13 μA in the steady state, and drives a maximum load current of 25 mA at the supply power of 0.6 V with an active area of 0.053-mm² in a 180 nm CMOS process. When the load current jumps from 0.5 mA to 25 mA at the edge of 100 ps, the undershoot voltage and overshoot voltage are only 335 mV with the recovery time of 2.7 μs and 47.6 mV with the recovery time of 2.1 μs at the total on-chip capacitor of 50 pF, respectively, resulting in two competitive figures of merits (FoMs) than the previous works.

1. Introduction

In Internet of Things (IoT) and system-on-chip (SoC) application scenarios, energy-efficient fine-grained power management systems are indispensable for self-power wireless sensors due to the limited power capability of the supply and energy harvester. At high supply voltages (e.g., 1.2 V and above), analog low-dropout regulators (LDOs) can regulate a constant voltage for analog and RF modules due to their excellent noise performance and high PSRR characteristics, which maximize the performance and energy efficiency [1,2]. With CMOS process scaling, the intrinsic gain of the transistors is smaller, leading to an analog circuit accuracy reduction. Although the multistage operational transconductance amplifier improves the gain, it also introduces stability issues and considerable power consumption. In addition, in the near-threshold range (62 mV to 0.6 V), the analog LDO (ALDO) also fails to show excellent energy efficiency. Recently, the digital LDO (DLDO) features low voltage operation, process scalability, and other benefits associated with digital-oriented design, which has received the attention of many researchers [3].

Compared with the DLDO with the power PMOS transistors, the DLDO with the power NMOS transistor can provide additional current through their intrinsic loop (V_gs) to optimize the undershoot voltage and the response time during the output voltage recovery process. Nevertheless, this type of DLDO requires a charge pump circuit and the level shifter to ensure that the gate voltage of the power NMOS transistor is higher than the supply voltage [4]. This leads to extra area and power consumption in the level shifter, charge pump, and capacitance. The classic digital LDOs improve the clock frequency of the dynamic comparator and the bidirectional shift register (S/R) for a better transient response, but increase the static power I_q in the steady state [5]. Therefore, it is crucial to enhance the transient response while simultaneously reducing the power consumption.

There are various approaches to enhance the dynamic response of digital LDOs. One method is to use asynchronous clocking [6] or the self-clock technique [7] instead of the synchronous clock as the trigger method of the comparator and the S/R. However, asynchronous clocking can make the logic design more intricate and susceptible to voltage and temperature variations, which compromises the robustness of the system. Another strategy involves modifying the structure of the power PMOS transistor array, for instance, a binary-weighted PMOS capacitor array. Because the most significant bit PMOS transistor always offers the maximum current whether large or small jumps occur in the output voltage, this leads to the oscillation phenomenon and a long recovery time when a small output voltage change occurs [8]. Dual-loop regulation is an effective way to avoid the oscillation phenomenon by utilizing an extra transient detector (TD) to check the output changes. The coarse loop is used to quicken the output level recovery when the output exceeds the detection boundaries, and when the threshold level is not surpassed, the PMOS transistor in the fine loop is switched at each clock edge for high accuracy and current efficiency. However, the continuous-time (CT) comparator in the TD can increase the static power consumption of the digital LDO [9]. The analog-assisted (AA) technique uses a coupling capacitor C_C with a resistance R₁ that forms a high-pass filter to compensate the transient current to the gate of the PMOS transistor, which is a promising technology as there is no additional static power consumption [10]. However, the performance is degraded in the light-to-heavy load transient case because the transconductance of the PMOS transistors is too small to fully compensate for the load transient current. Fortunately, the light load current can reach about several hundred μA. The only fly in the ointment is that the transient response can be boosted at the expense of area (C_C = 120 pF). Finally, the fifth technique is adaptive clocking, which selects the clock frequency of the comparator and the S/R. However, the glitch during the fast/slow clock switching process may affect the performance of the circuit [11].

To address the above-mentioned issues, the comparator and bidirectional S/R were controlled with different trigger methods without extra circuit assistance and robustness issues in our work. Specifically, the comparator obtains the quantization result at the rising edge, while the bidirectional S/R then samples and shifts this quantization result at the falling edge. As a result, the transient response can be enhanced because the PMOS array can adjust the output current in the current cycle. In other words, this trigger technology can relax the clock frequency at the steady state by 2×. In addition, a built-in adaptive voltage-controlled oscillator (VCO) clock (AVC) is proposed to reduce both the static and transient power consumption by adjusting the clock frequency of the comparator and bidirectional S/R in real-time according to the output voltage. When the output current change jumps from 0.5 mA to 25 mA within 100 ps, the clock frequency of the AVC is boosted from 8 MHz in the steady state to 50 MHz, which lowers the undershoot voltage and the recovery time in the undershoot case and overshoot case to 335 mV, 2.7 μs, and 2.1 μs. To boost the current efficiency, the self-clock comparator in the transient detector is employed. The post-simulation results show that the proposed DLDO can provide a load current from 0.5 mA to 25 mA and achieve a peak current efficiency of 99.6% at the supply voltage of 0.6 V with an active area of 0.053 mm² in a standard 0.18 μm CMOS process, leading to the FoM₁ and FoM₂ of 2.654 ps and 0.13 pF, respectively.

The rest of this paper is organized as follows. Section 2 describes the architecture and working principle of the proposed DLDO. Section 3 demonstrates the circuit implementations and design considerations of each circuit module. Section 4 presents the simulation results and comparisons. Section 5 concludes this work.

2. Architecture and Working Principle

Figure 1a presents the overall architecture of the proposed DLDO with an AA loop from Ref. [4]. The proposed DLDO consists of the main comparator CMP₀ with an RS latch, two selectors controlled by the MOD signal, the coarse and fine bidirectional S/R, the coarse and fine power PMOS transistor arrays, the AVC, and the TD.

To trade off the power and transient response, the PMOS array is divided by 128 coarse PMOS transistors with a size of 100 μm/0.18 μm and 64 fine PMOS transistors with a size of 10 μm/0.18 μm. The total size of the coarse PMOS array is mainly determined by the maximum load current, while the size of the unit for the fine PMOS transistor is decided by the minimum load current. Under the same maximum output current capability, as the bits of the coarse PMOS array increases, for example, 256 bits, the output current of every unit of the coarse PMOS transistor is halved, which not only increases the area of the coarse bidirectional SR, but also prolongs the recovery time. In contrast, with the decrease in the bit of the coarse PMOS array such as 64 bits, the transient current provided by every coarse PMOS transistor is increased by more than two times at a large undershoot in the output voltage since the source to drain voltage (V_sd) of every coarse PMOS transistor increases from 50 mV in the steady state to several hundred mV in the transient response. The simulation shows that the output current of every coarse PMOS transistor with a size of 400 μm/0.18 μm is 924 μA and 1.8 mA at the V_sd of 50 mV and 300 mV, which is much higher than the total current (828 μA) provided by the fine PMOS array. However, by doing this, the output suffers from the overshoot voltage after the undershoot voltage, which still prolongs the recovery time. More significantly, the proposed DLDO cannot switch from the coarse loop to the fine loop during the output recovery process. Furthermore, the RS latch can protect or temporarily store the main comparator result during the comparator reset phase.

It can be seen from Figure 1 that the gate voltage of the power PMOS transistors is determined by the coarse/fine loop bidirectional S/R and the AA loop. When the output current increases suddenly, the output voltage of the proposed DLDO decreases sharply, and the output voltage change is assumed as ΔV_out. The AA loop has a faster response than the main loop of the DLDO, and thus the gate voltage can reduce C_C·ΔV_out/(C_C + C_P) immediately to lower the undershoot voltage, where C_P is the parasitic gate capacitor of the power PMOS transistors. In the proposed work, the total size of the fine PMOS array is only 1/20 of that of the coarse PMOS array. Therefore, the undershoot voltage dominantly relies on the coarse PMOS array. Furthermore, even if the AA loop is employed in the fine PMOS array, the undershoot voltage cannot be optimized obviously because the parasitic capacitance of the fine PMOS array is contained and the gate voltage change of all PMOS transistors is reduced under the identical C_C. Therefore, the AA loop is only used for the coarse PMOS array by trading off the undershoot voltage and gate voltage change of the power PMOS transistors.

Figure 1b shows the transient response comparison between the classical DLDO [5] and the proposed DLDO. When the load current (I_load) steps up at t₁ within a rapid edge time, the CMP₀ and the SR latch hardly provide a correct comparison result (CMP_out) due to the limited comparison time (1/(2·F_clk)). At t₂, the CMP_out turns to the high level at the rising edge of F_clk. Now, the coarse S/R is selected by the MOD because the V_OUT exceeds the threshold boundary, unlike the S/R of the classical DLDO [5] and the conventional coarse-fine loop DLDO [9], which is triggered in the next cycle t₃. The S/R in the proposed DLDO is triggered at the falling edge to turn on the power PMOS transistor to supplement the output current to reduce the ΔV_DEL until the I_PMOS is equal to I_load. In other words, the transient response can be enhanced by triggering the comparator CMP₀ and the S/R at the rising and falling edge, respectively, without the clock frequency increment and any hardware cost.

Unlike the conventional TD [12], the self-clocked comparators CMP₁ and CMP₂ replace two CT comparators to lower the power consumption, and the operation frequency of these two comparators is enhanced to 58 MHz to diminish the comparator’s delay effect on the DLDO at a supply voltage of 0.6 V. The four resistors R₁, R₂, R₃, and R₄ in the TD have resistance values of 5300 Ω, 200 Ω, 200 Ω, and 5300 Ω, respectively. Therefore, V_H, V_FB, and V_L can be calculated as follows:

$$\left\{\begin{array}{c}{\mathrm{V}}_{\mathrm{H}}=\frac{{\mathrm{R}}_2+{\mathrm{R}}_3+{\mathrm{R}}_4}{{\mathrm{R}}_1+{\mathrm{R}}_2+{\mathrm{R}}_3+{\mathrm{R}}_4}\cdot {\mathrm{V}}_{\mathrm{out}}\\ {\mathrm{V}}_{\mathrm{FB}}=\frac{{\mathrm{R}}_3+{\mathrm{R}}_4}{{\mathrm{R}}_1+{\mathrm{R}}_2+{\mathrm{R}}_3+{\mathrm{R}}_4}\cdot {\mathrm{V}}_{\mathrm{out}}\\ {\mathrm{V}}_{\mathrm{L}}=\frac{{\mathrm{R}}_4}{{\mathrm{R}}_1+{\mathrm{R}}_2+{\mathrm{R}}_3+{\mathrm{R}}_4}\cdot {\mathrm{V}}_{\mathrm{out}}\end{array}\right.$$

(1)

According to Equation (1), even if there is a resistance mismatch, V_H must be larger than V_REF, while V_L must be smaller than V_REF. If the TD range is too small (2 mV), the proposed DLDO will jump from the fine loop to the coarse loop with a slight change in the output voltage. As a result, the output voltage will oscillate during output recovery due to multiple overshoots and undershoots, resulting in a long recovery time. If the TD range is too large (200 mV), it is difficult to switch the proposed DLDO from the fine loop to the coarse loop with a large jump in the output. As a consequence, this situation also leads to a long recovery time since the current provided by each PMOS transistor in the fine loop is small. In our design, the TD range was designed to be 20 mV by compromising the recovery time in the case of the large jump and the small jump in the output voltage. In addition, the V_H and V_L were designed for 285 mV and 265 mV, respectively, by the series resistor ladder instead of the voltage reference for the dynamic voltage scaling. The voltage reference operating in the subthreshold region or the 2T solution in [13] can dramatically reduce the static power consumption. However, the series resistor ladder was used in our work for two reasons. Firstly, V_H, V_L, and V_FB vary with the supply voltage to achieve a fixed V_drop. The voltage reference (2T solution) can only provide a fixed level under different PVT conditions, which shrinks the supply voltage range. Secondly, we assumed that a voltage reference with the value of 285 mV was designed with the nanowatt level power consumption. An external operational amplifier is still required to generate a voltage reference value of 265 mV, resulting in additional power consumption and increased circuit complexity. When the load current changes sharply, the overshoot voltage or undershoot voltage exceeds the threshold voltage V_H or V_L, and then the MOD outputs 1. The AVC generates a high-frequency clock. At the same time, the comparator and coarse bidirectional S/R, controlled by this high-frequency clock, can quickly recover the output voltage through a coarse PMOS array until V_FB is recovered between the V_H and V_L levels. More importantly, because the clock frequency (F_clk) is controlled by the V_H and V_L associated with the output of the DLDO (V_out), it will decrease with the decrease in the undershoot voltage. Therefore, the oscillation at V_out can effectively be avoided during the signal recovery process. When the circuit output is at a steady state or when the overshoot voltage or undershoot voltage is small, MOD outputs 0, and the AVC produces a corresponding low-frequency clock to control the CMP₀ and the fine-loop bidirectional SR for the output voltage recovery. Meanwhile, the coarse bidirectional SR is idle to lower the power consumption.

3. Design Results and Comparison

3.1. Dynamic Comparator Design

The self-clock comparators CMP₁ and CMP₂ in the TD shown in Figure 2 consist of a double-tail comparator (DTC), an XOR, and an SR latch. Assuming that the initial outputs Out_p and Out_n are at the low level at the reset state, the CLK becomes the high level after the delay of the XOR (t_XOR), and then the comparator starts to compare the feedback signals (V_H and V_L) and V_REF to generate the new results Out_p and Out_n after the delay of the comparator (t_cmp). By performing an XOR for the new results Out_p and Out_n, the CLK becomes the low level after the t_NOR, and the comparator can also be reset after the reset time of the comparator. Hence, the operation frequency of the self-clock comparator can be written as:

$${\mathrm{f}}_{\mathrm{clk}}=1/\left(2\cdot t_{\mathrm{XOR}}+t_{\mathrm{reset}}+t_{\mathrm{cmp}}\right)$$

(2)

Compared to the strong-arm comparator, the DTC is made up of the preamplifier stage (preamp) and the second latch stage, and the kickback noise can be isolated by the preamplifier stage in the low-voltage operation. The main comparator CMP₀ is controlled by the AVC to enhance the transient response, while the comparators CMP₁ and CMP₂ are controlled by the clocks CLK₁ and CLK₂ separately for the output voltage detection in real-time. To analyze the delay of the comparator (t_cmp), the operation process of the DTC is divided into three phases: the reset phase, the integrated phase, and the latch phase. The delay in the integrated phase (t₀) and the latch phase (t_latch) of the comparator is the dominant factor. t₀ represents the charging process to the load capacitor (C_out) until the first n-channel transistor (NM₃/NM₄) turns on. t_latch stands for the latching delay of two cross-coupled inverters (PM₃, PM₄, NM₃, and NM₄ transistors), which is from an initial output voltage difference V₀ (The final state of the integral phase) to a voltage swing of V_outp − V_outn = V_DD/2. The total delay (t_cmp) of this comparator can be evaluated as follows [14]:

$$\begin{array}{ll}{\mathrm{t}}_{\mathrm{cmp}}& ={\mathrm{t}}_0+{\mathrm{t}}_{\mathrm{latch}}=2\frac{V_{thnm5,6}\cdot {\mathrm{C}}_{\mathrm{out}}}{I_{tail2}}+\frac{{\mathrm{C}}_{\mathrm{out}}}{g_{m,inv}}\cdot ln\left(\frac{V_{DD}/2}{\Delta V_0}\right)\\ & =2\frac{V_{thnm5,6}\cdot {\mathrm{C}}_{\mathrm{out}}}{I_{tail2}}+\frac{{\mathrm{C}}_{\mathrm{out}}}{g_{m,inv}}\cdot ln\left(\frac{V_{DD}\cdot I_{tail2}^2\cdot {\mathrm{C}}_{\mathrm{X}}}{8\cdot g_{mnm1,2}\cdot g_{mnm5,6}\cdot {\mathrm{C}}_{\mathrm{out}}\cdot V_{thnm5,6}^2\cdot \Delta V_{in}}\right)\end{array}$$

(3)

where C_X is the output parasitic capacitor at the nodes f_n and f_p, g_mnm1,2, g_mnm5,6, and g_m,inv are the transconductance of the NM₁, NM₂, NM₅, and NM₆ transistors, and the two cross-coupled inverters, I_tail2 and V_thnm5,6 stand for the tail current of the M_tail2 transistor at the latch phase and the threshold voltage of the NM₅ and NM₆ transistors. It can be seen from Formula (3) that the delay of the comparator can be affected by the input level difference and the process corners.

Figure 2. (a) Schematic of the comparator with the self-clocked technology. (b) Schematic of the double-tail dynamic comparator.

Figure 2. (a) Schematic of the comparator with the self-clocked technology. (b) Schematic of the double-tail dynamic comparator.

The effect of the offset voltage of the comparator on the proposed DLDO can be equivalent to the effect on the accuracy of the voltage reference (V_REF). The offset voltage can be calculated as follows:

$${\mathrm{V}}_{\mathrm{os}}={\mathrm{V}}_{\mathrm{os}, \mathrm{preamp}}+\frac{1}{{\mathrm{A}}_{\mathrm{preamp}}}{\mathrm{V}}_{\mathrm{os}, \mathrm{latch}}$$

(4)

where V_{os, preamp} and V_{os, latch} are the offset of the preamplifier stage and the second latch stage. A_preamp represents the gain of the preamplifier stage. Since the V_{os, latch} is damped by the preamplifier stage, the offset voltage of the dynamic comparator is dominated by that of the preamplifier stage and the V_{os, preamp} can be expressed as follows [15]:

$${\mathrm{V}}_{\mathrm{os},\mathrm{preamp}}=\Delta {\mathrm{V}}_{\mathrm{thNM}1,2}+\frac{{\left({\mathrm{V}}_{\mathrm{gs}}-{\mathrm{V}}_{\mathrm{th}}\right)}_{\mathrm{NM}1,2}}{2}\cdot \left(\frac{\Delta {\mathrm{S}}_{\mathrm{N}\mathrm{M}1,2}}{{\mathrm{S}}_{\mathrm{N}\mathrm{M}1,2}}+\frac{\Delta {\mathrm{R}}_{\mathrm{N}\mathrm{M}1,2}}{{\mathrm{R}}_{\mathrm{N}\mathrm{M}1,2}}\right)$$

(5)

where ∆V_thNM1,2, ∆S_NM1,2, and ∆R_NM1,2 indicate the threshold voltage mismatch, the parameter (μC_OXW/L) mismatch of the NM₁ and NM₂ transistors, and the equivalent load mismatch at the nodes f_p and fn, respectively. (V_gs-V_th)_NM1,2 stands for the overdrive voltage of the NM₁ and NM₂ transistors. Therefore, the W/L of the input transistor NM₁ and NM₂ needs to be increased to suppress the offset voltage of the DTC. When the positive side of the comparator is increased linearly from 265 mV to 285 mV in 20 μs, and the negative side of the comparator is fixed at 275 mV, Figure 3 shows the 500-run Monte Carlo simulation of the offset voltage at the clock frequency of 8 MHz and 50 MHz. The type of Monte Carlo simulation is “process and mismatch”. The mean and standard deviation of the comparator’s offset voltage are independent of the clock frequency and are about 700 μV, which can match the theoretical calculation.

3.2. Built-In Adaptive VCO Clock

Figure 4a presents the schematic of the AVC, which is composed of the 11-stage inverter-based ring oscillator in Figure 4b, the pull-down controlled transistors (MN₁-MN₆), and the pull-up-controlled transistor (MP₁-MP₆). The working state of the AVC is decided by the TD. When the proposed DLDO is in the steady state (V_H > V_REF > V_L), the outputs Out₁ and Out₂ of the self-clocked comparator CMP₁ and CMP₂ are high level, and the oscillation frequency of the AVC is determined by the pull-up current of 1.3 μA from the MP₃ transistor and the pull-down current of 1.4 μA from the MN₃ transistor. If the pull-up current is equal to the pull-down current in the steady state, the AVC will generate a clock with a duty cycle of 50%. Because the reset time (T_res) at the low level of the main comparator (CMP₀) is independent of the input signal amplitude, it can be less than the quantization time (T_quan) at the high level to improve the operating frequency of the CMP₀. That is to say, it is not necessary to design the clock duty ratio of 50% under the steady state. Because the pull-up current is less than the pull-down current, the pull-up time is greater than the pull-down time for every inverter in Figure 4b. The T_res at the low level and the T_quan at the high level can be calculated as follows:

$$\left\{\begin{array}{c}{\mathrm{T}}_{\mathrm{res}}=6\cdot {\mathrm{t}}_{\mathrm{inv}\_\mathrm{pu}}+5\cdot {\mathrm{t}}_{\mathrm{inv}\_\mathrm{pd}}\\ {\mathrm{T}}_{\mathrm{quan}}=5\cdot {\mathrm{t}}_{\mathrm{inv}\_\mathrm{pu}}+6\cdot {\mathrm{t}}_{\mathrm{inv}\_\mathrm{pd}}\end{array}\right.$$

(6)

It can be seen from Formula (6) that the reset time of the comparator is just less than the quantization time of the comparator.

This oscillation frequency of the AVC can be calculated as 8.13 MHz, which can match the simulation result (8 MHz). When the output (V_out) of the proposed DLDO encounters a large undershoot in the transient response (V_H < V_REF), the Out₁ turns to the low level and the Out₂ remains at the high level. The pull-down current from the current mirror (the MN₁ and MN₂ transistors) and the extra pull-up current from the MP₂ transistor can boost the oscillation frequency of the AVC. Meanwhile, the pull-down current is controlled by the V_L, and the larger the undershoot voltage, the higher the I_MN2 current and oscillation frequency of the AVC. Similarly, when the overcharge voltage occurs (V_L > V_REF), the oscillation frequency of the AVC is also enhanced by the pull-up current from the MP₄ transistor and the extra pull-down current from the MN₄ transistor. Figure 4c summarizes the working state and the oscillation frequency of the AVC in different conditions of the DLDO. Figure 5a shows that the clock frequency of the AVC varies with the V_L and V_H. F_clk is only 8 MHz at the steady state; the F_clk can be boosted up to about 50 MHz at the transient response at a 0.6 V supply through the PSS simulation.

The clock frequency of the AVC at different temperatures and corners at the steady state and transient state is presented in

Table 1. F_clk at different temperature and process corners.

Temp [°C]	−40			27			85
Corner	FF	TT	SS	FF	TT	SS	FF	TT	SS
Steady state @ Fclk [MHz]	7.86	5.97	4.12	10.05	8.01	5.10	13.13	10.96	7.15
Undershoot @ Fclk [MHz]	52.31	40.28	29.97	60.11	51.23	39.58	70.23	61.34	49.22
Overshoot @ Fclk [MHz]	51.03	39.24	28.92	57.88	49.54	38.37	69.58	60.77	48.64

. The slowest frequency and fastest clock frequency occur at the −40 ℃@ss corner and 85 ℃@ff corner. Furthermore, the clock frequency ratio between the steady state and the transient state is almost 1:6.25 at any process corner and temperature. Figure 5b shows the 500-run Monte Carlo simulation of the clock frequency at the steady state and transient state. The mean value and standard deviation of the clock frequency at the steady state are 8.21 MHz and 2.48 MHz, respectively, while those of the clock frequency at the undershoot case and overshoot case are nearly 52 MHz and 11.61 MHz, and 50.82 MHz and 13.12 MHz, respectively.

3.3. Loop Stability Analysis

Following a similar analysis presented in [4,10], the small signal model and the zero-pole distribution are demonstrated in Figure 6a and 6b, respectively. The bidirectional S/R acts as an ideal discrete-time integrator with a dc pole (p₀) with the gain of K_SR. The PMOS array outputs a constant current and provides a gain of K_DC until the next negative clock edge, thus a zero-order hold (ZOH) is placed in front of the output stage, which is modeled by the load resistor (R_load) and the load capacitor (C_load). Hence, the second pole p₂ and the third parasitic pole p₃ are located at the output node V_out and the gate of the power transistor (V_G), where R_on1 and R_on2 stand for the output resistance of the turn-on power transistors and the output resistance of the inverter in the coarse loop and the S/R in the fine loop at node V_G. The p₃ is far away from the unit gain-bandwidth product, which does not affect the loop stability. Furthermore, the AA loop in Figure 6b introduces a dc zero z₀ and a pole p_AA, and it does not work in the steady state of the DLDO. Therefore, the open-loop transfer function H(s)_{open_loop} and closed-loop transfer function H(s)_close-loop in the steady state can be expressed respectively as follows:

$$\begin{array}{ll}H{\left(s\right)}_{open\_loop}& =e^{-s{T}_{clk}/2}\cdot {\mathrm{K}}_{\mathrm{SR}}\cdot \frac{1}{1-z^{-1}}\cdot \frac{1-e^{T_{clk}}}{s}\cdot \frac{{\mathrm{K}}_{\mathrm{DC}}}{1+s/F_{load}}\\ & =\frac{{\mathrm{K}}_{\mathrm{forward}}}{z-1}\cdot \frac{1-e^{-F_{load}/F_{clk}}}{z-e^{-F_{load}/F_{clk}}}\end{array}$$

(7)

$$\begin{array}{ll}H{\left(s\right)}_{close\_loop}& =\frac{H{\left(s\right)}_{open\_loop}}{1+H{\left(s\right)}_{open\_loop}}\\ & =\frac{{\mathrm{K}}_{\mathrm{forward}}\left(1-e^{-F_{load}/F_{clk}}\right)}{\left(z-1\right)\left(z-e^{-F_{load}/F_{clk}}\right)+K_{\mathrm{forward}}\left(1-e^{-F_{load}/F_{clk}}\right)}\end{array}$$

(8)

where the forward gain K_forward = K_SR·K_DC, and F_load and F_clk are the output pole frequency ((R_on1||R_load)·C_Load)⁻¹ and the adaptive clock frequency, respectively. Unlike the analog LDO, the DLDO cannot directly reflect the zero-pole point position and the phase characteristics by the AC simulation. The DLDO judges the stability by the distribution of poles in the z plane. As analyzed in Equation (7), one pole is located on the unit circle, which is derived from the S/R. The other pole is determined by the F_load and F_clk together. The worst case of stability is at the light load due to a large output resistance. In the pre-simulation, the F_clk of the AVC was 8 MHz and the F_load was 36.4 MHz. In the post-simulation, the F_clk was reduced to 7.8 MHz, and the F_load was reduced to 35.8 MHz. Hence, the second pole was almost unchanged and hardly affected the stability. Based on the MATLAB model, under the condition of the constant sampling rate F_clk, with the decrease in the load current, the decrease in F_load makes the two poles (z = 1 and z = e^{−Fload/Fclk}) closer in Figure 7a, and easily leads to the instability of the system because the phase margin (PM) is decreased from 84.8° to 45.1°, as shown in Figure 7b. The stability of the proposed DLDO benefits from the AVC technology because the clock frequency of F_clk can drop down to 8 MHz whether under a heavy or light load.

3.4. LCO Issues at the Steady State

The intrinsic quantization noise of the DLDO causes the output ripple at the steady state, which is also known as the limit cycle oscillation (LCO) phenomenon. Normally, the LCO period is 2M times the clock period (T_clk), where M is the mode of the LCO. In the classical DLDO, since the bidirectional S/R always samples the quantization result of the previous cycle in Figure 8, the response time of the power PMOS array has a period delay, resulting in the obvious voltage ripple in the conventional DLDO. With the double-edge-trigger method, the comparator performs quantization at a high level, and the S/R outputs and shifts the comparator result at the falling edge in the same cycle. Therefore, the proposed digital LDO can prompt the output timelier than the classical DLDO.

As shown in Figure 8, when V_out is slightly higher than the V_REF in the steady state, the comparator performs quantization at t₀, a single PMOS power transistor controlled by the fine bidirectional S/R can be switched off to reduce the output current at t₁, and the output begins to be pulled down. If the settling time τ, decided by the output pole, is less than half of the sampling clock cycle (T_clk/2), the output voltage can be stable at the next quantization point t₂. According to the comparator result, the PMOS array turns on a single PMOS transistor to provide the output current from the moment t₃, and then the output voltage begins to be stretched to a level higher than V_REF, like the moment t₀. As depicted in Figure 8, the mode of the LCO can be reduced from 3 to 1. Compared with the auxiliary redundant PMOS power transistor in the feedforward path [16,17], the proposed LDO can reduce the LCO mode to 1 without adding any extra power consumption or design complexity.

4. Simulation Results and Comparisons

Figure 9 shows that the proposed DLDO occupies an active area of 0.053 mm² in a standard 0.18 μm CMOS process including the CMP₀, the AVC, the TD with two self-clocked comparators (CMP₁ and CMP₂), the AA circuit, and the coarse and fine S/R and the power PMOS transistor array. Figure 10 shows the simulation setup of the proposed DLDO. The total on-chip capacitor (C_C) was 50 pF and the resistors R_a1 and R_a2 were served for the heavy load and light load, which were designed as 22.5 Ω and 1100 Ω, respectively. The switch (S_w) and the inverter (inv₁) are employed to generate the falling and rising edge time of 100 ps for the load transient.

All parasitic effects were considered including the parasitic capacitance from the metal wires to the substrate, the parasitic capacitance among different metal wires, and the parasitic resistance of the wires. The parasitic resistance of the entire proposed DLDO was reduced by the minimum spacing between modules and the multilayer metal interconnection technology. Because the static current of the proposed DLDO was less than 100 μA, the effect of the parasitic resistance was almost negligible. In addition, the offset of the dynamic comparator and resistance mismatch in the TD circuit were suppressed by good matching and dummy technology.

The proposed DLDO provides a load current from 500 μA to 25 mA and consumes a quiescent current of 95.13 μA at the heavy load of 25 mA under a low supply of 0.6 V, resulting in a peak current efficiency of 99.6%. The power consumption is independent of the I_load, and Figure 11 illustrates the power breakdown of the proposed DLDO in the steady state where the resistors in the TD occupy more than 50% of the total power, and the power of the AVC is only 2.5% of the total power.

The proposed DLDO can regulate V_OUT from 550 mV to 1050 mV with the V_DD varying from 0.6 V to 1.1 V with a dropout voltage of 50 mV. Figure 12a shows that the line regulation (LR) was 5.8 mV/V at the load current of 0.5 mA and 4.3 mV/V at the heavy load of 25 mA, respectively, while Figure 12b shows that the best and worst LR were 4.2 mV/V and 6.6 mV/V at the V_REF of 0.75 V and 0.5 V, respectively. Figure 12c shows that the fluctuation of the load regulation (LD) varied the supply voltage, and the LD as 0.1265 mV/mA at the supply of 0.6 V. Figure 12d,e verified the LR at the light load of 0.5 mA and LD at the 0.6 V supply at different corners, and the LR and LD remained at the same order of magnitude. To evaluate the transient performance of the proposed DLDO, the proposed DLDO regulator was operated at the V_DD of 600 mV with the V_OUT of 550 mV and the C_C of 50 pF.

Regardless of the analog LDO or the digital LDO, the shorter the T_edge, the more it can reflect the worst undershoot voltage and overshoot voltage of the LDO. Therefore, T_edge was designed to be 100 ps to reflect the worst undershoot voltage and overshoot voltage. The advantage of the capacitor C_C in the AA technology is that the off-chip load capacitor can be reduced to 0 [10]. In order to intuitively reflect the transient effects of parasitic capacitance and resistance, Figure 13 shows that the overshoot voltage and undershoot voltage of the proposed DLDO were almost unchanged, and the recovery time of the undershoot and overshoot was extended by 70 ns and 60 ns, respectively.

Figure 14 shows the transient response comparison among the conventional LDO, the DLDO with the AA loop, and the proposed double-edge-triggered DLDO with the AA loop and the AVC. At the external clock frequency of 8 MHz, the undershoot voltage of the conventional DLDO with the AA technology decreased by 66 mV than that of the conventional DLDO when the load current stepped up from 0.5 mA to 25 mA at the edge time (I_load) of 100 ps. Compared with the conventional DLDO with the AA technology, the undershoot voltage with the proposed double-edge-triggered DLDO can be reduced from 438 mV to 335 mV, and the recovery time was optimized from 14.8 μs to 2.7 μs in the undershoot case and from 10.5 μs to 2.1 μs in the overshoot case. Meanwhile, it can be seen from Figure 14 that the clock frequency was enhanced from 8 MHz to 50 MHz by the AVC. Figure 14 also shows the transient response of the proposed DLDO with and without a load capacitor at a supply of 0.6 V at the different T_edge. As can be seen from Figure 14, the undershoot voltage with the load capacitor was only 21 mV smaller than that without the load capacitor, while the overshoot voltage was almost constant whether the load capacitor exists or not. This verifies that the C_C in the AA technology can reduce the off-chip load capacitor to 0. Furthermore, when the T_edge was 400 ns as in [18], the undershoot voltage and overshoot voltage were decreased to 274 mV and 46.51 mV. Figure 15 shows the transient response of the proposed DLDO with and without a load capacitor at a supply of 1.1 V. The undershoot voltage and overshoot voltage were 230 mV and 46 mV without the load capacitor, respectively. When a load capacitor (C_load) of 50 pF was added, the undershoot voltage and overshoot voltage decreased to 232 mV and 44.8 mV, respectively. Furthermore, the transient response was also enhanced due to the improvement in the clock frequency of the AVC. Overall, the undershoot voltage and overshoot voltage were optimized with a longer T_edge and a load capacitor.

To verify the robustness of the transient responses, the simulation at different process corners and temperatures is depicted in

Table 2. Transient response at different temperatures and process corners.

Temp [°C]	−40 °C @Iload from 0.5 to 25 mA			27 °C @Iload from 0.5 to 25 mA			85 °C @Iload from 0.5 to 25 mA
Corner	FF	TT	SS	FF	TT	SS	FF	TT	SS
Undershoot @ Tr [mV/μs]	329	354	399	292	335	378	268	296	342
	2.46	4.22	8.58	1.8	2.7	4.3	1.22	1.3	3.01
Overshoot @ Tr [mV/μs]	47.5	47.9	48.3	46.8	47.6	48.1	45.3	47.1	47.9
	2.12	3.78	7.57	1.31	2.1	4.03	0.92	1.02	2.88

. The undershoot voltage and overshoot voltage at the FF corner had a smaller spike, and the recovery time became faster than the performances at the TT corner with the same temperature, while the performances at the SS corner behaved just right, in contrast. As a result, the worst undershoot voltage and overshoot voltage were 399 mV with a recovery time of 2.7 μs and 48.3 mV with a recovery time of 2.1 μs, respectively. The reason why the overshoot voltage was almost constant is that V_out jumped to almost the supply voltage when the output voltage suddenly dropped from 25 mA to 0.5 mA.

Table 3. Performance summary and comparison with other DLDOs.

	JSSC’ 18 [19] b	TCAS-II’ 20 [9] b	TCAS-II’ 20 [11] b	TPE’ 20 [18] b	AEU’ 21 [20] a	TPE’ 22 [21] b	TCAS-II’ 23 [22] b	This Work a
Process [nm]	65	65	28	40	45	65	65	180
Gen method of clock	External clock	External clock	External clock	External clock	External clock	VCO	External clock	VCO
Trigger method	Asyn/ SET	Syn/ SET	Syn/ SET	Asyn/ SET	Syn/ SET	Syn/ SET	Asyn/ SET	Syn/ DET
Clock Adaptive	Yes	NO	Yes	NO	NO	Yes	Yes	Yes
Fclk [MHz]	1–240	10	4–64	100	10	500	NA	8–50
VDD [V]	0.5–1	0.6–1.0	0.5–1	0.6–1.1	0.5–1	0.9–1.2	0.7–1.3	0.6–1.1
Vout [V]	0.3–0.45	0.55–0.95	0.45–0.95	0.5–1	0.45–0.95	0.5–1.1	0.65–1.25	0.55–1.05
Vdrop [mV]	50	50	50	100	50	100	50	50
Cload [pF]	400	1000	100	4700	50	200	0	0
Ctotal [pF]	400	1000	100	4700	50	200.5	9.5	50
IQ [μA]	14	10.2	20.1	19.6	22	131	1050	95.13
Iload, max [mA]	5.6	4.5	6.5	20	2	6	80	25
Iload, min [mA]	0.0001	0.1	1	0.4	0.5	0.15	5	0.5
∆ILoad [mA]	1.06	-	2	19	1.5	3	28	24.5
Line regulation [mV/V]	2.3	-	-	-	23.8	-	2.63	4.3
Load regulation [mV/mA]	5.6	4.4	0.0196	1	1.007	0.15	-	0.1265
Tedge [ns]	15.1	10	5	400	1	5	0.1	0.1
∆VOUT [mV]	40	118	92	40	140	80	275	335
Settling Time [μs]	0.1	5.9	0.083	1.3	1.2	0.09	0.0018	2.7
Peak current efficiency [%]	99.8	99.7	99.8	99.9	99.98	99.3	99.7	99.6
Area [mm2]	0.0023	0.0896	0.04173	0.18	0.0064	0.059	0.0925	0.053
FoM1 [ps] [4]	199.359	62.16	46.23	10.2	6.84	232.88	3.498	2.654
FoM2 [pF] [11]	0.7	0.683	0.205	0.387	0.228	1.397	0.15	0.13

^a Simulation results, ^b Measurement results; SET: Single-edge trigger, DET: Double-edge trigger; FoM₁ = C_total × ∆V_out × I_Q/∆I_load²; FoM₂ = C_total × ∆V_out × I_Q/(V_out × ∆I_load).

illustrates the performance parameters of the proposed DLDO in this paper and compares the simulation performances with the state-of-the-art DLDO architectures. In the steady state, the V_drop voltage is always 50 mV for any supply voltage. Specifically, when the supply voltage is 1.1 V, the output voltage is 1.05 V, while the supply voltage is 600 mV and the output voltage is 550 mV. Compared with [18,19], these DLDOs still need a large load capacitor to suppress the voltage fluctuation within 100 mV during the transient response. Compared to works with a fixed clock frequency [9,19,20,21], the AVC between the steady state and the transient response could better balance the transient responses and static current. Although the load current change could achieve a change of 28 mA in [22] at the only load capacitor of 9.5 pF, the DLDO consumed up to the quiescent current of about 1 mA, which degraded the current efficiency. The proposed DLDO can fix the stability issues at any load current and thus allows the output change from the minimum to the maximum load current within an edge time of 100 ps because the clock frequency can be adaptively adjusted based on the output voltage in time. Moreover, even though the power of the AVC is included, the quiescent current of the entire DLDO is still very low, resulting in the two FoMs. Meanwhile, we provide a comparison of the related simulation results with the previous publications [1,2,23,24] in

Table 4. Performance summary and comparison with other analog LDOs.

	Electronics’ 21 [23] a	Electronics’ 22 [24] a	Electronics’ 23 [1] a	Electronics’ 23 [2] a	This Work a
Process [nm]	180	180	180	180	180
Architecture	ALDO	ALDO	ALDO	ALDO	DLDO
VDD [V]	1.297–3.3	1.2–1.8	1.8	2–5	0.6–1.1
Vout [V]	1.2	1	1.5	1.8	0.55–1.05
Vdrop [mV]	97	200	300	200	50
Cload [pF]	50	100	50	5	0
Ctotal [pF]	56.1	107.5	1050	5	50
PowerQ [μW]	11.15	12.36	28.98	132.8	57.07
Iload, max [mA]	50	100	50	300	25
Iload, min [mA]	1	1	0.2	3	0.5
∆ILoad [mA]	50	99	49.8	297	24.5
Line regulation [mV/V]	0.065	2.74	-	0.55	4.3
Load regulation [mV/mA]	0.006	0.034	1450	0.00194	0.1265
Tedge [ns]	1000	100	10	300	0.1
∆VOUT [mV]	666	47	129	153	335
Settling Time [μs]	6.7	0.19	0.2	0.4	2.7
Peak current efficiency [%]	99.9	99.9	99.9	99.9	99.6
Area [mm2]	0.103	0.01524	0.046	0.085	0.053
FoM1 [ps] [4]	0.11	0.005	0.879	0.005	2.654
FoM2 [pF] [11]	0.005	0.0005	0.029	0.0001	0.13

^a Simulation results.

regarding the analog LDOs in electronics. It can be seen from Table 4 that the static power consumption of the recent analog LDOs is comparable to that of the proposed DLDO. Furthermore, the area of these analog LDOs did not include the area of the load capacitor (C_load). The analog LDO could achieve better FoMs than the proposed DLDO because of the small undershoot voltage and overshoot voltage due to a larger load capacitor and a looser T_edge. The main advantages of the proposed DLDO are the ability to achieve an adjustable output voltage, completely circumvent the load capacitor, and a rigorous T_edge of only 0.1 ns at a low power supply (V_DD < 1.2 V).

5. Conclusions

A double-edge-triggered DLDO was proposed with a built-in adaptive VCO clock. With the double-edge-trigger technology, the transient response can be enhanced by 2× without any power increment in the DLDO. In addition, the stability is also relaxed due to the low clock frequency, and the mode of the LCO is optimized as 1. Moreover, the built-in adaptive clock can accelerate the clock frequency from 8 MHz to 50 MHz, which balances the recovery time in the transient response and the power consumption in the steady state. The post-simulation results using a standard 0.18 μm CMOS process demonstrated that the maximum current is 99.6% with the self-clock comparators. Furthermore, benefiting from the process scaling, the proposed DLDO will be very suitable for ultra-low-voltage and ultra-low-power integrated digital circuits and systems.