Search Results (38)

An Analog-to-Digital Converter (ADC) is an indispensable part of image sensor systems. This paper presents a silicon-based 13-bit 100 kS/s two-step single-slope analog-to-digital converter (TS-SS ADC) for infrared image sensors with a frame rate of 100 Hz. For the charge leakage and offset voltage issues inherent in conventional TS-SS ADC, a four-terminal comparator was employed to resolve the fine ramp voltage offset caused by charge redistribution in storage and parasitic capacitors. In addition, a current-steering digital-to-analog converter (DAC) was adopted to calibrate the voltage reference of the dynamic comparator and mitigate differential nonlinearity (DNL)/integral nonlinearity (INL). To eliminate quantization dead zones, a 1-bit redundancy was incorporated into the fine quantization circuit. Finally, the quantization scheme consisted of 7-bit coarse quantization followed by 7-bit fine quantization. The ADC was implemented using an SMIC 55 nm processSemiconductor Manufacturing International Corporation, Shanghai, China. The post-simulation results show that when the power supply is 3.3 V, the ADC achieves a quantization range of 1.3 V–3 V. Operating at a 100 kS/s sampling rate, the proposed ADC exhibits an effective number of bits (ENOBs) of 11.86, a spurious-free dynamic range (SFDR) of 97.45 dB, and a signal-to-noise-and-distortion ratio (SNDR) of 73.13 dB. The power consumption of the ADC was 22.18 mW. Full article

In application domains where severe environmental conditions are unavoidable, including high-energy physics and nuclear power plants, accurate and dependable time-to-digital converters (TDCs) are essential components. Single-event upsets (SEUs) associated with the configuration memory of field-programmable gate array (FPGA)-based implementations are becoming common sources of performance degradation even in terrestrial areas. Hence, the need to test and mitigate the effects of SEUs on FPGA-based TDCs is crucial to ensure that the design achieves reliable performance under critical conditions. The TMR SEM IP provides real-time fault injection, and dynamic SEU monitoring and correction in safety critical conditions without intervening with the functionality of the system, unlike traditional fault injection methods. This paper presents a scalable and fast fault emulation framework that tests the effects of SEUs on the configuration memory of a 5.7 ps-resolution TDC implemented on ZedBoard. The experimental results demonstrate that the standard deviation in mean bin width is 2.4964 ps for the golden TDC, but a 0.8% degradation in the deviation is observed when 3 million SEUs are injected, which corresponds to a 0.02 ps increment. Moreover, as the number of SEUs increases, the degradation in the RMS integral non-linearity (INL) of the TDC also increases, which shows 0.04 LSB (6.8%) and 0.05 LSB (8.8%) increments for 1 million and 3 million SEUs injected, respectively. The RMS differential non-linearity (DNL) of the faulty TDC with 3 million SEUs injected shows a 0.035 LSB (0.8%) increase compared to the golden TDC. Full article

This paper proposes a low-power 10-bit 20 MS/s pipelined analog-to-digital converter (ADC) designed for the burgeoning needs of low-data-rate communication systems, particularly within the Internet of Things (IoT) domain. To reduce power usage, multiple power-saving techniques are combined, such as sample-and-hold amplifier-less (SHA-less) architecture, capacitor scaling, and dynamic comparators. In addition, this paper presents a novel operational amplifier (op-amp) with gain boosting, featuring a dual-input differential pair that enables internal pipeline stage switching, effectively alleviating the crosstalk and memory effects inherent in conventional shared op-amp configurations, thereby further reducing power consumption. A prototype ADC was fabricated in a 180 nm CMOS process and the core size was 0.333 mm². The ADC implemented operated at a 20 MHz sampling rate under a 1.8 V supply voltage. It achieved a spurious-free dynamic range (SFDR) of 61.83 dB and a signal-to-noise-and-distortion ratio (SNDR) of 54.15 dB while demonstrating a maximum differential non-linearity (DNL) of 0.36 least significant bit (LSB) and a maximum integral non-linearity (INL) of 0.67 LSB. Notably, the ADC consumed less than 5 mW of power at the mentioned sampling frequency, showcasing excellent power efficiency. Full article

This paper presents a novel high-precision 11-bit single-slope/successive approximation register analog-to-digital converter (SS/SAR ADC) architecture specifically designed for CMOS image sensors (CISs). The proposed design solves critical challenges in conventional ADCs by utilizing only two reference voltages, thereby minimizing voltage mismatch and completely eliminating the need for complex switch arrays. This unique approach reduces the transistor count by 64 per column ADC, significantly enhancing area efficiency and circuit simplicity. Furthermore, a groundbreaking on-chip fine step range calibration technique is introduced to mitigate the impact of parasitic capacitance, ensuring the precise alignment between coarse and fine steps and achieving exceptional linearity. Fabricated using a 0.18-µm CMOS process, the ADC demonstrates superior performance metrics, including a differential nonlinearity (DNL) of −1/+1.86 LSB, an integral nonlinearity (INL) of −2.74/+2.79 LSB, an effective number of bits (ENOB) of 8.3 bits, and a signal-to-noise and distortion ratio (SNDR) of 51.77 dB. Operating at 240 kS/s with a power consumption of 22.16 µW, the ADC achieves an outstanding figure-of-merit (${\mathrm{FOM}}_W$) of 0.291 pJ/step. These results demonstrate the proposed architecture’s potential as a transformative solution for high-speed, energy-efficient CIS applications. Full article

This study investigated implementation strategies to optimize the precision of Tapped Delay Line (TDL) Time-to-Digital Converters (TDCs) designed for Xilinx 20 nm UltraScale Field-Programmable Gate Arrays (FPGAs). This optimization process aims to bridge the performance gap between FPGA-based TDCs, which are more flexible and suitable for fast prototyping, and the better-performing Application-Specific Integrated Circuit (ASIC) solutions, making FPGA-based TDCs viable for cutting-edge applications. Our key areas of focus included the optimal design of the decoder, the degree of sub-interpolation, and the placement of TDLs, with particular emphasis on the clocking distribution scheme within the Configurable Logic Block (CLB) to minimize the effects of Bubble Errors (BEs) and quantization error. The research led to the development and comparison of multiple TDL TDC solutions implemented on a Kintex UltraScale device (i.e., XCKU040-2FFVA1156E) housed on a KCU105 general-purpose Evaluation Board (EVB). From these, two main solutions emerged: one with high precision and one with low area. The first one was characterized by a Single-Shot Precision (SSP) of 2.64 ps r.m.s., and by Differential and Integral Non-Linearity (DNL/INL) Errors of 0.523 ps and 16.939 ps, respectively, occupying 883 CLBs and 126 kb of Block RAM (BRAM). The second one had an SSP of 3.75 ps r.m.s., a DNL of 0.599 ps, and an INL of 7.151 ps, and it occupies only 259 CLBs and 72 kb of BRAM. Full article

Over the last ten years, the need for high-resolution time-domain digital signal production has grown exponentially. More than ever, applications call for a digital-to-time converter (DTC) that is extremely accurate and precise. Skew compensation and camera shutter operation represent just a few examples of such applications. The advantages of adopting a flexible and rapid time-to-market strategy focused on fast prototyping using programmable logic devices—such as field-programmable gate arrays (FPGAs) and system-on-chip (SoC)—have become increasingly evident. These benefits outweigh those of performance-focused yet expensive application-specific integrated circuits (ASICs). Despite the availability of various architectures, the high non-recurring engineering (NRE) costs make them unsuitable for low-volume production, especially in research or prototyping environments. To address this trend, we introduce an innovative DTC IP-Core with a resolution, also known as least significant bit (LSB), of 52 ps, compatible with all Xilinx 7-Series FPGAs and SoCs. Measurements have been performed on a low-end Artix-7 XC7A100TFTG256-2, guaranteeing a jitter lower than 50 ps r.m.s. and offering a high dynamic range up to 56 ms. With resource utilization below 1% and a dynamic power dissipation of 285 mW for our target FPGA, the design maintains excellent differential and integral nonlinearity errors (DNL/INL) of 1.19 LSB and 1.56 LSB, respectively. Full article

Low-power portable devices play a major role in IoT applications, where the analog-to-digital converters (ADCs) are very important components for the processing of analog signals. In this paper, a 5-bit two-step flash ADC with a low-power double-tail dynamic comparator (DTDC) using the control switching technique is presented. The most significant bit (MSB) in the proposed design is produced by only one low-power DTDC in the first stage, and the remaining bits are generated by the flash ADC in the second stage with the help of an auto-control circuit. A control circuit produced reference voltages with respect to the control input and mid-point voltage (${\mathrm{V}}_k$). The proposed design and simulations are carried out using 90 nm CMOS technology. The result shows that the peak differential non-linearity (DNL) and integral non-linearity (INL) are +0.60/−0.69 and +0.66/−0.40 LSB, respectively. The signal-to-noise and distortion ratio (SNDR) for an input signal having a frequency of 1.75 MHz is found to be 30.31 dB. The total power consumption of the proposed design is significantly reduced, which is 439.178 $\mathsf{\mu }$W for a supply voltage of 1.2 V. The figure of merit (FOM) is about 0.054 pJ/conversion step at 250 MS/s. The present design provides low power consumption and occupies less area compared to the existing works. Full article

Digital histogram generation for time-resolved measurements with single-photon avalanche diode (SPAD) sensors requires the storage of many timestamp signals. This work presents a mixed-signal time-to-digital converter (TDC) that uses analog storage to achieve an area-efficient design that can be integrated in large SPAD arrays. Fabricated using a 150 nm CMOS process, the prototype occupies an area of only 18.3 µm × 36.5 µm, a notable size reduction compared to conventional designs. The experimental results demonstrated high performance, with an integral nonlinearity (INL) of 0.35/0.14 least significant bit (LSB) and a differential nonlinearity (DNL) of 0.14/−0.12 LSB. In addition, the proposed TDC can support the construction of histograms comprising up to 512 bins, making it an effective solution to accommodate a wide range of resolution requirements. Validated in a point-of-care (PoC) device for fluorescence lifetime measurements, it distinguished between lifetimes of approximately 4.1 ns, 3.6 ns and 80 ns with the Alexa Fluor (AF) 546 and 568 dyes and Quantum Dot (QD) 705, respectively. The analog storage design and area-efficient architecture offer a novel approach to integrating TDCs in SPAD-based systems, with potential applications in medical diagnostics and beyond. Full article

This two-part work develops a comprehensive toolbox for the statistical characterization of nonlinear distortions of DAC-generated signal constellations to be transmitted over communication links, be they electronic (wireline, wireless) or photonic, Mach–Zehnder modulator (MZM)-based optical interconnects in particular. The all-analytic toolbox developed here delivers closed-form expressions for the second-order statistics (means, variances) of all relevant constellation metrics of the DACs’ building blocks and of DAC-driven MZM-based optical transmitters, all the way to the slicer in the optical receivers over a linear channel with coherent detection. The key impairment targeted by the model is the random current mismatch of the ASIC devices implementing the DAC drivers. In particular the (skew-)centrosymmetry of the DAC metrics is formally derived and explored. A key applicative insight is that the conventional INL/DNL (Integral NonLinearity/Differential NonLinearity) constellation metrics, widely adopted in the electronic devices and circuits community, are not quite useful in the context of communication systems, since these metrics are ill-suited to predict communication link statistical performance. To rectify this deficiency of existing electronic DAC metrics, we introduce modified variants of the INL|DNL, namely the integral error vector (IEV) and the differential error vector (DEV) constellation metrics. The new IEV|DEV represent straightforward predictors of relevant communication-minded metrics: error vector magnitude (EVM) treated here in Part I, and Symbol/Bit Error-Rates (SER, BER) treated in the upcoming Part II of this paper. Full article

Time-to-digital converters (TDCs) with superior performance are in high demand in application domains like light detection and ranging (LIDAR), nuclear physics, and time interval counters. One of the interesting architectures for field-programmable gate array (FPGA)-based TDCs is the tapped delay line (TDL) approach with carry chains as delay elements. However, the resolution of TDL-TDCs is limited, and linearity is weakened by the ultra-wide bins that correspond to the FPGA’s long routing wires crossing into another clock area. This paper presents wave union TDC using FPGA internal routing wires as delay elements to subdivide ultra-wide bins. The Zynq Evaluation and Development (ZED) board is used to implement and test the wave union types: A (WU-A) and B (WU-B) TDCs. According to experimental data, the WU-A TDC based on an 8 × 128 matrix of counters has a resolution of 5.7 ps, an integral nonlinearity (INL) of 1.1170 LSB (RMS), and a differential nonlinearity of 0.329 LSB (RMS). WU-A TDC improves DNL and INL by 19% and 57%, respectively, over ordinary TDC. The WU-B TDC uses an average of sixteen different time measurements, resulting in an effective resolution of up to 0.356 ps, a DNL of 0.60 LSB (RMS), and an INL of 1.04 LSB (RMS). These characteristics make the TDC suitable for time-of-flight applications such as LIDAR and for other general-purpose scientific instruments. Full article

This work presents a rad-hard 12-bit 3 MS/s resistor string DAC for space applications. The converter has been developed using rad-hardened techniques both at architecture and layout levels starting from a conventional topology. The design considers the different effects of the radiation that could damage the circuits in space environments. The DAC has been developed and integrated a standard CMOS 0.13 μm technology by IHP, using RHBD techniques. Low Earth Orbit (LEO) requires a TID value of around 100 krad (Si), according to the expected length of the mission. The temperature range is between −55 °C and 125 °C. The DAC power budget is similar to that of terrestrial applications. The measured INL (Integral Non-Linearity) and DNL (Differential Non-Linearity) are better than 0.2 LSB, while the ENOB (Effective Number Of Bits) at a 3 MS/s clock exceeds 9.7 bits while loading a 10 pF capacitor. The DAC has been characterized under radiation, showing a fluctuation in the analog output lower than 2 LSB (mainly due to measurement uncertainty) up to 500 krad (Si). Power consumption shows a negligible increase, too. A 10-bit version of the same DAC as the downscaled 12-bit one has been developed as well. Full article

A 16-bit 125 MS/s pipelined analog-to-digital converter (ADC) implemented in a 0.18 $\mathsf{\mu }$m CMOS process is presented in this paper. A sample-and-hold amplifier-less (SHA-less) modified 2.5-bit front-end is adopted, which splits the sampling capacitor in half to eliminate the common-mode voltage buffer. The multiplying-digital-to-analog converter (MDAC) in the first pipeline stage is modified by reusing the sampling capacitor in a foreground digital calibration for improving the ADC linearity. This design can circumvent a dedicated reference buffer to generate the calibration voltages at all comparator thresholds. By calibrating the ADC in the digital domain, the integral non-linearity (INL) is improved from −9.2/10 LSB to −3/2.2 LSB, and the spurious-free dynamic range (SFDR) is optimized by over 8dB. The ADC consumes 154mW (reference buffer and clock included) from a 1.8 V supply. Full article

This study introduces a readout integrated circuit (ROIC) tailored for multi-gas sensor arrays featuring a proposed baseline calibration scheme aimed at mitigating the issue of sensor baseline variation. Unlike previous approaches, the proposed scheme stores each sensor’s baseline value and dynamically updates the signal extraction range accordingly during ROIC operation. This adjustment allows for the optimal use of the ROIC’s dynamic range, enhancing sensor uniformity and accuracy without the need for complex additional circuitry or advanced post-processing algorithms. We fabricated a prototype ROIC using a 180 nm CMOS process, achieving a low power consumption of 0.43 mW and a conversion rate of 50 kSPS. The prototype boasts an integrated noise level of 9.9 μV_RMS across a frequency range of 0.1 Hz to 5 kHz and a dynamic range of 142.6 dB, coupled with superior linearity, indicated by a maximum integral non-linearity (INL) of −75.71 dB. This design significantly reduces sensor offset scattering to within 1 LSB of the A/D reference scale. In this study, the efficacy of the proposed scheme was validated using Figaro TGS-2600. The ROIC targets a sensitivity range from 0.54 to 0.23 for gas concentrations ranging from 5 ppm to 20 ppm and a resolution of 39 Ω for sensor resistance range from 10 kΩ to 90 kΩ. The enhancements in performance make the proposed ROIC a promising solution for precise gas concentration detection in sensor applications. Full article

This paper presents a digital calibration method for a 10-bit noise-shaping Successive Approximation Register Analog to Digital Converter (SAR ADC). The proposed calibration method is inspired by its Data Weight Averaging (DWA) counterpart, but stays static, while achieving a similar Integral Nonlinearity (INL) and 1.3 dB better Signal-to-Noise Ratio (SNR) in measurements without oversampling. This advantage in SNR holds until an Oversampling Ratio (OSR) of 2 for the proposed method, which also saves 50 % power. At a 1.2 V power supply, the ADC consumes a power of 70 µW at a conversion rate of 50 kHz. Fabricated using 55 nm Complementary Metal Oxide Semiconductor (CMOS) Metal-Oxide-Metal Capacitor (MOMCAP) technology, it occupies an active area of 370 µm × 350 µm, when achieving an INL of 0.3 Least Significant Bit (LSB) and an SNR of 66.9 dB at an OSR of 8. Full article

In this paper, two of the most common calibration methods of synchronous TDCs, which are the bin-by-bin calibration and the average-bin-width calibration, are first presented and compared. Then, an innovative new robust calibration method for asynchronous TDCs is proposed and evaluated. Simulation results showed that: (i) For a synchronous TDC, the bin-by-bin calibration, applied to a histogram, does not improve the TDC’s differential non-linearity (DNL); nevertheless, it improves its Integral Non-Linearity (INL), whereas the average-bin-width calibration significantly improves both the DNL and the INL. (ii) For an asynchronous TDC, the DNL can be improved up to 10 times by applying the bin–by-bin calibration, whereas the proposed method is almost independent of the non-linearity of the TDC and can improve the DNL up to 100 times. The simulation results were confirmed by experiments carried out using real TDCs implemented on a Cyclone V SoC-FPGA. For an asynchronous TDC, the proposed calibration method is 10 times better than the bin-by-bin method in terms of the DNL improvement. Full article