Search Results (604)

With the rapid proliferation of real-time digital communication, particularly in multimedia applications, securing transmitted image data has become a vital concern. While chaotic systems have shown strong potential for cryptographic use, most existing approaches rely on low-dimensional, integer-order architectures, limiting their complexity and resistance to attacks. Advances in fractional calculus and memristive technologies offer new avenues for enhancing security through more complex and tunable dynamics. However, the practical deployment of high-dimensional fractional-order memristive chaotic systems in hardware remains underexplored. This study addresses this gap by presenting a secure image transmission system implemented on a field-programmable gate array (FPGA) using a universal high-dimensional memristive chaotic topology with arbitrary-order dynamics. The design leverages four- and five-dimensional hyperchaotic oscillators, analyzed through bifurcation diagrams and Lyapunov exponents. To enable efficient hardware realization, the chaotic dynamics are approximated using the explicit fractional-order Runge–Kutta (EFORK) method with the Caputo fractional derivative, implemented in VHDL. Deployed on the Xilinx Artix-7 AC701 platform, synchronized master–slave chaotic generators drive a multi-stage stream cipher. This encryption process supports both RGB and grayscale images. Evaluation shows strong cryptographic properties: correlation of $-6.1081\times {10}^{-5}$, entropy of 7.9991, NPCR of 99.9776%, UACI of 33.4154%, and a key space of $2^{1344}$, confirming high security and robustness. Full article

In this article, thermal investigation methods for electrically insulating and thermally conductive substrate materials will be presented. The investigations were performed in their real-world application environment, i.e., in the form of IGBT (insulated gate bipolar transistor) module substrate plates. First, the overall thermal resistance and thermal structure function of the system in a multivariable parameter space were revealed using CFD (computational fluid dynamics) simulations. Afterwards, thermal transient testing was performed on real samples, with the help of which the thermal resistance values of the modules were determined using the thermal dual interface test method. The presented tests are not intended to determine material parameters, but to rank different substrate materials based on their thermal performance. Full article

AlGaN-based high-electron-mobility transistors are critical for next-generation power electronics and radio-frequency applications, yet achieving stable enhancement-mode operation with a high threshold voltage remains a key challenge. In this work, we designed p-AlGaN superlattices with different structures and performed energy band structure simulations using the device simulation software Silvaco. The results demonstrate that thin barrier structures lead to reduced acceptor incorporation, thereby decreasing the number of ionized acceptors, while facilitating vertical hole transport. Superlattice samples with varying periodic thicknesses were grown via metal-organic chemical vapor deposition, and their crystalline quality and electrical properties were characterized. The findings reveal that although gradient-thickness barriers contribute to enhancing hole concentration, the presence of thick barrier layers restricts hole tunneling and induces stronger scattering, ultimately increasing resistivity. In addition, we simulated the structure of the enhancement-mode HEMT with p-AlGaN as the under-gate material. Analysis of its energy band structure and channel carrier concentration indicates that adopting p-AlGaN superlattices as the under-gate material facilitates achieving a higher threshold voltage in enhancement-mode HEMT devices, which is crucial for improving device reliability and reducing power loss in practical applications such as electric vehicles. Full article

Carbon nanotube field-effect transistors (CNTFETs) are becoming a strong competitor for the next generation of high-performance, energy-efficient integrated circuits due to their near-ballistic carrier transport characteristics and excellent suppression of short-channel effects. However, CNT FETs with large diameters and small band gaps exhibit obvious bipolarity, and gate-induced drain leakage (GIDL) contributes significantly to the off-state leakage current. Although the asymmetric gate strategy and feedback gate (FBG) structures proposed so far have shown the potential to suppress CNT FET leakage currents, the devices still lack scalability. Based on the analysis of the conduction mechanism of existing self-aligned gate structures, this study innovatively proposed a design strategy to extend the length of the source–drain epitaxial region (L_ext) under a vertically stacked architecture. While maintaining a high drive current, this structure effectively suppresses the quantum tunneling effect on the drain side, thereby reducing the off-state leakage current (I_off = 10⁻¹⁰ A), and has good scaling characteristics and leakage current suppression characteristics between gate lengths of 200 nm and 25 nm. For the sidewall gate architecture, this work also uses single-walled carbon nanotubes (SWCNTs) as the channel material and uses metal source and drain electrodes with good work function matching to achieve low-resistance ohmic contact. This solution has significant advantages in structural adjustability and contact quality and can significantly reduce the off-state current (I_off = 10⁻¹⁴ A). At the same time, it can solve the problem of off-state current suppression failure when the gate length of the vertical stacking structure is 10 nm (the total channel length is 30 nm) and has good scalability. Full article

Gallium nitride high-electron-mobility transistors (GaN HEMTs) are critical for high-power applications like AI power supplies and robotics but face reliability challenges due to increased dynamic ON-resistance (R_{DS_ON}) from electrical and thermomechanical stresses. This paper presents a novel self-calibrating temperature-sensitive electrical parameter (TSEP) model that uses gate leakage current (I_G) to estimate junction temperature with high accuracy, uniquely addressing aging effects overlooked in prior studies. By integrating I_G, aging-induced degradation, and failure-in-time (FIT) models, the approach achieves a junction temperature estimation error of less than 1%. Long-term hard-switching tests confirm its effectiveness, with calibrated R_{DS_ON} measurements enabling precise remaining useful life (RUL) predictions. This methodology significantly improves GaN HEMT reliability assessment, enhancing their performance in resilient power electronics systems. Full article

Dynamic on-resistance (R_ON) of commercial GaN on Si normally off high-electron-mobility transistor (HEMT) devices is a very important parameter because it is responsible for conduction losses that limit the power conversion efficiency of high-power switching converters. Due to charge trapping effects, dynamic R_ON is always higher than in DC, a behavior known as current collapse. To study how short-time dynamics of charge trapping and release affects R_ON we use rectangular 0–5 V gate voltage pulses with durations in the 1 μs to 100 μs range. Measurements are first carried out for single pulses of increasing duration, and it is found that R_ON depends on both pulse duration and drain current I_D, being higher at shorter pulse durations and lower I_D. For a train of five pulses, R_ON decreases with pulse number, reaching a steady state after a time interval of 100 μs. The response to a five pulses train is compared to that of a square-wave signal to study the time evolution of R_ON toward a dynamic steady state. The DC R_ON is also measured, and it is a factor of ten smaller than dynamic R_ON at the same I_D. This confirms that a reduction in trapped charges takes place in DC as compared to the square-wave switching operation. Additional off-state stress tests at V_DS = 55 V reveal the presence of residual surface traps in the drain access region, leading to four times increase in R_ON in comparison to pristine devices. Finally, the dynamic R_ON is also measured by the double-pulse test (DPT) technique with inductive load, giving a good agreement with results from single-pulse measurements. Full article

Quantum neural networks (QNNs) represent an emerging technology that uses a quantum computer for neural network computations. The QNNs have demonstrated potential advantages over classical neural networks in certain tasks. As a core component of a QNN, the parameterized quantum circuit (PQC) plays a crucial role in determining the QNN’s overall performance. However, quantum circuit architectures designed manually based on experience or using specific hardware structures can suffer from inefficiency due to the introduction of redundant quantum gates, which amplifies the impact of noise on system performance. Recent studies have suggested that the advantages of quantum evolutionary algorithms (QEAs) in terms of precision and convergence speed can provide an effective solution to quantum circuit architecture-related problems. Currently, most QEAs adopt a fixed rotation mode in the evolution process, and a lack of an adaptive updating mode can cause the QEAs to fall into a local optimum and make it difficult for them to converge. To address these problems, this study proposes an adaptive quantum evolution algorithm (AQEA). First, an adaptive mechanism is introduced to the evolution process, and the strategy of combining two dynamic rotation angles is adopted. Second, to prevent the fluctuations of the population’s offspring, the elite retention of the parents is used to ensure the inheritance of good genes. Finally, when the population falls into a local optimum, a quantum catastrophe mechanism is employed to break the current population state. The experimental results show that compared with the QNN structure based on manual design and QEA search, the proposed AQEA can reduce the number of network parameters by up to 20% and increase the accuracy by 7.21%. Moreover, in noisy environments, the AQEA-optimized circuit outperforms traditional circuits in maintaining high fidelity, and its excellent noise resistance provides strong support for the reliability of quantum computing. Full article

Electromagnetic interference (EMI) has become a significant issue as electronic devices become more integrated and achieve high performance. In order to operate at high performance in an integrated system, a high-frequency clock signal is essential to enhance processing speed. However, the harmonic component of the clock signal or gate signal is one of the major EMI sources that can cause peripheral devices to malfunction and affect their stability and reliability. In this paper, harmonic component analysis of the MOSFET gate signal which depends on gate resistance is conducted. Based on theoretical analysis using Fourier series expansion, gate resistance contributes to harmonic components that are determined by the rising and falling times of a gate signal. Simulation and measurement are conducted using a buck converter as a practical application. The theoretical analysis is validated by simulation and experimental results demonstrate that the magnitude of the harmonics is reduced because increasing the gate resistance extends the rising and falling times. Full article

Background/Objectives: Ovarian follicular cysts (OFCs) in dairy cows represent a significant cause of infertility and share striking similarities with polycystic ovary syndrome (PCOS) in women. This study aimed to elucidate the molecular mechanisms underlying OFCs and their relevance to PCOS by profiling differentially expressed (DE) microRNAs (miRNAs) and constructing integrative RNA interaction networks. Methods: Expression analysis of 84 bovine miRNAs was conducted in antral follicular fluid from normal and cystic follicles using miScript PCR arrays. Bioinformatic tools including miRBase, miRNet, and STRING were employed to predict miRNA targets, construct protein–protein interaction networks, and perform gene ontology and KEGG pathway enrichment. Network analyses integrated miRNAs with coding (mRNAs) and non-coding RNAs (circRNAs, lncRNAs, snRNAs). Results: Seventeen miRNAs were significantly dysregulated in OFCs, including bta-miR-18a, bta-miR-30e-5p, and bta-miR-15b-5p, which were associated with follicular arrest, insulin resistance, and impaired steroidogenesis. Upregulated miRNAs such as bta-miR-132 and bta-miR-145 correlated with inflammation, oxidative stress, and intrafollicular androgen excess. Key regulatory lncRNAs such as Nuclear Enriched Abundant Transcript 1 (NEAT1), Potassium Voltage-Gated Channel Subfamily Q Member 1 Opposite Strand/Antisense Transcript 1 (KCNQ1OT1), Taurine-Upregulated 1 (TUG1), and X Inactive Specific Transcript (XIST), as well as circRNA/pseudogene hubs, were identified, targeting pathways involved in metabolism, inflammation, steroidogenesis, cell cycle, and apoptosis. Conclusions: The observed transcriptomic changes mirror core features of human PCOS, supporting the use of bovine OFCs as a comparative model. These findings provide novel insights into the regulatory RNA networks driving ovarian dysfunction and suggest potential biomarkers and therapeutic targets for reproductive disorders. This network-based approach enhances our understanding of the complex transcriptomic landscape associated with follicular pathologies in both cattle and women. Full article

This paper investigates the short-circuit characteristics of 1.2 kV symmetrical and asymmetrical trench-gate SiC MOSFETs. Based on the self-designed short-circuit test platform, single and repetitive short-circuit tests were carried out to characterize the short-circuit capability of the devices under different electrical stresses through the short-circuit withstanding time (SCWT). Notably, the asymmetric trench structure exhibited a superior short-circuit capability under identical test conditions, achieving a longer SCWT compared to its symmetrical counterpart. Moreover, TCAD was used to model the two devices and fit the short-circuit current waveforms to study the difference in short-circuit characteristics under different conditions. For the degradation of the devices after repetitive short-circuit stresses, repetitive short-circuit pulse experiments were conducted for the two groove structures separately. The asymmetric trench devices show a positive Vth drift, increasing on-resistance, increasing C_gs and C_ds, and decreasing C_gd, while the symmetric trench devices show a negative Vth drift, decreasing on-resistance, and inverse variation in capacitance parameters. Both blocking voltages are degraded, but the gate-source leakage current remains low, indicating that the gate oxide has not yet been damaged. Full article

The growing need for adaptable and efficient hardware-based encryption methods has led to increased interest in unconventional models such as cellular automata (CA). This study presents the hardware design and the field programmable gate array (FPGA)-based implementation of a multi-layer symmetric block encryption algorithm built on the principles of reversible cellular automata (RCA). The algorithm operates on 128-bit plaintext blocks processed over iterative rounds and integrates five RCA components, each assigned with specific transformation roles to ensure high data diffusion. A 256-bit secret key that governs the rule configuration yields a vast keyspace, significantly enhancing resistance to brute-force attacks. Key elements such as rule-based evolution, neighborhood radius, and hybrid cellular automata for random state generation are also integrated into the hardware logic. All cryptographic components, including initialization, encryption logic, and control, are built exclusively using CA, ensuring design consistency and low complexity. The cryptosystem takes advantage of the localized interactions and naturally parallel CA structure, which align with the architecture of FPGA devices, making them a suitable platform for implementing such encryption schemes. The results demonstrate the feasibility of deploying multi-layer RCA encryption schemes on reconfigurable devices and provide a viable path toward efficient and secure hardware-level encryption systems. Full article

Triatoma dimidiata is a widely distributed vector of Trypanosoma cruzi in Mexico and Central America, found across a range of habitats from sylvatic to domestic. Vector control has relied heavily on indoor residual spraying with pyrethroids; however, reinfestation and emerging resistance have limited its long-term effectiveness. In this study, we analyzed the genetic diversity and population structure of T. dimidiata from Veracruz, Oaxaca, and Yucatan using mitochondrial markers (cyt b and ND4) and screened for knockdown resistance (kdr)-type mutations in the voltage-gated sodium channel (VGSC) gene. High haplotype diversity and regional differentiation were observed, with most genetic variation occurring between populations. The ND4 marker provided greater resolution than cyt b, revealing ten haplotypes and supporting evidence of recent population expansion. Haplotype networks showed clear geographic segregation, particularly between populations east and west of the Isthmus of Tehuantepec. The L925I mutation, highly associated with pyrethroid resistance, was detected for the first time in Mexican populations of T. dimidiata, albeit at low frequencies. These findings highlight the importance of integrating population genetic data and resistance surveillance into regionally adapted vector control strategies for Chagas disease. Full article

Elevator fault diagnosis is critical for ensuring operational safety and reliability in modern vertical transportation systems. Traditional approaches, which rely on time- and frequency-domain signal analysis, often struggle with the issues such as noise sensitivity, inadequate feature extraction, and limited adaptability to complex scenarios. To address these challenges, this paper proposes a Graph Attention Recurrent Network (GARN) which integrates graph-structured signal representation with spatiotemporal feature learning. The GARN employs a limited penetrable visibility graph to transform raw vibration signals into noise-robust graph topologies, preserving critical patterns while suppressing high-frequency noise through controlled edge penetration. An adaptive attention mechanism dynamically fuses triaxial features to prioritize the most relevant information for fault diagnosis. The GARN combines a graph convolutional network to extract spatial correlations and a gated recurrent unit to capture temporal fault progression, enabling holistic and accurate fault classification. Experimental results based on real-world elevator datasets demonstrate the superior performance of the GARN, showcasing its strong noise resistance, adaptability to complex fault conditions, and ability to provide reliable and timely fault diagnosis, making it a robust solution for modern elevator systems. Full article

In situ estimations of gate oxide degradation and junction temperature are critical for SiC MOSFETs, as these parameters are key for device-level health management. However, the indicators used in existing evaluation methods primarily focus on one aspect and do not effectively integrate the assessment of both targets, as they require different indicators. To address this problem, this paper proposes a unified evaluation method that uses a single indicator to simultaneously estimate both gate oxide degradation and junction temperature. An on-state resistance (R_ON) model is used as the indicator. The R_ON model is first proposed to characterize the influence of temperature and gate degradation on R_ON. An iterative approach is introduced to determine the R_ON model parameters, utilizing R_ON measurements across various temperatures and gate degradation levels, while accounting for the physical characteristics of the parameters. Furthermore, an in situ estimation method for gate degradation and junction temperature is developed based on a two-level turn-on strategy. By analyzing R_ON before and after gate voltage changes, the gate degradation level and junction temperature can be simultaneously estimated. The proposed method’s effectiveness is demonstrated in a DC-DC converter application. Full article

As a novel energy-saving and maneuvering device for ships, the gate rudder system (GRS) functions similarly to an accelerating duct. While providing additional thrust, its independently controllable rudder blades on either side of the propeller also enhance ship maneuverability. The GRS was first fully implemented on a container ship in Japan, demonstrating improved propulsion efficiency, fuel savings, and excellent performance in maneuvering, noise, and vibration reduction. In recent years, extensive research has been conducted on the hydrodynamic performance, acoustic characteristics, and energy-saving effects of the GRS. However, certain gaps remain in the research, such as a lack of systematic studies on optimal GRS design in the publicly available literature. Only Ahmet Yusuf Gurkan has investigated the sensitivity of propulsion performance to parameters such as rudder angle, rudder X-shift, rudder tip skewness, and blade tip chord ratio. Therefore, this study employs the JBC benchmark vessel and adopts a coupled CFD-CAESES approach to develop a matching optimization design for the GRS. The influence of geometric parameters—including GRS airfoil camber, maximum camber position, chord length, thickness, distance from the leading edge to the propeller plane, and the gap between the GRS and propeller blades—on ship propulsion performance is investigated. The sensitivity of these design variables to propulsion performance is analyzed, and the optimal GRS design is selected to predict and evaluate its energy-saving effects. This research establishes a rapid and comprehensive CFD-based optimization methodology for GRS matching design. The findings indicate that the gap between the GRS and propeller, the distance from the GRS to the stern, and the airfoil camber of the GRS significantly contribute to various performance responses. After GRS installation, the viscous pressure resistance of the JBC ship decreases, resulting in an 8.05% energy-saving effect at the designated speed. Full article