Switching Noise Harmonic Reduction for EMI Improvement Through Rising and Falling Time Control Using Gate Resistance

Abstract

Electromagnetic interference (EMI) has become a significant issue as electronic devices become more integrated and achieve high performance. In order to operate at high performance in an integrated system, a high-frequency clock signal is essential to enhance processing speed. However, the harmonic component of the clock signal or gate signal is one of the major EMI sources that can cause peripheral devices to malfunction and affect their stability and reliability. In this paper, harmonic component analysis of the MOSFET gate signal which depends on gate resistance is conducted. Based on theoretical analysis using Fourier series expansion, gate resistance contributes to harmonic components that are determined by the rising and falling times of a gate signal. Simulation and measurement are conducted using a buck converter as a practical application. The theoretical analysis is validated by simulation and experimental results demonstrate that the magnitude of the harmonics is reduced because increasing the gate resistance extends the rising and falling times.

1. Introduction

Recently, electronic devices have been increasingly integrated and designed for enhanced performance. For example, the rated power, number of transistors, and clock frequency of microprocessors which are widely used in electronic devices have been gradually increasing [1,2]. Specifically, high-frequency clock signals, one of the major electromagnetic interference (EMI) sources, cause EMI problems in peripheral devices.

Typically, EMI can affect communication between the transmitter and receiver, resulting in a malfunction of devices. For a practical case of an EMI effect in communication, ambient noise in the image around unshielded magnetic resonance imaging (MRI) was investigated, where the noise components generated by external EMI coils interfere with the receiver coil of the MRI, leading to distorted images [3,4].

In practical power electronics applications, EMI is a critical concern due to the frequent variations in voltage and current caused by switching operations and relatively high-power operating conditions. Controlling EMI is essential in power electronics. For this reason, many studies have been conducted to reduce the EMI generated by power conversion systems. For example, studies have been conducted not only on EMI reduction in wireless charging electric vehicles [5,6], but also on the effects of EMI and corresponding mitigation strategies in unmanned aerial vehicles [7,8].

Common approaches include the use of additional filters in power conversion circuits [9,10] and spread spectrum techniques, which employ variable clock frequency signals to drive switches [11,12,13,14,15,16]. In particular, since the switching device itself is a major source of noise, research has focused on analyzing the noise generated by switching operations and on developing gate drivers to suppress such noise [14,15,16,17,18]. Additionally, some research groups have focused on optimizing the power delivery network (PDN). However, effective EMI control often requires careful consideration during the initial PCB layout and component selection stages [19,20]. Post-layout strategies, such as implementing shielding or increasing the spatial separation from noise sources, are generally less effective and tend to increase design complexity and cost. As a result, due to the complexity and relatively high cost of these conventional methods, it is essential to explore simplified analysis techniques and design approaches for EMI reduction.

One solution is to control the switching transition time. Although increasing the transition time of the MOSFET introduces additional switching losses, adjusting the transition time can enhance system robustness and reduce harmonic noise that may affect nearby systems. Therefore, since the transition time can be determined by the circuit model, theoretical analysis of the transition model of the MOSFET is significant for power electronics modules.

In this study, a practical technique to reduce EMI by modifying a single resistor value within an existing circuit topology is analyzed. The switching noise at the MOSFET gate is theoretically evaluated, and harmonic reduction by controlling the gate resistance is proposed. Theoretical analysis confirms that gate resistance (R_G) and the parasitic capacitances of the MOSFET are the primary parameters influencing the magnitude of harmonic components. This analysis can contribute to reducing radiated emissions with minimal impact on overall system design, providing a low-cost and compact solution for EMI control. Because the parasitic parameters are practically uncontrollable due to their physical structure and manufacturing process [21], this research mainly focuses on the effects of gate resistance. For this reason, the analysis is conducted at the MOSFET device level, considering parasitic capacitances and gate resistance which affect the turn-on and turn-off behavior of the MOSFET. In addition, to confirm the tendency of switching noise in practical applications, the switch in the power conversion system is designed. In order to validate in power conversion system, a low-side DC-DC buck converter is selected, as the low-side buck converter is widely used due to the advantages of the low-side topology explained in [22,23,24].

2. Theoretical Modeling Based on MOSFET Device

In order to investigate the effect of R_G on the harmonic components, switching noise modeling is performed under the device level of the MOSFET and a no-load condition to decrease the complexity of the analysis. In this work, the definitions of the symbols are listed in

Table 1. Definition of Symbols.

Symbols	Expressions
RG	Gate resistance
VG	Gate signal high level
VGS	Gate-source voltage
VGS,on	Gate-source voltage during turn-on state
VGS,off	Gate-source voltage during turn-off state
VGS,on,max	Maximum value of VGS,on
VDS	Drain-source voltage
Vth	Threshold voltage of MOSFET
CGS	Gate-source capacitance
CGD	Gate-drain capacitance
IG	Gate current
IGS	Gate-source current
IGD	Gate-drain current
ich	MOSFET channel current
fsw	MOSFET gate switching frequency
PLoss	Switching losses of MOSFETs
a0	Magnitude of DC component
an	Fourier coefficient of cosine term
bn	Fourier coefficient of sine term
cn	Magnitude of harmonic components
n	Harmonic order
T	MOSFET switching period
φ	Phase difference between sine and cosine terms
τ	Rising and falling times of VGS,on and VGS,off

.

An equivalent circuit for theoretical modeling is illustrated in Figure 1a. As illustrated, the drain of the MOSFET is shorted to ground to represent the no-load condition.

Here, the parasitic capacitance between the gate and source terminals, and the parasitic capacitance between the gate and drain terminals are denoted as C_GS and C_GD, respectively. In order to assume the operating condition of the MOSFET, a driving circuit consisting of V_G, R_G, and V_DS which represent the gate signal high level, gate resistance, and drain-source voltage, respectively, is considered. Also, in this research, the switching noise is focused on gate-source voltage (V_GS) that determines turn-on and -off states of the MOSFET. The turn-on and -off states are represented in Figure 1b and Figure 1c, respectively, with a modified equivalent circuit for simplicity. Specifically, Figure 1b shows that the I_G, driven by the V_G, is divided into I_GS and I_GD. When C_GS is charged by the current I_GS, the V_GS increases above the threshold voltage of the MOSFET (Vth), and the MOSFET turns on. On the other hand, as illustrated in Figure 1c, when the V_G becomes zero, the charge stored in C_GS and C_GD introduces I_GS and I_GD, discharging both capacitors. As a result, when the V_GS drops below Vth, the MOSFET turns off.

2.1. Transient Response of Gate-Source Voltage

To evaluate switching noise, Kirchhoff’s current law (KCL) is applied to the V_GS node. Additionally, the duration of the turn-on and -off states is assumed to be equal. Equation (1) represents the relationship between input and output currents at the V_GS node, and can be expressed in terms of the node voltages.

$$I_G\left(t\right)=I_{GS}\left(t\right)+I_{GD}\left(t\right)$$

(1)

Each current term can be represented as stated in the following equations.

$$I_G\left(t\right)={\displaystyle \frac{V_G-V_{GS}\left(t\right)}{R_G}}$$

(2)

$$I_{GS}\left(t\right)=C_{GS}{\displaystyle \frac{d{V}_{GS}\left(t\right)}{dt}}$$

(3)

$$I_{GD}\left(t\right)=C_{GD}{\displaystyle \frac{d\left(V_{GS}\left(t\right)-V_{DS}\right)}{dt}}$$

(4)

Assuming a constant V_DS, as the differential of V_DS becomes zero, I_GD(t) can be modified as in Equation (5).

$$I_{GD}\left(t\right)=C_{GD}{\displaystyle \frac{d\left(V_{GS}\left(t\right)-V_{DS}\right)}{dt}}=C_{GD}{\displaystyle \frac{d{V}_{GS}\left(t\right)}{dt}}$$

(5)

By utilizing Equations (2), (3) and (5), Equation (1) can be written as

$${\displaystyle \frac{V_G-V_{GS}\left(t\right)}{R_G}}=\left(C_{GS}+C_{GD}\right){\displaystyle \frac{d{V}_{GS}\left(t\right)}{dt}}.$$

(6)

The turn-on transient response can be obtained by solving the differential equation in Equation (6), which is given as

$$V_{GS,on}\left(t\right)=V_G\times \left(1-e^{{\displaystyle \frac{-t}{\left.{\left(R\right.}_G\times \left(C_{GS}+C_{GD}\right)\right)}}}\right).$$

(7)

By using Equation (7), the transient response of the MOSFET turn-on state can be obtained.

In the case of a turn-off state, as V_G is zero, the C_GS and C_GD begin to discharge, resulting in the V_GS becoming zero.

Considering Figure 1c, the I_GS(t) and I_GD(t) can be expressed as in Equation (8) to Equation (9).

$$I_{GS}\left(t\right)=C_{GS}{\displaystyle \frac{d(-V_{GS}\left(t\right))}{dt}}$$

(8)

$$I_{GD}\left(t\right)=C_{GD}{\displaystyle \frac{d\left(V_{DS}-V_{GS}\left(t\right)\right)}{dt}}$$

(9)

Due to the discharge of the parasitic capacitances during the turn-off state with a constant V_DS, Equation (9) is rewritten as

$$I_{GD}\left(t\right)=C_{GD}{\displaystyle \frac{d\left(V_{DS}-V_{GS}\left(t\right)\right)}{dt}}=C_{GD}{\displaystyle \frac{d(-V_{GS}\left(t\right))}{dt}}.$$

(10)

By applying a similar procedure to that in Equation (6) to the turn-off state, the following equation is derived as

$${\displaystyle \frac{V_{GS}\left(t\right)}{R_G}}=\left(C_{GS}+C_{GD}\right){\displaystyle \frac{d\left(-V_{GS}\left(t\right)\right)}{dt}}.$$

(11)

As a result, the turn-off transient response is formulated as

$$V_{GS,off}\left(t\right)=V_{GS,on,max}\times e^{{\displaystyle \frac{-t}{\left.{\left(R\right.}_G\times \left(C_{GS}+C_{GD}\right)\right)}}}.$$

(12)

Here, V_G in the turn-on state is substituted by V_GS,on,max since the turn-off state follows the turn-on state.

Based on Equations (7) and (12), it is revealed that transient responses are dominantly determined by R_G, C_GS, and C_GD. This means that appropriate values for R_G, C_GS, and C_GD are significant for operating the MOSFET under desirable transient conditions. However, considering that the parasitic capacitances (C_GS, C_GD) are difficult to control due to their dependence on the physical structure, the effect of R_G, which is more conveniently controllable, is analyzed.

In order to verify the theoretical analysis, circuit simulation results obtained by using OrCAD PSpice are compared with the transient responses. The simulation conditions correspond to Figure 1a, and the circuit parameters are listed in

Table 2. Circuit parameters of equivalent circuits.

	Case 1	Case 2	Case 3
RG	1 Ω	100 Ω	1 kΩ
VG	12 V	12 V	12 V
VDS	5 V	5 V	5 V
fsw	10 kHz	10 kHz	10 kHz
CGS	0.89 nF	0.89 nF	0.89 nF
CGD	0.45 nF	0.45 nF	0.45 nF

.

Because of uncontrollable parasitic elements, the comparison results for the variation in R_G are presented in Figure 2.

To clearly observe the effect of R_G, the values of R_G were chosen as 1 Ω, 100 Ω, and 1 kΩ, corresponding to cases 1, 2, and 3, respectively. As shown in Figure 2a–c, the rising time and falling time increase as R_G increases. Also, the similarity in the slope, which is depicted near the points of full turn-on and turn-off, supports Equations (7) and (12).

2.2. Frequency Component Calcaulted by Fourier Coefficient

Based on Equations (7) and (12), it is essential to identify the frequency components using Fourier series expansion derived as Equation (13). The magnitude of the frequency components in the transient responses is determined by the c_n which is calculated through a_n and b_n, as expressed in Equations (14)–(16). The a₀ represents the average of the transient response, while a_n and b_n are defined as the Fourier coefficients of the cosine and sine terms, respectively, with a period of T and a harmonic order of n. Here, the coefficients a_n and b_n are given by Equations (17) and (18) in terms of circuit parameters, with the gate signal high level V_G and rising and falling times (τ) defined in Equation (19). The theoretical analysis of harmonic components is demonstrated by the Fast Fourier Transform (FFT) result of the transient responses.

$$f\left(t\right)=a_0+{\displaystyle \sum }_{n=1}^{\infty }\left(a_n\times \mathit{cos}{\displaystyle \frac{2\pi n}{T}}t+b_n\times \mathit{sin}{\displaystyle \frac{2\pi n}{T}}t\right)=a_0+{\displaystyle \sum }_{n=1}^{\infty }\left(c_n\times cos\left({\displaystyle \frac{2\pi n}{T}}t-\phi \right)\right)$$

(13)

$$a_n={\displaystyle \frac{2}{T}}{{\displaystyle \int }}_0^{T}f\left(t\right)\mathit{cos}{\displaystyle \frac{2\pi n}{T}}tdt$$

(14)

$$b_n={\displaystyle \frac{2}{T}}{{\displaystyle \int }}_0^{T}f\left(t\right)\mathit{sin}{\displaystyle \frac{2\pi n}{T}}tdt$$

(15)

$$c_n=\sqrt{{a_n}^2+{b_n}^2}$$

(16)

$$a_n={\displaystyle \frac{-2V_{G}T\tau e^{\frac{-T}{2\tau }}\times \left(e^{\frac{-T}{2\tau }}\times \left(1+{\left(-1\right)}^n\right)+e^{\frac{T}{2\tau }}-e^{\frac{-T}{\tau }}-2\times {\left(-1\right)}^n\right)}{T^2+{\left(2\pi n\tau \right)}^2}}$$

(17)

$$b_n=2V_G\times \left({\displaystyle \frac{si{n}^2\left(\frac{\pi n}{2}\right)}{\pi n}}-{\displaystyle \frac{2\pi n{\tau }^2{e}^{\frac{-T}{2\tau }}\times \left(e^{\frac{-T}{2\tau }}\times \left(1+{\left(-1\right)}^n\right)+e^{\frac{T}{2\tau }}-e^{\frac{-T}{\tau }}-2\times {\left(-1\right)}^n\right)}{T^2+{\left(2\pi n\tau \right)}^2}}\right)$$

(18)

$$\mathsf{\tau }={\mathrm{R}}_{\mathrm{G}}\times \left(C_{GS}+C_{GD}\right)$$

(19)

The comparison was conducted under the same condition as the transient response with respect to R_G, and frequency components are depicted from the fundamental frequency (10 kHz) up to the 11th harmonic. The comparison results between the calculated frequency components using Fourier coefficients and the FFT of the transient simulation are illustrated in Figure 3.

As shown in Figure 3a–c, frequency components decrease as R_G increases and similarity between theoretical analysis and simulation results are observed. These results support that the Fourier coefficients are dominant in τ and that variations in τ determine harmonic components, as given in Equations (17) and (18). When focusing on the odd harmonic components, the calculation and simulation results correspond for R_G = 1 Ω and R_G = 100 Ω. However, for R_G = 1 kΩ, an error rate of less than 16% is observed. The error comes from the differences between the circuit model and the SPICE model, which incorporates a dynamic capacitance model. Specifically, the Miller plateau can be observed in the SPICE model, whereas it is not considered in the circuit model to reduce complexity [25].

2.3. Determination of R_G Considering Switching Loss

Though the increasing R_G reduces EMI-related harmonic components, which are generated by the harmonic components of V_GS which are mathematically derived and confirmed by simulation, it also leads to increased switching losses (P_Loss), which can be calculated as the integral of the product of the drain-source voltage and the channel current (i_ch) during the switching process, and are proportional to the switching frequency (f_sw), as described in Equation (20) [26,27].

$$P_{Loss}=f_{sw}·\int i_{ch}{V}_{DS}dt$$

(20)

In this research, regarding the transition time, the rising/falling time is denoted as τ, which is the product of R_G and C_GS + C_GD, and R_G is directly proportional to τ and, consequently, to the rising time. In practice, determining an exact R_G value is challenging because the parasitic capacitance of MOSFETs varies depending on the manufacturer. Therefore, it is advisable to refer to the datasheets given by manufacturers, which typically include experimental data. Although the optimal R_G value may vary depending on the characteristics of the MOSFET, it is generally selected to be below a few hundred ohms [28,29,30,31]. The focus of this research is the theoretical evaluation and observation of the harmonic reduction trend depending on different R_G values, ranging from 1 Ω to 1 kΩ in simulation and from 1 Ω to 300 Ω in experimentation.

3. Low-Side Buck Converter with R_G Control

In order to demonstrate the proposed idea, a buck converter is considered. In general, a buck converter composed of an auxiliary circuit such as a bootstrap, charge pump, or pulse transformer is necessary because the source voltage of the N-type MOSFET is floating from the ground. In this research, not only to avoid additional components but also to observe switching noise in V_GS with respect to the ground, the low-side buck converter topology is employed which utilizes an N-type MOSFET on the low side.

3.1. Configuration of the Low-Side Buck Converter

A circuit diagram for simulation is shown in Figure 4, and the IRF530N (Infineon) is selected for the MOSFET.

In order to consider practical characteristics, the internal SPICE model in PSpice is used for the IRF530N, with C_GS and C_GD corresponding to 0.89 nF and 0.45 nF, respectively. For the gate signal, a pulse voltage source with a trapezoidal waveform due to its rising and falling time was used. Regarding the capacitor, inductor and diode, ideal components from the PSpice library were utilized. The DC input voltage is restricted to 5 V to emphasize the effect of switching noise caused by V_GS. The gate resistance is set to 1 Ω, 100 Ω, and 1 kΩ, similar to the previous simulation at the device level of switch, and the detailed circuit parameters are shown in Figure 4. Additionally, simulations were conducted using a transient solver in the PSpice and the maximum time step was set to 10 ns to enable fine time resolution during the rising and falling transitions of the V_GS. In this case, the V_GS is monitored at the observation point using a voltage probe and the frequency components are extracted through the FFT function in the simulation.

3.2. Simulation Results

The observed transient responses of V_GS in the low-side buck converter are represented in Figure 5.

Consistent with results at the device level, the rising and falling times of V_GS increase as R_G increases, whereas they decrease as R_G decreases. In the case of an R_G equal to 1 kΩ, the V_GS remains at approximately 4 V for a certain duration, which is known as a Miller plateau [25]. This Miller plateau also extends both the rising and falling times.

In Figure 6, frequency components are confirmed from 10 kHz up to 300 kHz to investigate the effect of switching noise in a power conversion system.

Here, the dBV unit was utilized to facilitate the observation of fine frequency components. Although frequency components are irregular with an R_G value of 1 kΩ due to the Miller plateau, the magnitudes of harmonics follow a consistent trend that is similar to the device-level results. From the results, the magnitudes of the high-frequency harmonics were reduced, except for the even-order components, which are relatively negligible.

4. Experimental Validation

In order to verify harmonic reduction by increasing R_G, experiments with various R_G values were conducted. The switching noise in V_GS is measured under similar conditions as the simulation in a low-side buck converter.

4.1. Fabricated Low-Side Buck Converter and Measurement Setup

The fabricated low-side buck converter for measurement was built on a perfboard as shown in Figure 7.

The ATmega128 module, used as the microcontroller unit (MCU), is placed in the upper left corner to provide the gate signal through the R_G and the gate driver. For the gate driver, the IR2184 (Infineon) is used to boost a 5 V pulse to 12 V and is supplied by DC input 1. As in the simulation, the IRF530N is used as the MOSFET with its parasitic capacitance varying depending on the drain-source voltage and being given as a range in the datasheet, unlike the theoretical and simulation results [32]. Thus, the measured value of C_GS is in the range of 0.86–0.90 nF and C_GD is in the range of 0.30–0.45 nF. The DC input 2 and load resistance are connected to the DC input and the electronic load of the low-side buck converter, respectively.

The experimental setup is illustrated in Figure 8, consisting of power supplies, an oscilloscope (Keysight DSOX4024A) for waveform monitoring, measurement probes including a passive probe (Keysight N2894A), a differential probe (Keysight N2791A), and current probes (Keysight N2782B), and an electronic load (Kikusui PLZ1205W) functioning as a load resistor.

The DC output voltage is measured using the differential probe, while the DC input current and DC output current are measured using the current probes. In addition, the transient response of V_GS is measured by the passive probe, and frequency components are extracted through the internal FFT function in the oscilloscope. The load resistance is set to 2 Ω via the constant resistance function in the electronic load, and the rest of the detailed experimental parameters are represented in Figure 7. In order to ensure stable power delivery and minimize interference, three power supplies are employed in the experiment. The ATmega128, IR2184, and the DC input of the low-side buck converter are powered by power supplies 1, 2, and 3, respectively. Since a 1 kΩ gate resistance is rarely used for practical applications, the measurement is conducted with R_G values of 1 Ω, 10 Ω, and 300 Ω.

4.2. Expermental Results

The experimental results are also compared with the simulation results for various R_G. Figure 9 shows the measured V_GS on an oscilloscope. Since the MCU is designed to generate a 10 kHz switching frequency, it is observed consistently in all cases. Also, as discussed in Section 2 with Equation (19), as the R_G increases, the rising time and falling time increases. This phenomenon is also verified in the simulated results. Specifically, when the R_G varies from 1 Ω, to 10 Ω, to 300 Ω, the measured rising time changes from 18ns, to 71 ns, to 1.5 µs, respectively. The measured falling time is 17 ns, 74, ns and 1 µs as the R_G increases. These results correspond with the simulation results, which is attributed to the use of an identical component spice model.

While the rising time and falling time correspond to each other, ringing is observed in the experimental results. As illustrated in Figure 9a,b, ringing is more prevalent when the R_G is 1 Ω and 10 Ω compared to when the R_G is 300 Ω, as shown in Figure 9c. Specifically, when R_G is equal to 1 Ω, the overshoot reaches nearly 16 V, and the frequency of the ringing is approximately 370 kHz. These phenomena are due to the unexpected internal parasitic components in the fabricated low-side buck converter. Practically, a resistance that is used for a gate resistance also includes parasitic inductance and capacitance. Also, the input and output terminals have parasitic capacitance in practice, and even solder joints and wires connecting the electronic components introduce parasitic inductance. These parasitic components are inevitably present when fabricating the buck converter. However, the parasitic components on the board are beyond the scope of this research, as the focus was to confirm the reduction of harmonic components by varying the gate resistance. Thus, except for the effect of parasitic components, the relationship between the rising and falling times and switching noise in practical applications is validated.

Figure 10 represents the comparison of the magnitudes of frequency components, from fundamental frequency (10 kHz) up to the 11th harmonic (110 kHz). As expected from previous results, the magnitude of frequency components decreases as R_G increases, which follows the consistent trend. Specifically, the 5th harmonic decreased by approximately 0.2 dB at most, while the fundamental frequency component remained nearly constant despite the increase in R_G. The measurement and simulation errors in fundamental and harmonic components are due to the gate driver, IRS2184, which is designed to provide low-side and high-side gate signals simultaneously and includes an internal 500 ns dead time to prevent shoot-through [33]. The internal dead time leads to errors in the duty cycle of the pulse signal, which causes the duty to be slightly lower or higher than 50%, resulting in errors in odd and even harmonic components. For this reason, except for the effect of the gate driver, the switching noise in power conversion systems can be reduced by selecting an appropriate R_G.

Figure 11 illustrates the merged results from Figure 10a–c with a linear scale. In this figure, it can be noticeable that as the R_G increases, the absolute value of the harmonic component decreases, thereby improving EMI performance. This supports the theoretical analysis with experimental results.

5. Discussions

This paper covers the analytical analysis behavior of a MOSFET depending on RG. Though this research discusses only the effect of a single MOSFET, in practice, power conversion systems typically use multiple MOSFETs. The proposed RG selection and theoretical analysis contribute to reducing harmonic components, as each component’s amplitude is subject to superposition, thereby affecting the system-level harmonic distribution. The limitation of this article is that temperature and other environmental conditions are not considered. In practice, MOSFETs can exhibit different behaviors under varying temperatures and atmospheric pressures [34,35]. Therefore, a comprehensive analysis that accounts for temperature variations and other specific environmental conditions could be an important direction for future research to enhance the robustness and applicability of the proposed methodology.

6. Conclusions

In this paper, the control of gate-source voltage with respect to the variation of gate resistance is evaluated in order to reduce switching noise in the MOSFET.

To analyze the adjustment of the gate-source voltage, the equivalent circuit for MOSFET switching considering parasitic capacitances is used. The transient response is modeled from the equivalent circuit and the frequency components are derived by Fourier series expansion. The theoretical analysis is verified through simulations and measurements of the low-side buck converter, as well as simulations at the device level of the MOSFET. As theoretically explained, the experimental results confirm that the harmonic components in a power conversion system can be reduced by using an appropriate gate resistance. As a result, regardless of the topology, for modules that include MOSFETs, selecting an appropriate gate resistance can be an effective option to reduce harmonic EMI components.