Search Results (25)

This paper presents a low-noise analog front-end (AFE) integrated circuit (IC) circuit for capacitive micro-electromechanical system (MEMS) accelerometers that can be used for optical image stabilization (OIS) in various optical imaging systems. The AFE circuit design features a fully differential chopper stabilization technique that efficiently minimizes low-frequency 1/f noise and parasitic coupling. The AFE circuit chip is fabricated in a 0.18 $\mathsf{\mu }$m complementary metal-oxide-semiconductor (CMOS) technology and co-packaged with an x-axis capacitive MEMS accelerometer based on a silicon-on-glass (SOG) process. The SOG accelerometer has a footprint of 1000 $\mathsf{\mu }\mathrm{m}$ $\times$ 950 $\mathsf{\mu }\mathrm{m}$. The packaged system demonstrates a sensitivity of 342 mV/g and a nonlinearity of 1.1% between −1 g and +1 g, a dynamic range of 88 dB, and an equivalent noise floor of 14 $\mathsf{\mu }\mathrm{g}/\sqrt{\mathrm{H}\mathrm{z}}$. Full article

For the application of a high-performance shortwave infrared (SWIR) detector, a fully integrated analog front-end (AFE) circuit is proposed in this paper, which includes a readout integrated circuit (ROIC) and a 12-bit/100 kHz two-step single-slope analog-to-digital converter (TS-SS ADC). The ROIC adopts a direct injection (DI) structure with a pixel size of only 10 µm × 10 µm. The column processing circuit uses a passive correlated double-sampling (CDS) circuit to reduce noise and improve dynamic range. The comparator of four inputs in the ADC solves the problem of linearity reduction caused by charge redistribution during coarse quantization. In addition, the current steering digital-to-analog converter (DAC) is used to compensate for the non-ideal characteristics of the switch, which effectively optimizes the differential nonlinearity (DNL) and integral nonlinearity (INL). The AFE is implemented using SMIC 180 nm 1P6M technology. The post-simulation results show that at a power supply voltage of 3.3 V, the AFE has a frame rate of 100 Hz and a full well capacity (FWC) of 2.8 Me⁻. The linearity can reach 99.59%, and the equivalent output noise is 243 µV. The dynamic range is 73.8 dB. Meanwhile, the signal-to-noise distortion ratio (SNDR) and effective number of bits (ENOB) are 68.38 dB and 11.06 bits, respectively. Full article

A low-power, high-speed adder circuit topology based on current-starved inverters is presented to provide a basic arithmetic function for low-power, high-frequency signal processing systems. The adder is designed in 22 nm FDSOI (Fully-Depleted Silicon-on-Insulator) technology and is suitable for operation up to 5 GHz (Giga-Hertz). The proposed adder utilizes current-starved inverters to implement low-power operation while still maintaining signal integrity for high-frequency sine signals. The circuit uses a differential input and output structure to mitigate potential noise coupling onto any high-frequency signal pathways. The proposed solution differs from standard adder architectures by utilizing a fully analog signal processing design, accepting analog inputs while outputting an analog signal, and offering suitable functionality at Giga-Hertz level signals as compared to other relevant works. The simulated experimental results show the power consumption to be approximately 150 nW at 0.8 V supply with an input-referred noise of 6.091 nV/Hz at 5 GHz. Full article

This paper introduces a fully differential asynchronous successive approximation register analog-to-digital converter (SAR ADC) designed for biomedical signal processing. By extending the tracking time and utilizing fully differential inputs in the analog front-end circuit, the signal-to-noise ratio is enhanced in the system. Using an asynchronous clock can reduce power consumption across a wider range of sampling frequencies. In comparison to conventional architecture in high-speed SAR ADC, using an internal clock generator can operate at lower frequencies. A fully differential input can eliminate the DC offset of the analog front-end circuit and reduce the adverse effects of process variation, voltage variation, and temperature variation. The chip is implemented by TSMC 0.18 $\mathsf{\mu }$m complementary metal-oxide-semiconductor (CMOS) technology, and the chip area is 0.680 mm² (including ESD I/O PAD). At a 1.2 V supply, the maximum sampling rate is 10 Kilo Samples per second (KSps). The implemented ADC has an 11-bit resolution, while the input voltage range is 300∼900 mV. The total power consumption is 1.7 $\mathsf{\mu }$W, with the core power consumption at 932 nW. Full article

This article deals with the calibration method of analog integrated circuits (ICs) designed in CMOS nanotechnology. A brief analysis of various methods and techniques (e.g., fuse trimming, chopper stabilization, auto-zero technique, etc.) for calibration of a specific IC’s parameter is given, leading to motivation for this research that is focused on the digital calibration. Then, the principle and overall design of the calibration subcircuit, which was generally used to calibrate the input offset voltage $V_{IN\_OFF}$ of the operational amplifier (OPAMP). The essence of this work is verification of the proposed digital calibration algorithm for minimization the $V_{IN\_OFF}$ of a bulk-driven fully differential difference amplifier (FDDA) with the power supply voltage $V_{DD}$ = 0.4 V. Evaluation of ASIC prototyped chip samples with silicon-proved results has been done. This evaluation contains comparison of selected parameters and characteristics obtained from both simulations and measurements of non-calibrated and calibrated FDDA configurations. Full article

The wireless capture of analog differential signals from fully passive (battery-less) sensors is technically challenging but it can allow for the seamless capture of differential biosignals such as an electrocardiogram (ECG). This paper presents a novel design for the wireless capture of analog differential signals using a novel conjugate coil pair for a wireless resistive analog passive (WRAP) ECG sensor. Furthermore, we integrate this sensor with a new type of dry electrode, namely conductive polymer polypyrrole (PPy)-coated patterned vertical carbon nanotube (pvCNT) electrodes. The proposed circuit uses dual-gate depletion-mode MOSFETs to convert the differential biopotential signals to correlated drain-source resistance changes and the conjugate coil wirelessly transmits the differences of the two input signals. The circuit rejects (17.24 dB) common mode signals and passing only differential signals. We have integrated this novel design with our previously reported PPy-coated pvCNT dry ECG electrodes, fabricated on a stainless steel substrate with a diameter of 10 mm, which provided a zero-power (battery-less) ECG capture system for long duration monitoring. The scanner transmits an RF carrier signal at 8.37 MHz. The proposed ECG WRAP sensor uses only two complementary biopotential amplifier circuits, each of which has a single-depletion MOSFET. The amplitude-modulated RF signal is envelope-detected, filtered, amplified, and transmitted to a computer for signal processing. ECG signals are collected using this WRAP sensor and compared with a commercial counterpart. Due to the battery-less nature of the ECG WRAP sensor, it has the potential to be a body-worn electronic circuit patch with dry pvCNT electrodes that stably operate for a long period of time. Full article

This paper presents a practical implementation and measurement results of power-efficient chip performance optimization, utilizing low-cost indirect measurement methods to support self-X properties (self-calibration, self-healing, self-optimization, etc.) for in-field optimization of analog front-end sensory electronics with XFAB 0.35 µm complementary metal oxide semiconductor (CMOS) technology. The reconfigurable, fully differential indirect current-feedback instrumentation amplifier (CFIA) performance is intrinsically optimized by employing a single test sinusoidal signal stimulus and measuring the total harmonic distortion (THD) at the output. To enhance the optimization process, the experience replay particle swarm optimization (ERPSO) algorithm is utilized as an artificial intelligence (AI) agent, implemented at the hardware level, to optimize the performance characteristics of the CFIA. The ERPSO algorithm extends the selection producer capabilities of the classical PSO methodology by incorporating an experience replay buffer to mitigate the likelihood of being trapped in local optima. Furthermore, the CFIA circuit has been integrated with a simple power-monitoring module to assess the power consumption of the optimization solution, to achieve a power-efficient and reliable configuration. The optimized chip performance showed an approximate 34% increase in power efficiency while achieving a targeted THD value of −72 dB, utilizing a 1 Vp-p differential input signal with a frequency of 1 MHz, and consuming approximately 53 mW of power. Preliminary tests conducted on the fabricated chip, using the default configuration pattern extrapolated from post-layout simulations, revealed an unacceptable performance behavior of the CFIA. Nevertheless, the proposed in-field optimization successfully restored the circuit’s performance, resulting in a robust design that meets the performance achieved in the design phase. Full article

This paper presents a fully-differential touch screen panel (TSP) self-capacitance sensing (SCS) system with a self-capacitance mismatch calibration technique. Due to the self-capacitance mismatch of TSP, the analog front-end (AFE) of the receiver (RX) circuit suffers from dynamic range degradation and gain limitations, which lead to the signal-to-noise ratio (SNR) loss for the TSP SCS system. The proposed calibration introduces the difference in input resistance and the driving amplifier’s strength between the fully-differential input. Thus, the mismatch effect is efficiently relieved in terms of area and power consumption. The proposed calibration restores the SNR by $19.54$ dB even under the worst self-capacitance mismatch case. Full article

This paper presents a novel analog front-end for EMG sensor signal processing powered by 1 V. Such a low supply voltage requires specific design steps enabled using the 28 nm fully depleted silicon on insulator (FDSOI) technology from STMicroelectronics. An active ground circuit is implemented to keep the input common-mode voltage close to the analog ground and to minimize external interference. The amplifier circuit comprises an input instrumentation amplifier (INA) and a programmable-gain amplifier (PGA). Both are implemented in a fully differential topology. The actual performance of the circuit is analyzed using the corner and Monte Carlo analyses that comprise fifth-hundred samples for the global and local process variations. The proposed circuit achieves a high common-mode rejection ratio (CMRR) of 105.5 dB and a high input impedance of 11 G$\mathrm{\Omega }$ with a chip area of 0.09 mm${}^2$. Full article

The angular displacement sensor is a digital angular displacement measurement device that integrates optics, mechanics, and electronics. It has important applications in communication, servo control, aerospace, and other fields. Although conventional angular displacement sensors can achieve extremely high measurement accuracy and resolution, they cannot be integrated because complex signal processing circuitry is required at the photoelectric receiver, which limits their suitability for robotics and automotive applications. The design of a fully integrated line array angular displacement-sensing chip is presented for the first time using a combination of pseudo-random and incremental code channel designs. Based on the charge redistribution principle, a fully differential 12-bit, 1 MSPS sampling rate successive approximation analog-to-digital converter (SAR ADC) is designed for quantization and subdivision of the incremental code channel output signal. The design is verified with a 0.35 μm CMOS process and the area of the overall system is 3.5 × 1.8 mm². The fully integrated design of the detector array and readout circuit is realized for the angular displacement sensing. Full article

Inverter-based Operational Transconductance Amplifiers (OTAs) are versatile and friendly scalable analog circuit blocks. Especially for the new CMOS technological nodes, several recent applications have been extensively using them, ranging from Analog Front End (AFE) to analog-to-digital converters (ADC). This work tracks down the current advances in inverter-based OTAs design, comparing their basic fully differential structures, such as Nauta (N), Barthelemy (B), Vieru (V) and Mafredini (M) ones, and, in addition, mixing them up to propose new fully differential single-ended and two-stage hybrid versions. The new herein-proposed fully differential hybrid OTAs are the composition of Barthelemy/Nauta (B/N), Barthelemy/Manfredini (B/M), Nauta/Vieru (N/V), and Manfredini/Vieru (M/V) OTAs. All OTAs were designed using the same Global Foundries 180 nm open-source PDK and their performances are compared for post-layout simulations. Full article

Analog integrated circuit sizing is notoriously difficult to automate due to its complexity and scale; thus, it continues to heavily rely on human expert knowledge. This work presents a machine learning-based design automation methodology comprising pre-defined building blocks such as current mirrors or differential pairs and pre-computed look-up tables for electrical characteristics of primitive devices. Modeling the behavior of primitive devices around the operating point with neural networks combines the speed of equation-based methods with the accuracy of simulation-based approaches and, thereby, brings quality of life improvements for analog circuit designers using the $g_{\mathrm{m}}/I_{\mathrm{d}}$ method. Extending this procedural automation method for human design experts, we present a fully autonomous sizing approach. Related work shows that the convergence properties of conventional optimization approaches improve significantly when acting in the electrical domain instead of the geometrical domain. We, therefore, formulate the circuit sizing task as a sequential decision-making problem in the alternative electrical design space. Our automation approach is based entirely on reinforcement learning, whereby abstract agents learn efficient design space navigation through interaction and without expert guidance. These agents’ learning behavior and performance are evaluated on circuits of varying complexity and different technologies, showing both the feasibility and portability of the work presented here. Full article

The application requirements of high frame rate CMOS image sensors (CIS) in the industry have not been satisfied due to the speed limitations in traditional single-slope and serial two-step analog-to-digital converters (ADCs). In this paper, a high-speed fully differential two-step ADC design method for CIS was proposed. The proposed method was based on differential ramp and time-to-digital conversion (TDC) technology. A parallel conversion mode was formed that is different from serial conversion, and the robustness of the system was ensured due to the existence of differential ramps. Aiming at the inconsistency between traditional TDC technology and single-slope ADC, a TDC technology based on level coding was proposed. The proposed technology achieves the TDC in the last clock cycle of analog-to-digital conversion, and realized a two-step conversion process at another level. This paper presents a complete circuit design, layout design, and test verification of the proposed design method based on the 55 nm 1P4M CMOS experimental platform. Under the design environment of the analog voltage of 3.3 V, the digital voltage of 1.2 V, the clock frequency of 100 MHz, and a dynamic input range of 1.6 V, this design was a 12-bit ADC with a conversion time of 480 ns, column-level power consumption of 62 μW, differential nonlinearity (DNL) of +0.6/−0.6 LSB, and integral nonlinearity (INL) of +1.2/−1.4 LSB. Furthermore, it achieved a signal-to-noise distortion ratio (SNDR) of 70.08 dB. The proposed design provided a large area array with a high frame rate, and compared with the existing advanced single-slope ADC, its conversion speed increased by more than 52%. It provides an effective solution for the implementation of high frame frequency CIS Full article

Brownian motion is a dynamic behavior with random changes over time (stochastic) that occurs in many vital functions related to fluid environments, stock behavior, or even renewable energy generation. In this paper, we present a circuit implementation that reproduces Brownian motion based on a fully deterministic set of differential equations. The dynamics of the electronic circuit are characterized using four well-known metrics of Brownian motion, namely: (i) Detrended Fluctuation Analysis (DFA), (ii) power law in the power spectrum, (iii) normal probability distribution, and (iv) Mean Square Displacement (MSD); where traditional Brownian motion exhibits linear time growth of the MSD, a Gaussian distribution, a $-2$ power law of the frequency spectrum, and DFA values close to $1.5$. The obtained results show that for a certain combination of values in the deterministic model, the dynamics in the electronic circuit are consistent with the expectations for a stochastic Brownian behavior. The presented electronic circuit improves the study of Brownian behavior by eliminating the stochastic component, allowing reproducibility of the results through fully deterministic equations, and enabling the generation of physical signals (analog electronic signals) with Brownian-like properties with potential applications in fields such as medicine, economics, genetics, and communications, to name a few. Full article

It is well known that fully differential signal processing is more advantageous than single-ended signal processing in a noisy environment, and is widely used in audio, video and other signal processing applications. This paper introduces a new fully differential configuration that contains a first-order low-pass (LP) filter, high-pass (HP) filter, and all-pass (AP) filter, all present within the same circuit design. The proposed fully differential configuration is simple and employs only one multiple-output current differencing transconductance amplifier and one grounded capacitor. The circuit has a wide operating frequency range (up to 73 MHz). The additional features offered by the proposed circuit include use of the lowest number of active and passive components, suitability of the integrated circuit chip, support of cascadability, electronic tunability, no passive component-matching restrictions, availability of all first-order responses, i.e., LP, HP, and AP, and low-level operating supply voltages. Non-ideal and parasitic analyses are investigated for the proposed circuit, and PSPICE simulation results are presented to verify the proposed theory. Additionally, the proposed fully differential LP filter circuit is experimentally verified using off-the-shelf ICs. Moreover, the cascading feasibility is demonstrated by realizing a fully differential nth-order LP filter. Full article