A 68dB-SNDR, 100-Frame/s CMOS Analog Front-End for a SWIR Detector

Abstract

For the application of a high-performance shortwave infrared (SWIR) detector, a fully integrated analog front-end (AFE) circuit is proposed in this paper, which includes a readout integrated circuit (ROIC) and a 12-bit/100 kHz two-step single-slope analog-to-digital converter (TS-SS ADC). The ROIC adopts a direct injection (DI) structure with a pixel size of only 10 µm × 10 µm. The column processing circuit uses a passive correlated double-sampling (CDS) circuit to reduce noise and improve dynamic range. The comparator of four inputs in the ADC solves the problem of linearity reduction caused by charge redistribution during coarse quantization. In addition, the current steering digital-to-analog converter (DAC) is used to compensate for the non-ideal characteristics of the switch, which effectively optimizes the differential nonlinearity (DNL) and integral nonlinearity (INL). The AFE is implemented using SMIC 180 nm 1P6M technology. The post-simulation results show that at a power supply voltage of 3.3 V, the AFE has a frame rate of 100 Hz and a full well capacity (FWC) of 2.8 Me⁻. The linearity can reach 99.59%, and the equivalent output noise is 243 µV. The dynamic range is 73.8 dB. Meanwhile, the signal-to-noise distortion ratio (SNDR) and effective number of bits (ENOB) are 68.38 dB and 11.06 bits, respectively.

1. Introduction

With the rapid development of the information society, shortwave infrared (SWIR) imaging technology is widely used in military reconnaissance, environmental monitoring, medical diagnosis, remote sensing detection, and other fields. As the core component of the imaging system, the performance of the SWIR detector directly determines the quality of images, detection sensitivity, and response speed of the system. The SWIR detector mainly consists of three parts: the SWIR detector array, the analog front-end (AFE) circuit, and the digital signal processing module. The AFE includes a readout integrated circuit (ROIC) and an analog-to-digital converter (ADC). The ROIC converts the photocurrent generated by the SWIR sensor into a voltage signal, which is then converted into a digital signal by the ADC. The digital signal processing circuit further optimizes and processes the output digital code of the ADC to achieve imaging.

At present, research on ROICs mainly focuses on pixel circuits and column-level circuits. High-performance ROICs require pixel circuits to have strong charge processing capabilities, low noise, and stability [1]. N. Singh et al. used Gate Modulation Input (GMI) as an input stage to increase the gate area of the mirror current source to reduce flicker noise, but it increased area and power consumption [2]. T. P. Sun et al. proposed a dual-mode ROIC that includes both DI and buffered direct injection (BDI) structures. Four pixels share an ROIC for signals of different frequency bands [3]. The BDI is used for long-wave signals, while the DI is used for medium-wave signals. The disadvantage is that the structure is relatively complex, the noise is high, and the area of each pixel is limited. H. Kulah et al. proposed the current mirroring integration (CMI) structures with a pixel array of 16 × 16 [4]. And the pixel size is 20 μm × 25 μm. Under a 5 V power supply, the output swing is close to VDD. The photocurrent is mirrored to the integrating capacitor branch through a wide swing current mirror, and the detector bias is close to 0 V, so the dark current is very small. In order to reduce the area, the integral capacitor is not included in the pixel circuit. The output of the pixel circuit can be integrated from ground to the power supply voltage. The disadvantage is that there may be transistor mismatch during manufacture, so there may be a deviation in the accuracy of photocurrent replication. And when the photocurrent is small, the current mirror operates in the subthreshold region, deteriorating the performance. In addition, there is a positive feedback loop in the circuit, and circuit oscillation should be avoided during the design process. Manik et al. designed a pixel circuit that combines source follower structure and CMI structure, which improved noise performance, reduced power consumption, but increased circuit complexity [5]. To improve the overall performance of SWIR imaging systems, it is necessary to simultaneously enhance the sensor and circuit performance. Many scholars have proposed various design ideas for high-speed and high-linearity circuits, which provide valuable scientific inspiration for subsequent research. However, most optimization schemes have limited effectiveness, especially in the application of ultra-large arrays, which require focus on performance such as linearity and frame rate.

The ADC in the AFE of SWIR detectors generally uses the single-slope (SS) ADC architecture, which has the smallest area and simplest structure. Park et al. proposed a 10-bit/100 MHz column SS ADC based on a time extension circuit [6]; Ma et al. designed a 12-bit SS ADC with different clocks for the high 6 bits and low 6 bits to reduce power consumption [7]. Tang et al. presented a 12-bit two-step SS (TS-SS) ADC with a clock frequency of 62.5 MHz [8]. Lyu T et al. proposed a low-noise two-step ADC with a pixel size of 15 μm, which can be applied to a 1024 × 32 pixel array. Its effective resolution is 12 bits, conversion time is 36 μs, and the frame rate is 15.5 Hz at a clock frequency of 20 MHz [9]. Zhang H et al. designed a 12-bit two-step SAR/SS ADC, with the first stage being a SAR ADC and the second stage being a single-slope ADC. In the layout design, the capacitor array of the DAC is located on the left side of the comparator, and the ramp generator input of the SS ADC is located on the right side of the comparator. This scheme reduces the impact of capacitor array mismatch. Its conversion speed is 300 ks/s [10]. In summary, SS ADC is the mainstream structure used in SWIR AFEs, which is limited by performance parameters such as area, accuracy, speed, and power consumption.

This paper focuses on the application of the SWIR detector and designs a high-performance AFE circuit. The pixel adopts a DI structure, with a size of 10 μm × 10 μm. The ROIC uses the Integrated Then Read (ITR) mode. The integration capacitor and the holding capacitor are shared, which increases FWC within a limited pixel area and improves the dynamic range. The column-level circuit consists of a column-correlated double-sampling (CDS) circuit, column buffer, and switch array. The ADC is a 12-bit/100 kHz two-step single-slope (TS-SS) converter. The overall AFE adopts four-channel outputs, with a frame rate of 100 Hz, detectable current range of 7 nA–100 nA, and SNDR of 68 dB. At the circuit level, we emphasize the following practical choices: a redundant 7-bit (2ΔV) fine window in the TS-SS path to avoid boundary dead zones while keeping a single global ramp; a passive column CDS sized and timed for SWIR conditions; a four-input comparator with extended input common-mode range to directly accept the ROIC swing; and a current-steering ramp DAC used to counter code-dependent switch injection and static element mismatch.

2. Circuit Design

The schematic diagram of the carbon-based infrared detector is shown in Figure 1. Similar to a conventional MOSFET, it is also a four-terminal device comprising a top gate, bottom gate, source, and drain. The detector consists of a heterojunction formed by carbon nanotubes and PbS colloidal quantum dots (CQDs). The PbS CQD thin film on the top gate effectively absorbs infrared light and generates electron–hole pairs. A photovoltage is produced at the PN heterojunction of the PbS CQDs/ZnO thin film, and this photovoltage (Voc) modulates the gate of Carbon Nanotube Field-Effect Transistor (CNTFET), enabling further amplification of the optical signal and resulting in a high-gain photocurrent. The drain terminal of the carbon-based sensor is connected to the current input of the AFE, which processes the photocurrent. The pixel is modeled as an equivalent current source.

2.1. ROIC Design

The AFE is a mixed-signal circuit mainly composed of ROIC and TS-SS ADC. The ROIC includes a 64 × 64 pixel array, a column-level circuit, an output buffer, and a bias circuit. The TS-SS ADC comprises a sampling and hold circuit, comparator, latch, ramp generator, and digital circuits. The overall structure is shown in Figure 2. The analog signal chain needs to ensure adequate linearity and output dynamic range. The digital circuit provides timing control to achieve coordinated operation of the AFE.

In a global shutter, since all pixels are exposed at the same time, the integrated voltage needs to be held on the holding capacitor after exposure is completed. In the readout stage, due to the fact that pixels with lower readout order need to maintain the integrated voltage for a long period of time, there may be a leakage problem with the holding capacitor during the readout stage, which results in a deviation of the integrated voltage. In order to mitigate this impact, a rolling shutter and array partitioning technology are adopted to shorten the holding time from 10 ms per frame to 320 µs, greatly reducing the impact of leakage. Therefore, we divide a 64 × 64 array into four 32 × 32 sub-arrays.

The timing diagram of the ROIC is illustrated in Figure 3. The input signals include the clock (CLK) and the global reset (RST_N), while the output signals comprise the cell reset (CELL-RST), integration (INT), row selection (ROW<0:31>), and column selection (COL<0:31>) signals.

As shown, the values of ΔT1, ΔT2, ΔT4, and ΔT5 are consistent, with each representing a non-overlapping period of one clock cycle. ΔT3 denotes the integration time, and ΔT6 corresponds to the row readout time. Within each row’s readout time (ΔT6), all columns are read out sequentially.

The operational sequence for each pixel row involves reset, integration, and readout, with the reset-integration time interval separating consecutive rows. The process begins when RST_N is asserted low, which pulls INT low and sets all other output signals high. During the reset phase, CELL-RST is pulled low one clock cycle after RST_N returns high to reset the row. Following another clock cycle, INT goes high, initiating the integration operation. Upon completion of integration, CELL-RST is pulled high after one clock cycle to prevent premature signal reset before readout. The readout stage commences one clock cycle later: CELL-RST remains high as row selection signals ROW<0:31> are enabled sequentially, each lasting for 320μs. During each row selection period, column selection signals COL<0:31> are activated in sequence, with each lasting for 10μs to complete data readout.

Pixel circuits need to compromise performance parameters such as injection efficiency, layout area, and noise. In this paper, a DI structure is chosen as the pixel circuit for the ROIC. DI can be applied in a small pixel while ensuring high linearity and dynamic range. Its basic structure is shown in Figure 4. Its operation principle is as follows: when transistor M2 is turned off and M3 is turned on, integration begins. After integration is complete, M2 is turned on and M3 is turned off, providing a circuit for photocurrent to prevent charge accumulation from causing changes in the switch state. M4, M5, and M6 form a dynamic power source follower, which isolates the pixel from the column bus and prevents interference on the column bus from affecting the integration voltage. Among them, M4 is the amplification transistor and M5 is the switch transistor. During the readout phase, when the row selection signal COL_SEL (Vrow) is active, M5 conducts and the source follower transmits the integrated voltage to the source of M5, while also conducting M2 to discharge the photocurrent from M2 to the ground. This scheme avoids any impact on surrounding cells. During the integration process, M5 is disconnected, and the pixel output is reset to VDD.

Given the relatively small current range of 7 nA to 100 nA, the injection transistor can be appropriately biased in the subthreshold region. When M1 operates in the subthreshold region, its current is related to the gate-source voltage as follows:

$$I_{ds}={\mu }_p{\displaystyle \frac{W}{L}}{C}_{ox}{({\displaystyle \frac{kT}{q}})}^2\exp [{\displaystyle \frac{q(V_{gs}-V_{th})}{nkT}}]$$

(1)

From the above equation, it can be seen that the leakage current is independent of the drain-source voltage. The drain-source voltage of the injection transistor should be greater than 0.1 V to ensure stability of the detector. Cint is an integration capacitor. For the selected process in this paper, the unit area capacitance value of the MOS capacitor is 4.97 fF/μm², while the unit area capacitance value of the MIM capacitor is 2 fF/μm². Therefore, the MOS capacitor is more suitable for the design. Considering all factors, the PMOS capacitor is adopted. MOS devices used as capacitors need to consider their operating regions, namely the inversion region and the accumulation region. When operating in the inversion region, the MOS capacitance is unstable, and this region should be avoided during pixel integration to avoid serious nonlinear errors.

Due to the manufacturing mismatches, there will be a certain deviation in the threshold voltage of each MOS transistor, which can cause output deviation under the same input or in the absence of light, and this deviation is defined as fixed pattern noise (FPN) [11]. The impact of this noise on the overall performance is significant, and it is also the largest contributing factor to noise in ROIC. It can be reduced through correlated double-sampling (CDS) techniques [12]. A passive CDS circuit is used as shown in Figure 5. Buffer1 is the source follower in the DI structure. The left plate of C_CDS samples the reset voltage V_RST when the Φ_CDS is active and M1 is on, and the voltage on the right plate of C_CDS is V_CDS. At this time, the charge on the capacitor can be expressed as

$$Q_1=C_{CDS}(V_{RST}-V_{CDS})$$

(2)

After the pixel integration is completed, the Φ_CDS becomes invalid, the switch S1 is turned off, and the left plate of C_CDS samples V_pixel. At this time, the charge on C_CDS is

$$Q_2=C_{CDS}(V_{pixel}-V_{CDS})$$

(3)

The following can be obtained from the conservation of charge:

$$V_{OUT}=V_{pixel}-V_{RST}+V_{CDS}$$

(4)

V_pixel and V_RST are the pixel integration voltage and reset voltage, respectively. This circuit uses only one capacitor to achieve the function of correlated double-sampling, which is suitable for column-level readout circuits and can also be designed inside the pixel if the area allows [13].

The passive CDS is dimensioned. Meanwhile, its clamp-to-sample timing is chosen to suppress reset/FPN and low-frequency components while keeping the column chain compact.

Figure 5. Passive CDS circuit.

Figure 5. Passive CDS circuit.

Although this circuit has the advantages of a small area and low power consumption, C_CDS will redistribute charges with the junction capacitor of M1 and the input capacitor of Buffer2. Therefore, C_CDS must be large enough; otherwise, the parasitic capacitor will seriously affect the output swing.

2.2. 12 Bit/100 kHz TS-SS ADC

Figure 6 shows the structure of the TS-SS ADC, which mainly includes a sampling and hold circuit, a comparator, a coarse ramp generator, a fine ramp generator, a current-steering DAC, and a digital module. The storage capacitor C_H is not connected across the coarse ramp generator and the fine ramp generator, but is directly connected to the ground.

The quantization of ADC is accomplished based on the counter. The ramp generator generates a voltage reference for the comparator according to the output of the counter. Therefore, the performance of the counter also affects the establishment time of the ramp signal, etc. According to the different clock control methods, counters can be classified into synchronous and asynchronous counters. In an asynchronous counter, the delay time of each flip-flop is Td, meaning that the delay time of the last flip-flop is nTd. In a synchronous counter, each trigger is controlled by the master clock, so its delay time is Td. To achieve the minimum delay time, the synchronous counter is adopted in this paper.

The ramp generator adopts a voltage divider structure. The output of the counter cannot be directly applied to the on–off switch and needs to be decoded by a decoder. The binary code counting method is adopted. For a 6-bit decoder, when the value of the counter is 000000, only switch S0 is on. When the value of the counter is 000001, only switch S1 is on, and so on.

Since the design of the decoder does not require very high driving capacity, this paper adopts a 6-input NAND to save area and reduce power consumption.

In the sampling phase, the switch S_C is closed, and the sampling and hold circuit samples the output voltage of the ROIC, and the voltage is sampled to the inverting input terminal of the four-input comparator. The switch S_H is turned on, and V_ref inputs to one positive and one negative input terminal. Therefore, the input of the comparator can be expressed as

$$V_{in}=V_{Ramp\_c}-V_S$$

(5)

V_S is the common-mode voltage output by the sampling and hold circuit, which is the lowest level of the coarse ramp generator.

In the coarse quantization stage, S_C and S_F remain closed, and counting begins after the coarse quantization counter is reset. The voltage of each step in the coarse ramp generator is V_C[i], and the input of the comparator at this time is

$$V_{in}=V_C[i]-V_S$$

(6)

When ΔV_in > 0, the output of the comparator flips, and the latch uses an edge-triggered structure. The rising edge of the comparator triggers the operation of the latch, and the value of the counter is latched as the result of coarse quantization. Switch S_C is disconnected, and the voltage on the storage capacitor is

$$V_{CH}=(m+1)\Delta V$$

(7)

ΔV is the voltage of each step of the resistor array.

In the fine quantization stage, the edges of the quantization interval may cause errors in comparator results, resulting in a quantization dead zone. Therefore, the accuracy of the fine ramp generator is 7 bits instead of 6 bits, and its quantization range is 2ΔV. The lowest and highest voltage of the ramp are

$$V_L=(-{\displaystyle \frac{3}{2}}\Delta V)+V_{ref}$$

(8)

$$V_H={\displaystyle \frac{1}{2}}\Delta V+V_{ref}$$

(9)

The counter undergoes a reset process to ensure that the initial voltage of the fine ramp generator is V_L. After the reset is complete, the 7-bit fine quantization counter starts counting, causing the ramp voltage to rise accordingly. Switch S_H is turned off, and S_F is turned on. Then the count value i controls the decoder. The output of the decoder controls the switching of the resistor array to generate a fine ramp voltage. At this time, the differential input of the comparator is

$$V_{in}=(m+1)\Delta V-V_S+V_{Ramp\_F}[i]-V_{ref}$$

(10)

And the output voltage of the fine ramp generator is

$$V_{Ramp\_F}[i]=(-{\displaystyle \frac{3}{2}})\Delta V+V_{ref}+i·\Delta V$$

(11)

Equation (10) can be simplified as

$$V_{in}=m\Delta V-{\displaystyle \frac{1}{2}}\Delta V+i·\Delta V-V_S$$

(12)

As the value of the counter increases, the input of the comparator gradually increases. When V_in > 0, the comparator flips to high, and the latch also uses an edge-triggered structure. The rising edge of the comparator triggers the latch to operate, and the value of the counter is latched as the result of fine quantization. The results of fine and coarse quantization are added to obtain D[0:11]. Due to the addition of a quantization redundancy bit in the fine quantization stage to prevent dead zones, the output code will be 32 more than the ideal value. Therefore, it is necessary to subtract D[0:11] from 000000 100,000 to obtain the correct result Dout [11:0]. At this point, the 12-bit TS-SS ADC quantization is completed.

The 7-bit (2ΔV) fine ramp acts as a redundancy window around the coarse–fine boundary, eliminating dead zones and relaxing comparator settling; connecting C_H to ground avoids cross-domain charge sharing between the coarse and fine ramps.

The dynamic comparator is shown in Figure 7, consisting of a dynamic latch, two-stage preamplifiers, and an output buffer.

Under the selected process, the threshold voltage of MOS is about 0.75 V (power supply voltage is 3.3 V), and the maximum common-mode input signal can only reach 2.55 V, while the maximum output voltage of ROIC is 3 V. In order to meet the requirements of the input swing, the first preamplifier adopts a folded structure. Due to its input-stage topology, the folded amplifier can effectively expand the input common-mode range, making it more advantageous than ordinary operational amplifiers, especially in low-voltage and high-performance designs. At the same time, the input differential transistor is divided into two pairs, and the common mode range can reach 2.55 V. The cascode current mirror improves the common-mode rejection ratio and enhances the stability of the tail current, as shown in Figure 8. The structure of the second preamplifier is similar to that of the first stage, except it uses a fully differential structure with two inputs.

The schematic of the comparator is shown in Figure 9. Compared to the Strong-Arm comparator, the proposed comparator features lower input kickback noise and power consumption.

When CLK is low, the dynamic latch is in the reset phase. M8 and M9 are turned on, and both VOUTP and VOUTN are reset to VDD. M1 is turned off, so there is no current path from VDD to ground. Energy consumption during this process occurs only when VDD charges the output capacitance.

When CLK is high, the dynamic comparator enters the comparison phase. M8 and M9 are turned off. The input voltages VIN and VIP determine the current flowing through M2 and M3. When VIN > VIP, the current of M2 is greater than that of M3, which means the source potential of M4 drops faster than that of M5. The voltage difference between them is amplified by the positive feedback of the latch. Finally, VOUTP is pulled to VDD and VOUTN is pulled to GND, completing the comparison. When VIN < VIP, the current of M2 is less than that of M3. The voltage difference at their source terminals is amplified by the positive feedback of the latch. Finally, VOUTP becomes GND and VOUTN becomes VDD.

From the above analysis, it can be seen that the gain of the dynamic latch varies with time. The expression is as follows:

$$A_V(\mathrm{t})=e^{{\displaystyle \frac{t}{\tau }}}$$

(13)

The expression for the time constant τ is

$$\tau ={\displaystyle \frac{1}{g_m}}{C}_L$$

(14)

where g_m is the transconductance of the inverter, and C_L is the load of the dynamic latch. The 12-bit ADC requires the comparison accuracy to reach LSB/2, and the delay time is half of the clock cycle, T/2. Therefore, we have the following:

$$A_V({\displaystyle \frac{T}{2}})=e^{{\displaystyle \frac{T}{2\tau }}}\ge {\displaystyle \frac{2VDD}{LSB}}={\displaystyle \frac{2VDD}{2^{12}}}$$

(15)

Thus, we obtain the transconductance of the inverter:

$$g_m\ge {\displaystyle \frac{T{C}_L}{2\ln \frac{2VDD}{2^{12}}}}$$

(16)

The structure of the ramp generator is shown in Figure 10, which mainly includes two clamp op-amps, a resistor array, a counter, a decoder, and an output buffer. The top clamp op-amp (AMP TOP) clamps the top potential of the resistor array to 3 V through negative feedback, and the bottom clamp op-amp (AMP BOTTOM) clamps the bottom potential of the resistor array to 1.3 V through negative feedback. The output of the counter controls the decoder, and each bit of the decoder effectively outputs the voltage of the resistor array in sequence. The output buffer is designed to enhance the driving capability by isolating the ramp generator from the next circuit.

The top clamp op-amp of the ramp generator is a two-stage op-amp. The first stage uses a folded cascode amplifier with NMOS input due to the high common-mode level. The second stage uses a Class AB output stage, as shown in Figure 11. Correspondingly, due to the low common-mode level of the bottom clamp op-amp input, its first stage is a folded-cascode amplifier with PMOS input.

At the end of coarse quantization, the charges in the channel will flow into C_H due to the influence of charge injection, resulting in deviation during the fine quantization process and affecting the quantization accuracy. A current-steering digital-to-analog converter (DAC) is used to correct this deviation. The amount of charge injected into capacitor C_H by switch S_C is

$$Q=\delta (WL)S_C{C}_{ox}(V_{gs}-V_{th})=\delta (WL)S_C{C}_{ox}[VDD-(m+1)\Delta V-V_{th}]$$

(17)

δ is the charge injection coefficient; therefore, the voltage change caused by Q on C_H is

$$\Delta V_{CH}={\displaystyle \frac{\delta (WL)S_C{C}_{ox}[VDD-(m+1)\Delta V-V_{th}]}{C_H}}$$

(18)

It can be seen that ΔV_CH is related to m, and the derivative of m can be obtained

$${\displaystyle \frac{\partial \Delta V_{CH}}{\partial m}}={\displaystyle \frac{\delta (WL)S_C{C}_{ox}(-\Delta V)}{C_H}}$$

(19)

According to Equation (17), the variation of ΔV_CH is a linear relationship that can be eliminated by DAC. After considering the error caused by S_C, Equation (10) becomes

$$V_{in}=(m+1)\Delta V+\Delta V_{CH}(m)-V_S-{\displaystyle \frac{3}{2}}\Delta V+V_{ref}+i·\Delta V-V_{DAC}(m)$$

(20)

V_DAC(m) is the output of DAC, and its voltage value can be designed to be equal to V_ref + ΔV_CH to eliminate the influence of charge injection. Due to the low performance requirements of the calibrated DAC, a current-steering DAC can meet the system requirements, as shown in Figure 12.

During ramp operation, the current-steering path is used to compensate code-dependent switch injection and static element mismatch, stabilizing the INL/DNL presented to the TS-SS conversion.

The current-steering DAC consists of a two-stage operational amplifier. The MOSFETs at the non-inverting input are composed of M1 to M7, while the MOSFETs at the inverting input are composed of M10 to M16. The sizes of M1 to M6 and M10 to M15 increase in binary-weighted proportions. When the operational amplifier is configured in a unity-gain feedback structure, the analog output voltage can be adjusted by controlling switches S1 to S6. Its output is as follows:

$$V_{OUT}=V_L+{\displaystyle \frac{D}{2^N}}(V_H-V_L)$$

(21)

V_L is the lowest output voltage, V_H is the highest output voltage, N is the number of bits in the DAC, and D is the decimal value corresponding to the input binary code. By combining Equations (20) and (21), it can be concluded that it is difficult to eliminate the error caused by the charge injection of switch Sc using a single DAC. Therefore, this paper employs three identical DACs connected in series to mitigate the effects of charge injection as shown in Figure 13. The outputs of DAC_1 and DAC_2 are connected to the V_H and V_L inputs of DAC_3, respectively, while the input of DAC_3 is driven by the value of the coarse quantization counter.

The output of DAC_1 is

$$V_{OUT1}=(V_{ref}-{\displaystyle \frac{1}{2}}\Delta V)+{\displaystyle \frac{D_{TOP}}{2^6}}(V_H-V_L)[V_{ref}+{\displaystyle \frac{1}{2}}\Delta V-(V_{ref}-{\displaystyle \frac{1}{2}}\Delta V)]$$

(22)

D_TOP is the input digital code of DAC_1, and Equation (22) can be simplified as

$$V_{OUT1}=(V_{ref}-{\displaystyle \frac{1}{2}}\Delta V)+{\displaystyle \frac{D_{TOP}}{2^6}}\Delta V$$

(23)

Similarly, the output of DAC_2 is

$$V_{OUT2}=(V_{ref}-{\displaystyle \frac{1}{2}}\Delta V)+{\displaystyle \frac{D_{BOTTOM}}{2^6}}\Delta V$$

(24)

Therefore, the total output V_OUT can be expressed as

$$V_{OUT}=V_{ref}+\Delta V[{\displaystyle \frac{D_{TOP}}{2^6}}-{\displaystyle \frac{1}{2}}+{\displaystyle \frac{D_{SIN\_C}}{2^{12}}}(D_{TOP}-D_{BOTTOM})]$$

(25)

Because V_DAC(m) = V_ref + ΔV_CH, when the second term of Equation (25) is equal to ΔV_CH, the purpose of calibration can be achieved. Since D_TOP = D_BOTTOM = 100,000, V_OUT defaults to output V_ref.

Recent works report static-linearity improvements for current-steering DACs by (i) order-statistics/optimal-arrangement (OA) of unary MSB elements after foreground characterization (building a code-mapping LUT at start-up) [14,15], and (ii) split-DAC, comparator-based background calibration that generates a binary error (sign-LMS) to track slow PVT drift [16]. While our prototype keeps the baseline ramp DAC unchanged, these techniques are compatible with the present TS-SS architecture and could be added as non-intrusive options in future revisions for further INL/DNL reduction.

3. Post-Simulation Results

The proposed AFE is implemented with the SMIC 180 nm 1P6M process. The layout is shown in Figure 14 with an overall area of 3089 μm × 1895 μm. The power supply voltages for analog and digital circuits are 3.3 V and 1.8 V, respectively.

The transient simulation result of ROIC is shown in Figure 15. When the input current range is 7 nA–100 nA, the output voltage swing is 1.204 V, and the frame rate is 100 Hz.

We sample the output voltage and perform linear fitting on the input current and output voltage. The linearity simulation results are shown in Figure 16 with a linearity of 99.59%.

The noise is simulated using statistical analysis methods, as shown in Figure 17. The main sources of noise in the analog signal chain include the integrator, CDS, column buffer, and output buffer. Due to the uncorrelated nature of these noise sources, the total noise power can be obtained by simulating a single signal chain and summing the noise power contributions from each component. The total noise can be expressed as follows:

$$V_{n,OUT}^2=V_{n,DI}^2+V_{n,CDS}^2+V_{n,COL\_BUFFER}^2+V_{n,OUT\_BUFFER}^2$$

(26)

The terms on the right side of the equation represent the noise power of the DI circuit, the noise power of the CDS, the noise power of the column buffer, and the noise power of the output buffer, respectively. Since the readout circuit is a discrete-time circuit, the transient noise simulation method is employed for noise analysis. The output voltage from 500 simulation instances is sampled to generate a histogram for statistical analysis. The total noise is shown in Figure 17, with an output noise voltage of 243.7 μV and a dynamic range of approximately 73.87 dB.

Figure 16. Simulation result of the output voltage linearity of ROIC.

Figure 16. Simulation result of the output voltage linearity of ROIC.

Figure 17. Simulation result of noise.

Figure 17. Simulation result of noise.

When the input sine wave frequency is 9.96 kHz, the peak value is 1.2 V, and the sampling rate is 100 ks/s, the output FFT spectrum of the TS-SS ADC is shown in Figure 18. The SNDR is 68.38 dB. The SFDR is 79.14 dB, and ENOB reaches 11.06 bits.

The fixed peak-to-peak value of the input signal is 1.2 V, and the input frequency varies from 10 Hz to 50 kHz. The dynamic performance of ADC is shown in Figure 19. The simulation results show that the dynamic performance is good when the input frequency ranges from 10 Hz to its Nyquist frequency.

In order to evaluate the performance of the proposed AFE, the following references on ROICs and ADCs are compared, as shown in

Table 1. Performance comparison of ROIC.

Parameter	This Work	[17]	[18]	[19]	[20]	[21]
Array size	64 × 64	32 × 32	32 × 32	320 × 256	640 × 512	320 × 260
Pixel pitch (μm)	10	25	30	30	10	30
FWC (Me−)	2.8	NA	1.76	NA	7.8	NA
Power supply (V)	3.3 V/1.8	3.3	3.3	5.5	5	5
Frame rate (Hz)	100	>100	NA	NA	100	219.8
Linearity	99.59%	NA	99.82%	99.9%	>99.9%	99.08%
Output swing (V)	1.2	2	2.1796	NA	NA	NA
Noise (μV)	243.7	261	652.4	NA	NA	NA
Dynamic range (dB)	73.87	NA	70.42	34	NA	NA
Power consumption (mW)	28.94	<200	19.49	160	61	30

and

Table 2. Performance comparison of ADC.

Parameter	This Work	[9]	[22]	[23]	[24]	[25]
Process (nm)	180	90	110	130	90	130
Power supply (V)	3.3	2.8/1.5	NA	3.3/1.2	0.5	2.8/1.5
Structure	TS-SS	TS-SS	SS	TS-SS	SAR	SAR
Resolution (bit)	12	12	10	12	12	14
Input range (V)	1.7	NA	1	1.2	<0.5	1.2
Conversion time (μS)	10	39.6	34.2	10	10	2
ENOB (bit)	11.06	NA	8.8	11.25	10.7	NA

.

Our work realizes a more compact pixel structure, which has a larger area advantage compared to the pixel size reported in references [17,18,19,20], and is more suitable for the development needs of a high-resolution imaging detector for continuous improvement of pixel density. For noise suppression, a passive CDS module has been developed in a column-level processing channel, which effectively reduces the impact of reset noise on the signal chain through a timing control strategy. This design has better noise performance compared to references [17,18]. The pixel circuit adopts a DI structure, which significantly improves the output response linearity while maintaining charge conversion efficiency compared to the capacitor feedback transimpedance amplifier (CTIA) scheme used in reference [20]. Although the output swing is slightly smaller than the designs in references [17,18], good noise performance and dynamic range balance have been achieved by optimizing the noise suppression circuit and gain allocation strategy. In terms of power consumption, the dynamic bias mechanism introduced by the source follower and column buffer significantly reduces the overall power consumption by adjusting the bias current through the operation state and four channels in parallel.

Reference [9] achieved a low-power design using the smallest process node, but its conversion time is still nearly 40 μs. Compared to the traditional single-slope architecture used in reference [21], which requires a conversion time of 34.2 μs at 12-bit resolution, the TS-SS architecture proposed in this paper reduces the conversion time to 10 μs while maintaining the same resolution, significantly improving the frame rate in high-speed imaging scenes. Although reference [23] shortened the conversion time through a coarse/fine two-step quantization strategy, its 1.2 V quantization range is lower than the 1.7 V designed in this study, making it more susceptible to noise interference in low-light imaging. For the SAR ADC used in references [24,25], although the capacitive DAC has advantages in power consumption, it requires a large number of capacitor arrays, which greatly increases the layout area and is not suitable for large array readout circuits. In summary, compared with the previous work, the AFE in this paper has a fully integrated architecture, better noise performance, and a smaller area. And the ADC has a relatively balanced performance in quantization speed, accuracy, SNR, and other aspects.

4. Conclusions

For the application of SWIR detectors, an AFE based on the SMIC 180 nm 1P6M process is proposed in this paper. The size of the pixel array is 64 × 64, and the pixel size is 10 μm × 10 μm. The integration and holding capacitors are shared within the pixel to increase FWC within the limited pixel area. A passive CDS circuit is used in the column processing circuit to reduce noise and improve dynamic range. The ADC adopts a two-step single-slope architecture, and the comparator with four inputs solves the problem of storage capacitor charge leakage in the fine quantization stage. Meanwhile, a DAC is used to compensate for the charge injection of the switch. The post-simulation results show that the output swing of ROIC reaches 1.2 V, the output voltage linearity is 99.59%, the frame rate is 100 Hz, and the FWC is 2.8 Me⁻. The equivalent output noise is 243.7 μV, and the dynamic range reaches 73.87 dB. The TS-SS ADC has a sampling rate of 100 ks/s. SNDR is 68.38 dB, and ENOB is 11.06 bits.