Search Results (20)

To meet the demands for miniaturization, lightweight design, and high performance in modern electronic systems, advanced 3D TSV technology enables a substantial increase in storage capacity even within physically constrained form factors. This paper proposes a schematic design methodology and system-level integrated modeling approach for a four-layer stacked micro-module based on wafer-level packaging. By leveraging heterogeneous chip fan-out technology and TSV-based vertical stacking, the fabricated DDR3 micro-module achieves a compact footprint of 14 × 9 × 3.5 mm, a storage capacity of 4 GB, and a 64-bit bus width. Compared to conventional board-level mounting, the module reduces the footprint area by 95%. Following comprehensive multi-level testing, the micro-module fully complies with standard protocol requirements, enabling a paradigm shift in form factors for mobile computing devices while enhancing computational density and energy efficiency in data center server applications. Full article

Fine-pitch redistribution layers (RDLs) are key enabling technologies for fan-out wafer-level packaging (FOWLP)-based interposers used in chiplet and high-bandwidth memory (HBM) integration. In this study, a CAR-based photolithography process optimized for fine-pitch RDL fabrication was evaluated to realize 2 μm/2 μm line/space (L/S) RDL structures in an FOWLP environment. Key lithographic parameters, including exposure energy, focus offset, and thermal processing conditions, were systematically optimized to establish a stable and reproducible process window. Cross-sectional analysis confirmed the structural integrity of the electroplated RDL features formed under the optimized conditions. To assess functional feasibility, channel-level electrical simulations were performed using JEDEC-defined HBM3 signal assignments. Simulated eye diagrams indicate that the fabricated fine-pitch RDL interconnects are capable of supporting HBM3-class signal transmission with a moderate level of signal integrity. The presence of jitter and noise suggests that further optimization of RDL transmission line impedance is required. Rather than presenting a fully optimized interposer solution, this work provides an engineering-level assessment of lithographic and process constraints associated with implementing 2 μm class RDLs in FOWLP-based interposers, offering practical insight into fine-pitch RDL process window definition for advanced packaging applications. This work uniquely combines systematic CAR-based lithography optimization with cross-sectional structural validation and HBM3-class channel-level simulations to define a practical process window for 2 μm/2 μm RDLs in an FOWLP environment. Full article

Redistribution layer ordered routing is a critical problem in fan-out wafer-level chip-scale packaging (WLCSP) design. The traditional integer linear programming (ILP) method is inefficient in dealing with the ordered routing problem of multiple-capacity. Hence, we propose a high-performance ordered routing algorithm to solve the multiple-capacity ordered routing problem on the redistribution layer (RDL). First, we transform the ordered routing problem into the min-cost multi-commodity flow (MMCF) problem and use the linear programming (LP) method to solve it. Then, we use depth-first search (DFS) to process the LP method flow results and obtain the pre-assignment I/O candidate paths. Finally, the candidate path set obtains legal routing results by setting the crossing weight and a heuristic algorithm to receive the minimum crossing weight. When the pre-assignment I/O routing is uncompleted, we will set the capacity of tile nodes and edges to 0 and perform iterative routing for better results. Compared with the state-of-the-art work, experimental results show that our algorithm can solve twice the scale of the RDL ordered routing problems and reduce the routing time by 17% when dealing with multi-capacity RDL ordered routing problems. Full article

In this study, the reliability differences between a normal structure and a six-sided protective structure are investigated for 300 mm fan-out wafer-level packaging. Theoretical analysis indicates that the six-sided protective structure exhibits lower thermal stress (dropping by 9.06%) and superior thermal stability. The introduced epoxy molding compound (EMC) protective layer bonds tightly with other layers without changing the performance of the solder balls, such as shear strength and failure modes. After reliability testing, all the normal structure samples passed the high accelerated stress test (HAST) and temperature cycling testing (TCT), but none passed the pressure cooking testing (PCT). By contrast, the six-sided protective structure samples passed all tests. Scanning acoustic microscopy and cross-sectional scanning electron microscopy (SEM) pictures further confirmed that the six-sided protective structure passed the PCT. This result indicates that the reliability of the six-sided protective structure has been strengthened, consistent with the simulation analysis. A packaging solution for enhancing reliability by reducing structural thermal stress has been suggested. Full article

The rapid growth of artificial intelligence (AI), data centers, and high-performance computing (HPC) has increased the demand for large bandwidth, high energy efficiency, and high-density optical interconnects. Co-packaged optics (CPO) technology offers a promising solution by integrating photonic integrated circuits (PICs) directly within or close to electronic integrated circuit (EIC) packages. This paper explores the evolution of CPO performance from various perspectives, including fan-out wafer level packaging (FOWLP), through-silicon via (TSV)-based packaging, through-glass via (TGV)-based packaging, femtosecond laser direct writing waveguides, ion-exchange glass waveguides, and optical coupling. Micro ring resonators (MRRs) are a high-density integration solution due to their compact size, excellent energy efficiency, and compatibility with CMOS processes. However, traditional thermal tuning methods face limitations such as high static power consumption and severe thermal crosstalk. To address these issues, non-volatile neuromorphic photonics has made breakthroughs using phase-change materials (PCMs). By combining the integrated storage and computing capabilities of photonic memory with the efficient optoelectronic interconnects of CPO, this deep integration is expected to work synergistically to overcome material, integration, and architectural challenges, driving the development of a new generation of computing hardware with high energy efficiency, low latency, and large bandwidth. Full article

In this paper, the fabrication and testing of an integrated passive device (IPD) structure for X-band FMCW radar based on the fan-out wafer-level packaging (FOWLP) process are discussed. First, a transition line structure is added to the IPD structure to increase the upper impedance limit of the substrate, so as to reduce the process implementation difficulty and development cost. Second, the vertical soldered SubMiniature Push-On Micro (SMPM) interfaces testing method is proposed, reducing the testing difficulty of the dual-port structure with the antenna. Finally, the process fabrication as well as testing of the IPD structure are completed. The dimensions of the fabricated structure are 16.983 × 24.099 × 0.56 ${\mathrm{mm}}^3$. Test results show that, with a center frequency of 8.5 GHz, the actual operational bandwidth of the structure reaches 7.66% (8.095–8.74 GHz), with a maximum isolation of 33.9 dB. The bandwidth with isolation greater than 20 dB is 1.76% (8.455–8.605 GHz). The maximum gain at the center frequency is 2.02 dBi. Additionally, experimental uncertainty analysis is performed on different IPD structures, and the measurement results are basically consistent. These results validate the feasibility of the FOWLP process in the miniaturization of X-band FMCW radar antenna and other passive devices. Full article

This study presents an artificial intelligence (AI) prediction platform driven by deep learning technologies, designed specifically to address the challenges associated with predicting warpage behavior in fan-out wafer-level packaging (FOWLP). Traditional electronic engineers often face difficulties in implementing AI-driven models due to the specialized programming and algorithmic expertise required. To overcome this, the platform incorporates a graphical user interface (GUI) that simplifies the design, training, and operation of deep learning models. It enables users to configure and run AI predictions without needing extensive coding knowledge, thereby enhancing accessibility for non-expert users. The platform efficiently processes large datasets, automating feature extraction, data cleansing, and model training, ensuring accurate and reliable predictions. The effectiveness of the AI platform is demonstrated through case studies involving FOWLP architectures, highlighting its ability to provide quick and precise warpage predictions. Additionally, the platform is available in both uniform resource locator (URL)-based and standalone versions, offering flexibility in usage. This innovation significantly improves design efficiency, enabling engineers to optimize electronic packaging designs, reduce errors, and enhance the overall system performance. The study concludes by showcasing the structure and functionality of the GUI platform, positioning it as a valuable tool for fostering further advancements in electronic packaging. Full article

In advanced microelectronic packaging, high thermo-mechanical loads arise on the solder interconnects. Accurate and efficient modeling of the mechanical behavior is crucial in the design of the package, and the simulation results can provide a basis for estimations of the reliability of the assembly. However, the accuracy of the simulation results depends on the accuracy of the modeled geometry and the modeling simplifications and assumptions employed to achieve computational cost-efficient calculations. In this work, finite element analysis (FEA) of a Fan Out—Wafer Level Packaging (FO-WLP) layout was carried out considering the following variations: modeling domain (2-D and pseudo-3-D) was defined for creating the efficient calculation framework, where soldering material (SAC 305 and SACQ), incorporation of intermetallic compound (IMC), bond pad edge geometry (sharp and blunt) were modeled for cycles of thermal load. Stress and strain analysis was carried out to evaluate the solder behavior for the parameter variations. Furthermore, fatigue indicators were evaluated. An efficient planar simulation framework with 2-D and pseudo-3-D meshed geometries provides a quick estimate for the lower and upper bound for the strain, stress and strain energy-related parameters, respectively. This calculation framework can be employed for extensive parameter studies solved rapidly at low computational costs. Full article

This paper presents an integrated passive device (IPD) structure based on fan-out wafer-level packaging (FOWLP) for the front end of frequency-modulated continuous wave (FMCW) radar systems, focusing on enhancing the integration efficiency and performance of large passive components like antennas. Additionally, a new metric is introduced to assess this structure’s effect on the average noise figure in FMCW systems. Using this metric as a loss function, we apply the support vector machine (SVM) for electromagnetic simulation and the genetic algorithm (GA) for optimization. The sample fitting variance is 2.42 dB, reducing computation time from 12 min to under 1 millisecond, with the entire optimization completed in less than 100 s. The optimized IPD structure is 0.7 × 0.9 × 0.014 ${{\lambda }_0}^3$ in size and achieves over 35 dB isolation between the transmitter and receiver. Compared to the IPD model calculated by empirical formulas, the optimized device lowers the average noise figure by 15.2 dB and increases maximum gain by 4.19 dB. Full article

The hybrid integration of electronics in flexible substrates using fanned-out, wafer-level packaging (FOWLP) has recently gained significant attention, with numerous applications in wearable electronics, foldable displays, robotics, medical implants, and healthcare monitoring. In this study, a fully additive and scalable manufacturing process flow to realize a low-cost, flexible FOWLP system was introduced. Here, the integration of 36 LED chips in a biocompatible polydimethylsiloxane (PDMS) substrate was demonstrated using a stencil-printed silver (Ag) redistribution layer (RDL). The processes for the integration of chips, i.e., chip first (exposed die embedding), chip first (deep embedding with filled valleys) and chip last (RDL first), were implemented, and the corresponding samples were evaluated electrically. The bendability of the samples was also characterized at different bending diameters. Conclusively, it was shown that by using surface-modified PDMS as a flexible substrate and stretchable Ag paste as interconnect, flexible FOWLP can be produced. Full article

In this paper, a novel through mold via (TMV)-embedded fan-out wafer-level package (FOWLP) technology was demonstrated to manufacture the well-designed Antenna in Package (AiP) with ultrathin thickness (0.04 λ₀). Double-sided redistribution layers (RDLs) were employed to build the patch antenna, while a TMV interposer was used to connect the front and back RDLs. By optimizing the AiP’s parameters, the patch antenna can achieve a wide impedance bandwidth of 17.8% from 24.2 to 28.5 GHz, which can cover the 5G frequency bands. Compared with previous works, the proposed AiP has significant benefits in terms of its ultralow profile, easy processing, and high gain. Hence, the TMV-embedded FOWLP should be a promising technology for fifth generation (5G) millimeter wave (mm-Wave) applications. Full article

To meet the demands for miniaturization and multi-functional and high-performance electronics applications, the semiconductor industry has shifted its packaging approach to multi-chip vertical stacking. Among the advanced packaging technologies for high-density interconnects, the most persistent factor affecting their reliability is the electromigration (EM) problem on the micro-bump. The operating temperature and the operating current density are the main factors affecting the EM phenomenon. Therefore, when a micro-bump structure is in the electrothermal environment, the EM failure mechanism of the high-density integrated packaging structure must be studied. To investigate the relationship between loading conditions and EM failure time in micro-bump structures, this study established an equivalent model of the vertical stacking structure of fan-out wafer-level packages. Then, the electrothermal interaction theory was used to carry out numerical simulations in an electrothermal environment. Finally, the MTTF equation was invoked, with Sn63Pb37 as the bump material, and the relationship between the operating environment and EM lifetime was investigated. The results showed that the current aggregation was the location where the bump structure was most susceptible to EM failure. The accelerating effect of the temperature on the EM failure time was more obvious at a current density of 3.5 A/cm², which was 27.51% shorter than 4.5 A/cm² at the same temperature difference. When the current density exceeded 4.5 A/cm², the change in the failure time was not obvious, and the maximum critical value of the micro-bump failure was 4 A/cm²~4.5 A/cm². Full article

As the surface acoustic wave (SAW) filters incline to ultrafine, the failures resulting from the wafer molding process have become increasingly prominent. A methodology for coupling the mechanisms of die fly and die shift for the SAW filter miniatured with 737 $\mathsf{\mu }\mathrm{m}$ × 517 $\mathsf{\mu }\mathrm{m}$ × 200 $\mathsf{\mu }\mathrm{m}$ is developed for the trade-off between reliability and yields. In terms of die fly and die shift, the former occurs before the epoxy molding compound (EMC) is cured in the temperature rise period, while the latter occurs in the cooling stage after being cured. The die fly is induced by the fluid flow force in the high-temperature stage of heat compression, which is fatal for the scrap. Followed by the cooling stage, the CTE (coefficient of thermal expansion) misalignment between the die and epoxy molding compound (EMC) seriously affects the die shift and the following lithography process yields. The debonding critical energy in the mixed mode is employed to avert the die fly. Then, the die fly can be shunned by fine-tuning the die thickness, die layout, and EMC layout. A methodology to measure die shift was conducted, by which a total of 47,568 dies were embedded using compression molding. The mechanical error of the mounter and the die shift law are comprehensively leveraged, indicating that the die shift can be controlled within 50 $\mathsf{\mu }\mathrm{m}$ for 8-inch wafer-level packaging. Full article

This study investigated the impact of material properties of epoxy molding compounds on wafer warpage in fan-out wafer-level packaging. As there is currently a lack of comprehensive discussion on the various material property parameters of EMC materials, it is essential to identify the critical influencing factors and quantify the effects of each parameter on wafer warpage. The material properties include Young’s modulus of the epoxy molding compound before and after the glass transition temperature (Tg) range of 25–35 °C (E_L) and 235–260 °C (E_H), coefficient of thermal expansion (α1, α2), and the temperature change (∆T) between E_L and E_H. Results show that, within the range of extreme values of material properties, E_L and α1 are the critical factors that affect wafer warpage during the decarrier process in fan-out packaging. α1 has a more significant impact on wafer warpage compared with E_L. E_H, α2, Tg, and ∆T have little influence on wafer warpage. Additionally, the study identified the optimized material property of the epoxy molding compound that can reduce the maximum wafer warpage in the X and Y directions from initial values of 7.34 mm and 7.189 mm to 0.545 mm and 0.45 mm, respectively, resulting in a reduction of wafer warpage of 92.58% (X direction) and 93.74% (Y direction). Thus, this study proposes an approach for evaluating the impact of material properties of epoxy molding compounds on wafer warpage in fan-out wafer-level packaging. The approach aims to address the issue of excessive wafer warpage due to material variation and to provide criteria for selecting appropriate epoxy molding compounds to enhance process yield in packaging production lines. Full article

A fan-out wafer level package (FOWLP) with double-sided four redistribution layers (RDLs) and the mega pillars connecting the front and back RDLs has been proposed for millimeter-wave applications. A well-matched package-board transition has been designed in this paper. The simulated insertion loss for the transition is about 0.82 dB at 79 GHz, and the simulated return loss is better than 10 dB from 72 GHz to 86 GHz. More importantly, two different measurement methods based on the port reduction technique and the Thru-Reflect-Line (TRL) calibration technique have been proposed to get the S parameters of the transition. Moreover, the feasibility of the two methods has been verified by simulation. Full article