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Micromachines
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Applications of Data Sciences in Semiconductor Industry: Design, Manufacturing, Packaging...
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Applications of Data Sciences in Semiconductor Industry: Design, Manufacturing, Packaging and Testing

A special issue of Micromachines (ISSN 2072-666X). This special issue belongs to the section "D1: Semiconductor Devices".

Deadline for manuscript submissions: 31 May 2025 | Viewed by 5439

Special Issue Editors

Prof. Dr. Ping-Feng Pai

E-Mail Website
Guest Editor
Department of Information Management, National Chi Nan University, Nantou 54561, Taiwan
Interests: machine learning; neural networks; deep learning; big data; data mining; metaheuristics and optimization
Special Issues, Collections and Topics in MDPI journals
Prof. Dr. Yu-Po Wang

E-Mail Website
Guest Editor
1. Siliconware Precision Industries Co., Ltd. (SPIL), Taichung 42749, Taiwan
2. Bachelor of Science and Technology, National Chi Nan University, Nantou 54561, Taiwan
Interests: thermal/electrical simulation; design and advanced packaging development

Special Issue Information

Dear Colleagues,

With the rapid development of artificial intelligence in both hardware and software, the demand for semiconductors has highly increased in volume as well as function. The semiconductor theme mainly contains design, manufacturing, packaging, and testing. At the same time, the new advancements in information technology and information systems have also advanced data sciences including optimization, data mining, machine learning, deep learning, and artificial intelligence. The use of data sciences to perform data analysis represents an effective and efficient trend in many fields. The objective of this Special Issue is to utilize the latest data science techniques in the semiconductor industry, including design, manufacturing, packaging, and testing. The scope of this Special Issue is based on the application of data science approaches in coping with semiconductor industry issues.

Prof. Dr. Ping-Feng Pai
Prof. Dr. Yu-Po Wang
Guest Editors

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Micromachines is an international peer-reviewed open access monthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 2100 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • data sciences
  • machine/deep learning
  • artificial intelligence
  • optimization
  • semiconductor
  • integrated circuit design/manufacturing/packaging/testing
  • thermal/electrical simulation
  • design and advanced packaging development

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Further information on MDPI's Special Issue policies can be found here.

Published Papers (4 papers)

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Research

15 pages, 13760 KiB  
Article
Predicting Thermal Resistance of Packaging Design by Machine Learning Models
by Jung-Pin Lai, Shane Lin, Vito Lin, Andrew Kang, Yu-Po Wang and Ping-Feng Pai
Micromachines 2025, 16(3), 350; https://doi.org/10.3390/mi16030350 - 19 Mar 2025
Viewed by 431
Abstract
Thermal analysis is an indispensable aspect of semiconductor packaging. Excessive operating temperatures in integrated circuit (IC) packages can degrade component performance and even cause failure. Therefore, thermal resistance and thermal characteristics are critical to the performance and reliability of electronic components. Machine learning [...] Read more.
Thermal analysis is an indispensable aspect of semiconductor packaging. Excessive operating temperatures in integrated circuit (IC) packages can degrade component performance and even cause failure. Therefore, thermal resistance and thermal characteristics are critical to the performance and reliability of electronic components. Machine learning modeling offers an effective way to predict the thermal performance of IC packages. In this study, data from finite element analysis (FEA) are utilized by machine learning models to predict thermal resistance during package testing. For two package types, namely the Quad Flat No-lead (QFN) and the Thin Fine-pitch Ball Grid Array (TFBGA), data derived from finite element analysis, are employed to predict thermal resistance. The thermal resistance values include θJA, θJB, θJC, ΨJT, and ΨJB. Five machine learning models, namely the light gradient boosting machine (LGBM), random forest (RF), XGBoost (XGB), support vector regression (SVR), and multilayer perceptron regression (MLP), are applied as forecasting models in this study. Numerical results indicate that the XGBoost model outperforms the other models in terms of forecasting accuracy for almost all cases. Furthermore, the forecasting accuracy achieved by the XGBoost model is highly satisfactory. In conclusion, the XGBoost model shows significant promise as a reliable tool for predicting thermal resistance in packaging design. The application of machine learning techniques for forecasting these parameters could enhance the efficiency and reliability of IC packaging designs. Full article
(This article belongs to the Special Issue Applications of Data Sciences in Semiconductor Industry: Design, Manufacturing, Packaging and Testing)
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26 pages, 5241 KiB  
Article
Development of GUI-Driven AI Deep Learning Platform for Predicting Warpage Behavior of Fan-Out Wafer-Level Packaging
by Ching-Feng Yu, Jr-Wei Peng, Chih-Cheng Hsiao, Chin-Hung Wang and Wei-Chung Lo
Micromachines 2025, 16(3), 342; https://doi.org/10.3390/mi16030342 - 17 Mar 2025
Cited by 1 | Viewed by 577
Abstract
This study presents an artificial intelligence (AI) prediction platform driven by deep learning technologies, designed specifically to address the challenges associated with predicting warpage behavior in fan-out wafer-level packaging (FOWLP). Traditional electronic engineers often face difficulties in implementing AI-driven models due to the [...] Read more.
This study presents an artificial intelligence (AI) prediction platform driven by deep learning technologies, designed specifically to address the challenges associated with predicting warpage behavior in fan-out wafer-level packaging (FOWLP). Traditional electronic engineers often face difficulties in implementing AI-driven models due to the specialized programming and algorithmic expertise required. To overcome this, the platform incorporates a graphical user interface (GUI) that simplifies the design, training, and operation of deep learning models. It enables users to configure and run AI predictions without needing extensive coding knowledge, thereby enhancing accessibility for non-expert users. The platform efficiently processes large datasets, automating feature extraction, data cleansing, and model training, ensuring accurate and reliable predictions. The effectiveness of the AI platform is demonstrated through case studies involving FOWLP architectures, highlighting its ability to provide quick and precise warpage predictions. Additionally, the platform is available in both uniform resource locator (URL)-based and standalone versions, offering flexibility in usage. This innovation significantly improves design efficiency, enabling engineers to optimize electronic packaging designs, reduce errors, and enhance the overall system performance. The study concludes by showcasing the structure and functionality of the GUI platform, positioning it as a valuable tool for fostering further advancements in electronic packaging. Full article
(This article belongs to the Special Issue Applications of Data Sciences in Semiconductor Industry: Design, Manufacturing, Packaging and Testing)
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14 pages, 8059 KiB  
Article
The Effect of Through-Silicon-Via Thermal Stress on Metal-Oxide-Semiconductor Field-Effect Transistor Properties Under Cooling to Ultra-Low Temperatures
by Wenting Xie, Xiaoting Chen, Liting Zhang, Xiangjun Lu, Bing Ding and An Xie
Micromachines 2025, 16(2), 221; https://doi.org/10.3390/mi16020221 - 15 Feb 2025
Viewed by 603
Abstract
The thermal through-silicon-via (TTSV) has a serious thermal stress problem due to the mismatch of the coefficient of thermal expansion between the Si substrate and filler metal. At present, the thermal stress characteristics and strain mechanism of TTSV are mainly concerned with increases [...] Read more.
The thermal through-silicon-via (TTSV) has a serious thermal stress problem due to the mismatch of the coefficient of thermal expansion between the Si substrate and filler metal. At present, the thermal stress characteristics and strain mechanism of TTSV are mainly concerned with increases in temperature, and its temperature range is concentrated between 173 and 573 K. By employing finite element analysis and a device simulation method based on temperature-dependent material properties, the impact of TTSV thermal stress on metal-oxide-semiconductor field-effect transistor (MOSFET) properties is investigated under cooling down from room temperature to the ultra-low temperature (20 mK), where the magnitude of thermal stress in TTSV is closely associated with the TTSV diameter and results in significant tension near the Cu-Si interface and consequently increasing the likelihood of delamination and cracking. Considering the piezoresistive effect of the Si substrate, both the TTSV diameter and the distance between TTSV and MOSFET are found to have more pronounced effects on electron mobility along [100] crystal orientation and hole mobility along [110] crystal orientation. Applying a gate voltage of 3 V, the saturation current for the 45 nm-NMOS transistor oriented along channel [100] experiences a variation as high as 34.3%. Moreover, the TTSV with a diameter of 25 μm generates a change in MOSFET threshold voltage up to −56.65 mV at a distance as short as 20 μm. The influences exerted by the diameter and distance are consistent across carrier mobility, saturation current, and threshold voltage parameters. Full article
(This article belongs to the Special Issue Applications of Data Sciences in Semiconductor Industry: Design, Manufacturing, Packaging and Testing)
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15 pages, 10661 KiB  
Article
A Cross-Scale Electrothermal Co-Simulation Approach for Power MOSFETs at Device–Package–Heatsink–Board Levels
by Yuxuan Dai, Jiafei Yao, Jing Chen, Qingyou Qian, Maolin Zhang, Jun Zhang, Qing Yao, Chenyang Huang, Mingshun Sun and Yufeng Guo
Micromachines 2024, 15(11), 1336; https://doi.org/10.3390/mi15111336 - 31 Oct 2024
Cited by 1 | Viewed by 2605
Abstract
This paper proposes a cross-scale simulation approach for evaluating the steady-state electrothermal performance of power MOSFETs at the device–package–heatsink–board (DPHB) level. A co-simulation framework is designed by employing the iterative process of power loss and chip temperature to bridge the device and package–heatsink–board [...] Read more.
This paper proposes a cross-scale simulation approach for evaluating the steady-state electrothermal performance of power MOSFETs at the device–package–heatsink–board (DPHB) level. A co-simulation framework is designed by employing the iterative process of power loss and chip temperature to bridge the device and package–heatsink–board (PHB) level simulators. As a result, the cross-scale electrothermal coupling effect within multilevel settings is considered. Correspondingly, variation values in chip temperature and temperature-dependent drain current can be obtained at various voltage biases, level settings, and DPHB structural parameters, incorporating cross-level physical insights. The simulation results are compared with existing methods, and their features and limitations are discussed. Additionally, this paper also derives an empirical equation from the co-simulations to characterize the relationship between the drain current and the chip temperature under different operations exactly. A commercial MOSFET with TO-220F packaging is implemented in experiments to extract the chip temperature and drain current in electrothermal equilibrium. The method comparisons and fair agreement among simulations, equations, and measurements presents the proposed approach as generalized and powerful for describing variations in chip temperature and drain current considering from micrometer devices to millimeter packages–heatsinks–PCB boards, thus providing effective support for DPHB-level co-design. Full article
(This article belongs to the Special Issue Applications of Data Sciences in Semiconductor Industry: Design, Manufacturing, Packaging and Testing)
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