Search Results (1,432)

Conventional optoelectronic synapses rely on electrical signals for core operations, resulting in complex circuitry, limited response speed, and energy inefficiency. Herein, an all-optical synapse based on perovskite MAPbBr₂I is developed that directly converts optical stimuli into transmittance responses that mimic fundamental synaptic plasticity, including paired-pulse facilitation, short- and long-term memory, and learning. By using the dynamic transmittance response as input to an artificial neural network, high-accuracy dynamic pattern recognition of sequential characters is achieved. Furthermore, the optically controlled transmittance states are successfully integrated as programmable weights into a diffractive neural network, enabling all-optical classification of MNIST handwritten digits with an accuracy of 89%. This fully optical architecture, which eliminates electronic components and complex circuits, offers a promising pathway toward high-speed, energy-efficient vision systems by fundamentally circumventing the von Neumann bottleneck. Full article

Proton exchange membrane fuel cells (PEMFCs) play a key role in hydrogen-based energy systems; however, accurate and practical modelling remains challenging due to system nonlinearities, parameter variability, and degradation effects. This paper presents a low-complexity parameter estimation methodology for a simplified PEMFC equivalent circuit model using current-switching techniques. The approach enables direct extraction of key parameters, including internal resistance and capacitance, from transient voltage responses without requiring complex optimization or large datasets. Experimental validation was conducted using 100 W and 1 kW PEMFC systems under current loading and interruption conditions. The results demonstrate good agreement between measured and simulated voltage responses, with a maximum error below 10% and typical error levels in the range of ~1.4–3%. Compared to conventional mechanistic and data-driven models, the proposed method significantly reduces computational complexity and measurement requirements while maintaining high predictive accuracy. Moreover, the combination of the simplified equivalent circuit model with current-switching-based parameter estimation offers an effective and practical tool for electrical engineers, enabling real-time monitoring, control-oriented modelling, and seamless integration with power electronic systems. The proposed approach is particularly suitable for applications in DC microgrids and digital twin-based monitoring of hydrogen energy systems. Full article

A monolithic digital Silicon Photomultiplier (SiPM) featuring 1024 microcells with a 30-micrometer pitch and a 50% fill factor has been designed in a 110-nanometer CMOS image sensor technology. The device under consideration integrates both SPAD sensors and front-end electronics in the same substrate. It can count up to 1024 photons in less than 22 ns, while assigning timestamps to the first and last detected photons with a time resolution of less than 100 ps. A parallel counter structure combined with a fast adder tree provides photon counting in digital form with low latency, whereas a carefully balanced fast NAND tree ensures a fixed-pattern time uncertainty not exceeding 26 ps. The architecture incorporates in-pixel memory for individual cell disabling and configurable thresholding on the timing signal for noise mitigation. In order to optimize the fill factor, a part of the electronics is placed outside the array, while the most sensitive elements of the timing and counting circuits are laid out close to the sensor, in the SPAD array. A serial readout is employed to provide a single output connection per SiPM, thereby simplifying system integration. Full article

Cultural heritage, in all its tangible and intangible expressions, is undergoing a process of renewal driven by the integration of digital technologies and participatory approaches. This study presents a pilot project developed within the SAMOTHRACE Fundation, focused on the design of a Serious Game dedicated to the Norman Castle of Aci Castello in Sicily. The project explores how game-based learning and interactive storytelling can enhance visitor engagement, accessibility, and understanding of small-scale heritage sites that are often excluded from major cultural circuits. Using Unity and Blender, the prototype combines historical research, 3D reconstruction, and narrative interaction to transform the castle into an immersive educational environment. This initial phase also served as the basis for an academic thesis, laying the methodological groundwork for future expansion and evaluation. The results of this pilot provide preliminary quantitative evidence that serious games can support cultural communication strategies, foster emotional engagement, and stimulate curiosity toward minor heritage sites, while remaining compatible with the constraints of modest institutions. Ultimately, the project illustrates how even modest institutions can leverage digital innovation to revitalize their heritage assets, promote inclusive participation, and explore new models of interactive archaeology and community-centered cultural engagement. Full article

Neuromorphic computing seeks to mimic structure and function of biological neural systems to enable energy-efficient, adaptive information processing. A critical component of this paradigm is neural encoding—the translation of analog or digital input data into spike-based representations suitable for spiking neural networks (SNNs). This paper provides a comprehensive overview of major neural encoding schemes used in neuromorphic systems, including rate and temporal encoding, as well as latency, interspike interval, phase, and multiplexed encoding. The purpose of this paper is to explore the use of encoding techniques for deep learning applications. We discussed the underlying principles of spike encoding approaches, their biological inspiration, computational efficiency, power consumption, integrated circuit design and implementation, and suitability for various neuromorphic applications. We also presented our research on a hardware-and-software co-design platform for different encoding schemes and demonstrated their performance. By comparing their strengths, limitations, and implementation challenges, we aim to provide insights that will guide the development of more efficient and application-specific neuromorphic systems. We also performed an encoder performance analysis via Python 3.12 simulations to compare classification accuracies across these spike encoders on three popular image and video datasets. The performance of neural encoders working with both deep neural networks (DNNs) and SNNs is analyzed. Our performance data is largely consistent with the benchmark data on image classification from other papers, while limited performance data on the University of Central Florida’s 101 (UCF-101) video dataset were found in comparable studies on spike encoders. Based on our encoder performance data, the Interspike Interval (ISI) encoder performs well across all three datasets, preserving continuous, detailed spike timing and richer temporal information for standard classification tasks. Further, for image classification, multiplexing encoders outperform other spike encoders as they simplify timing patterns by enforcing phase locking and improve stability and robustness to noise. Within the SNN testbenches, the ISI-Phase encoder achieved the highest accuracy on the Modified National Institute of Standards and Technology (MNIST) dataset, surpassing the Time-To-First Spike (TTFS) encoder by 1.9%. On the Canadian Institute For Advanced Research (CIFAR-10) dataset, the ISI encoder achieved the highest accuracy. This ISI encoder had 22.7% higher accuracy than the TTFS encoder on the CIFAR-10 dataset. The ISI encoder performed best on the UCF-101 dataset, achieving 12.7% better performance than the TTFS encoder. Full article

The inherent bottleneck of the von Neumann architecture and the limited power budget of edge devices necessitate energy-efficient hardware solutions for artificial intelligence. Memristor-based In-Memory Computing (IMC) has emerged as a promising candidate; however, the high-power consumption of peripheral circuits, particularly Analog-to-Digital Converters (ADCs), and the reliability issues of memristive devices remain significant challenges. In this paper, we propose a hybrid Convolutional Spiking Neural Network (CSNN) architecture designed for resource-constrained edge computing. Our approach integrates digital Non-Leaky Integrate-and-Fire (NLIF) neurons with Knowm Self-Directed Channel (SDC) memristor-based synapses in a 1T1R crossbar array. To maximize power efficiency, we replace conventional high-resolution ADCs with a streamlined readout circuit utilizing a Current Sense Amplifier (CSA) and a 1-bit comparator. Furthermore, we employ an intensity-to-latency temporal coding scheme to minimize spike activity and mitigate device endurance degradation. We validated the proposed system using the MNIST dataset, achieving a classification accuracy of 97.8%, which is comparable to state-of-the-art floating-point SNNs using supervised learning methods. Power analysis confirms that our 1-bit readout method consumes only 18.4% of the energy required by an 8-bit ADC-based approach while maintaining negligible accuracy loss. Additionally, the deterministic single-spike nature of our temporal coding significantly reduces write stress on memristors compared to rate coding. These results demonstrate that the proposed hybrid CSNN offers a robust and energy-efficient solution for neuromorphic edge intelligence. Full article

Ambient backscatter systems enable passive sensing and information transfer by utilizing the reflection and modulation of incident radio-frequency (RF) signals. However, in real-world scenarios involving non-cooperative targets such as off-the-shelf printed circuit boards (PCBs), the backscattered signal is extremely weak and often obscured by strong direct-path self-interference (SI) at the receiver. This issue becomes even more severe when unintentional PCB structures act as radiating elements. In this work, we explore ambient backscatter leakage from a compromised PCB using a realistic measurement setup that includes separated transmit and receive antennas and a direct-conversion Universal Software Radio Peripheral (USRP)-based receiver. We demonstrate that residual carrier frequency offset (CFO), caused by oscillator mismatch and hardware imperfections, can spread the dominant SI in the baseband and completely mask the weak backscattered signal. To solve this problem, a software-based post-processing framework is applied. This method leverages the complex baseband representation enabled by the homodyne receiver to jointly manage the carrier and SI components without relying on intermediate-frequency processing or prior knowledge of the target signal parameters. Experimental results show that this approach significantly improves the detectability of weak backscattered baseband information that would otherwise be concealed within the raw I/Q data. This study emphasizes the importance of CFO-aware digital processing in ambient backscatter systems and offers new insights into unintended electromagnetic leakage mechanisms from commercial PCB platforms. Full article

Vehicle recharge time is a key barrier to widespread adoption of battery electric trucks, where megawatt class charging could be used to achieve refueling times comparable to internal combustion vehicles. This work presents the design and validation of a megawatt-capable rechargeable energy storage system (144 kWh, 40P384S) together with a physics-based modeling framework for safe 1 MW operation. The pack architecture is reconfigurable, enabling nominal 750 V (80P192S) propulsion mode as well as 1125 V and 1500 V charging modes compatible with the Megawatt Charging System (MCS). An equivalent circuit model is developed to relate cell-level parameters to pack-level power, heat generation, and temperature rise, providing guidance on feasible charge profiles and thermal limits. A Simulink-based digital twin of the reconfigurable pack is then used to analyze sensitivity to current sensor mismatch and to verify protection logic for multiple bus voltage configurations. Finally, pack tests up to 1 MW confirm the model-predicted operating envelope and illustrate practical constraints imposed by charger voltage and pack resistance. The combined hardware and modeling approach provides a reusable platform for studying extreme fast charging of medium- and heavy-duty BEV packs-class charging -capable rechargeable energy storage system (144 kWh, 40P384S) together with a physics-based modeling framework for safe 1 MW operation. The pack architecture is reconfigurable, enabling nominal 750 V (80P192S) propulsion mode as well as 1125 V and 1500 V charging modes compatible with the Megawatt Charging System (MCS). An equivalent-circuit model is developed to relate cell-level parameters to pack-level power, heat generation, and temperature rise, providing guidance on feasible charge profiles and thermal limits. A Simulink-based digital twin of the reconfigurable pack is then used to analyze sensitivity to current–sensor mismatch and to verify protection logic for multiple bus-voltage configurations. Finally, pack tests up to 1 MW confirm the model-predicted operating envelope and illustrate practical constraints imposed by charger voltage and pack resistance. The combined hardware and modeling approach provides a reusable platform for studying extreme fast charging of medium- and heavy-duty BEV packs. Full article

This paper introduces a cost-effective customised Printed Circuit Board (PCB) designed to establish an accurate Internet of Things (IoT) platform integrated with established Digital Twin (DT) models for advanced structural monitoring. The study focuses on developing a low-cost, precise PCB to synchronise real-time data between physical structures and their DT counterparts. The methodology includes a robust communication architecture utilising MQTT protocols, facilitating reliable data transmission and efficient integration with MATLAB for processing. Validation tests demonstrate high accuracy in data capture, with less than 1% deviation from conventional systems across multiple structural damage scenarios. This research highlights the potential of cost-effective PCB solutions for enhancing SHM and developing more resilient, proactive infrastructure management strategies. Full article

Sine and cosine wave synthesis is utilized for generating sinusoidal-like values in the digital domain. While this task is commonly handled through software, dedicated hardware like Direct Digital Synthesis (DDS) is also available. However, both methods rely on memory resources, such as look-up tables and Read-Only Memories (ROMs), which face latency limitations related to additional memory access times on top of additional $Si$ area. With the advent of real-time arithmetic for sine wave approximation, this paper presents a digital module that employs iterative multiply-accumulate (MAC) operations for sine and cosine synthesis. To support the integration of this module into Systems-on-Chip (SoCs), Field-Programmable Gate Arrays (FPGAs), and standalone Application-Specific Integrated Circuits (ASICs), a comprehensive figure of merit (FoM) comparison against various ROM-less methods is provided. When implemented on a Xilinx (AMD) XC7A100T-3CSG324 FPGA, the proposed architecture compared to other ROM-less solutions like the Taylor approximation, achieves 80.80% lower resource utilization, 80.89% reduced propagation delay, and 36.66% higher accuracy in sine and cosine wave approximation, both operating as 32-bit systems with one sample per clock cycle. Furthermore, the proposed sine accelerator, accompanying control and communication IPs, and custom firmware were deployed on an FPGA-based function generator platform and experimentally validated. Full article

This article aims to synthesize the current ecosystem of open-source tools for Integrated Circuit (IC) design, covering the entire digital design flow from Register-Transfer Level (RTL) description to fabricable layouts. The survey categorizes and analyzes tools across major stages of design, including code-generation tools, logic synthesis, simulation, and physical design flow. Special emphasis is given to the fabricable open-source Process Design Kit (PDK), which enables the physical realization of open-hardware projects. By examining interoperability, limitations, and maturity across this toolchain, the article provides a comprehensive overview of the Electronic Design Automation (EDA) landscape and identifies the research and educational opportunities that arise from democratizing silicon design through open and reproducible workflows. Full article

Spring-energy-storage circuit breakers are critical switching devices in power systems, and their operating reliability directly affects the safety and stability of the grid. In practical operations of transmission equipment, contacts may experience degradation such as poor contact, overheating, etc., due to multiple factors, including contact arcing erosion, mechanical wear, oxidation aging, and reduced contact pressure. Developing contact-point health monitoring and assessment enables prognostic maintenance, improves power supply reliability, and reduces operation and maintenance costs. This paper surveys the related research on health monitoring technologies for contact-point state in spring-energy-storage circuit breakers, systematically sorting out the operating principles and application characteristics, vibration and acoustic emissions monitoring, as well as electrical and mechanical parameter monitoring. It further analyzes the key bottlenecks faced by current monitoring technologies in online measurement accuracy, anti-interference capability, and engineering applicability, and finally discusses the future development trends of intelligent monitoring integrated with artificial intelligence, multi-source data fusion, and digital twin technologies. The research results provide theoretical reference and practical guidance for the upgrading of contact-point state monitoring technologies and the construction of intelligent operation and maintenance systems for spring-energy-storage circuit breakers. Full article

Automated optical inspection (AOI) for printed circuit boards (PCBs) requires localizing small, sparse defects under illumination drift and minor placement misalignment, while supporting fast, auditable pass/fail decisions. This paper presents a training-free, reference-based digital image processing framework with no learning/training stage that compares each defective query image with a small library of defect-free reference templates (for the same PCB layout/revision) using a small set of interpretable control parameters. A reference is selected by coarse-to-fine matching (fast pre-screening followed by SSIM refinement on a central region), and an optional global alignment is applied only when it increases SSIM to limit defect-driven over-correction. Defects are highlighted by a defect-likelihood field that fuses an SSIM-derived structural dissimilarity map with a normalized absolute-difference map, followed by connected-component extraction to produce confidence-ranked bounding boxes. The method achieves Precision = 0.9663, Recall = 0.9987, and F1 = 0.9822 at the best-F1 operating point (0.149 false positives per image). Under the adopted box-matching protocol, average precision reaches 0.984. Precision–recall and FROC curves are reported to support threshold selection under different false-alarm budgets. Full article

High-speed railway signaling equipment constitutes safety-critical infrastructure, wherein hardware failures may directly compromise operational safety. During the hardware prototyping and verification stage, structural testing is essential to detect latent faults in digital logic circuits and to ensure compliance with stringent safety integrity requirements. However, conventional test generation methods often suffer from long generation times and excessive test vector volume. To address these challenges, this study proposes a whale optimization-based dynamic compression Automatic Test-Pattern Generation (ATPG) algorithm. The proposed method integrates a discrete whale optimization algorithm (WOA) with a deterministic PODEM framework to dynamically compress generated test vectors. Additionally, a multi-path-sensitized PODEM enhanced with desensitization techniques is introduced to reduce backtracking and improve search efficiency. The proposed algorithm has been applied to the computer interlocking golden model netlist for testing purposes, achieving an impressive fault coverage rate of 100%. Test results from the ISCAS-85 standard circuit indicate that our approach significantly reduces both the length of the vector set and the time required for test generation when compared to traditional PODEMs without vector compression and pseudo-random combined PODEM vector generation methods. This advancement effectively enhances overall vector generation efficiency while maintaining comprehensive fault coverage. Full article

Dynamic Wireless Power Transfer (DWPT) is emerging as critical smart city infrastructure for sustainable urban mobility, enabling electric vehicle charging while driving. However, DWPT introduces complex fault scenarios requiring intelligent monitoring. Existing fault diagnosis approaches for wireless power transfer systems face three key complexities: (1) they are limited to static charging with only 2–4 fault categories, failing to address the time-varying coupling dynamics and segmented coil handover transients inherent in dynamic charging; (2) they lack integration with the host distribution grid, ignoring grid-side disturbances that propagate to charging stations; and (3) they offer only reactive detection without predictive capability for incipient fault management. This paper presents a deep neural network (DNN)-based fault diagnosis framework utilizing multi-station sensor fusion for DWPT systems integrated with the IEEE 13-bus distribution network to address these limitations. The system monitors 36 sensor features across three charging stations, employing feature-level concatenation with station-specific normalization for multi-station fusion, achieving 97.85% classification accuracy across eight fault types. Unlike static charging, the framework explicitly models time-varying coupling dynamics due to vehicle motion, including segmented coil handover effects. A digital twin provides dual-horizon prediction: long-term forecasting (24–72 h) for incipient faults and real-time detection under 50 ms for critical protection, with fault probability outputs and ranked fault lists enabling actionable maintenance decisions. The DNN outperforms SVM (92.45%), Random Forest (94.82%), and LSTM (96.54%) with statistical significance ($p<0.001$), while maintaining model inference latency of 4.2 ms, suitable for edge deployment. Circuit-based analysis provides analytical justification for fault signatures, and practical parameter acquisition methods enable real-world implementation. Five case studies validate robustness across highway, urban, and grid disturbance scenarios with detection accuracies exceeding 95%. Full article