A Whale Optimization-Based Dynamic Compression ATPG Algorithm for Computer Interlocking Equipment Testing

Abstract

High-speed railway signaling equipment constitutes safety-critical infrastructure, wherein hardware failures may directly compromise operational safety. During the hardware prototyping and verification stage, structural testing is essential to detect latent faults in digital logic circuits and to ensure compliance with stringent safety integrity requirements. However, conventional test generation methods often suffer from long generation times and excessive test vector volume. To address these challenges, this study proposes a whale optimization-based dynamic compression Automatic Test-Pattern Generation (ATPG) algorithm. The proposed method integrates a discrete whale optimization algorithm (WOA) with a deterministic PODEM framework to dynamically compress generated test vectors. Additionally, a multi-path-sensitized PODEM enhanced with desensitization techniques is introduced to reduce backtracking and improve search efficiency. The proposed algorithm has been applied to the computer interlocking golden model netlist for testing purposes, achieving an impressive fault coverage rate of 100%. Test results from the ISCAS-85 standard circuit indicate that our approach significantly reduces both the length of the vector set and the time required for test generation when compared to traditional PODEMs without vector compression and pseudo-random combined PODEM vector generation methods. This advancement effectively enhances overall vector generation efficiency while maintaining comprehensive fault coverage.

1. Introduction

High-speed railway (HSR) signal systems constitute safety-critical infrastructure that ensures reliable train operation under high-speed and high-density conditions. For instance, systems such as Automatic Train Protection (ATP) and computer interlocking equipment must adhere to Safety Integrity Level 4 (SIL-4) safety integrity requirements. Comprehensive testing and verification of computer interlocking equipment should be conducted throughout its entire life cycle, with rigorous evaluation at each developmental stage being essential. During the equipment development phase, accurately identifying equipment faults, improving the testing accuracy and efficiency of related equipment boards, and developing corresponding testing algorithms are key to ensuring the safe and reliable operation of computer interlocking systems.

Case-based testing has emerged as a practical alternative to conventional board-level testing for complex railway signaling systems. In automatic test case generation, approaches such as ISR-MCF-based methods have been developed to improve state transition coverage while reducing execution time and costs through multiple search strategies [1]. Enhancements to depth-first search (DFS) using Unified Modeling Language (UML) activity and sequence diagrams [2], along with assertion-augmented generation techniques [3], have aimed to produce more comprehensive test cases. For verification purposes, formal methods include timed automata (TA) consistency checking via UPPAAL-TRON for Automatic Train Operation (ATO) software–model alignment and fault variation analysis [4], high-level Petri net simulations to resolve train path conflicts and deadlocks [5], and dynamic fault tree transformations into Bayesian networks that quantify the impact of on-board subsystem failures on Chinese Train Control System level 3 (CCTS-3) reliability [6].

More recently, intelligent and automated approaches have solved the problems of excessive time consumption and insufficient coverage in traditional test case generation. Baqar et al. investigated AI techniques to automate and enhance test case generation in railway contexts, while highlighting limitations such as algorithmic bias, the need for high-quality domain-specific training data, and integration difficulties with existing workflows [7]. An intelligent management and supervision system for high-speed railway interlocking tests has been proposed, enabling automated analysis of test processes, data tables, and simulation integration to improve traceability and efficiency in safety-critical verification [8]. Additionally, third-party automated testing platforms leveraging image recognition technology have been developed for computer interlocking systems, facilitating the automatic generation of yard data, the execution and verification of test cases, and test sequence optimization via enhanced simulated annealing algorithms, resulting in reduced testing time [9]. Scenario-based simulation frameworks using extended train simulators have also been introduced for closed-loop validation of highly automated railway systems, enhancing test realism, coverage, and compliance with standards such as TSI [10]. Furthermore, automatic testing methods based on recognition of the interlocking host computer interface have been explored to enable script-free, intelligent verification of computerized interlocks [11].

The aforementioned methods, while advancing automated testing in railway signaling systems, still require enhancements in test speed, system stability, and test accuracy, particularly for complex, large-scale interlocking logic circuits. ATPG technology, originally developed for chip design testing, proves highly effective in generating compact test vectors and thus holds significant promise for structural testing of high-speed railway equipment hardware. ATPG automatically generates test vectors for the circuit under test based on deterministic or heuristic algorithms to achieve high fault coverage with minimal test set size. In 1966, Roth et al. introduced the deterministic test vector generation algorithm D within ATPG technology. This process entails propagating fault effects to the primary output by identifying all paths from the fault location to every output of the circuit affected by this propagation, ultimately resulting in a definitive test vector tailored for a particular fault [12]. In 1981, Goel proposed an enhanced version of the D algorithm known as the path-oriented decision algorithm (PODEM). PODEM minimizes the backtracking occurrences inherent in the D algorithm by implicitly enumerating branch limits and assigning values to original inputs before deriving the corresponding test vector for each tested fault [13]. The FAN algorithm represents an advancement over PODEM with its fan-out oriented approach. In scenarios where only one gate exists at a decision edge, FAN employs a unique sensitizing path to expedite processing while segmenting circuits into multiple fanless branches. Unlike PODEM’s strategy of tracing back to primary inputs within circuits, FAN traces back to the HEADLINE points of fanless branches. By maximizing backtracking across numerous paths, this approach significantly enhances generation efficiency [14].

As integrated circuit scale increases, test data volume and application costs rise substantially. To mitigate this issue, numerous test vector compression methods have been proposed, which can be categorized into static and dynamic compression techniques. For static compression, Neophytou et al. applied the D-intersection rule to merge compatible test vectors containing don’t-care bits, consolidating them into fewer vectors and reducing overall test set size [15]. For dynamic compression, Abramovici et al. introduced the double-detection technique, which replaces original vectors when newly generated sets meet specific compatibility conditions during ATPG [16]. Kareem et al. proposed a Satisfiability (SAT)-based dynamic compression framework using multi-valued coding to generate fewer vectors while maintaining or improving fault coverage [17].

Recent progress has further advanced test compression, especially dynamic methods tailored to ultra-large-scale and advanced-node designs. A comprehensive review of test stimulus compression for ultra-large-scale integrated circuits categorizes techniques into coding-based, scan chain optimization-based, and enhanced coding efficiency methods, emphasizing dynamic reconstruction strategies that balance control data overhead with compression ratio [18]. Low-power dynamic compression schemes, such as Dcompress for launch-on-capture transition fault testing, employ novel seed encoding to achieve substantial reductions in test data volume without sacrificing coverage [19]. Configuration-based dynamic compaction procedures enable on-the-fly compaction during ATPG, improving efficiency for complex scan architectures [20]. Additionally, post-ATPG static compaction using Pure MaxSAT solvers with partial fault dictionaries and n-detect modes has demonstrated pattern count reductions of up to 71.90% in open-source tools while preserving fault coverage [21].

With the advancements in modern cloud computing and the availability of vast amounts of storage and data, machine learning (ML) has reached a pinnacle within recent technological developments. Within the realm of ML, swarm intelligence optimization algorithms have been extensively utilized for test vector generation [22]. E.M. Rudnick et al. introduced a genetic algorithm (GA) framework for generating tests for sequential circuits, which facilitated the evolution of candidate test vectors and achieved high fault coverage in ISCA-89 sequential reference circuits [23]. Gu Yuan-Liang et al. proposed an automatic method for generating tests for sequential circuits based on particle swarm optimization (PSO), demonstrating both a high fault coverage and a reduced CPU time required for test generation [24]. Recently, Mirjalili, Seyedali, and colleagues presented a novel intelligent population optimization algorithm known as the whale optimization algorithm (WOA). WOA mimics the hunting behavior of humpback whales in oceanic environments; similarly to other metaheuristic algorithms, its search process commences with initializing a random set of solutions. The WOA consists of three stages: searching for prey, surrounding targets, and employing a spiral bubble hunt strategy. The efficacy of this algorithm hinges on achieving an optimal balance between global exploration and local exploitation phases [25].

With advances in cloud computing and data availability, machine learning (ML) and swarm intelligence algorithms have become prominent in test vector generation [22]. E.M. Rudnick et al. proposed a genetic algorithm (GA) framework for sequential circuit test generation, enabling evolution of candidate vectors and achieving high fault coverage on ISCAS-89 benchmarks [23]. Gu Yuan-Liang et al. developed a particle swarm optimization (PSO)-based method for automatic test generation in sequential circuits, demonstrating high fault coverage with reduced CPU time [24]. Dorigo et al. introduced ant colony optimization (ACO), inspired by ant foraging via pheromone trails and probabilistic path construction. ACO has been widely applied to combinatorial problems, including test suite generation and minimization, effectively covering interaction paths, with good coverage in graph-based testing [25]. Karaboga proposed the artificial bee colony (ABC) method, mimicking honey bee foraging with employed, onlooker, and scout phases. ABC has been successfully used in test suite minimization and generation, providing balanced exploration–exploitation for compact test sets and high fault coverage in multimodal problems [26]. Recently, Mirjalili and Lewis presented the whale optimization algorithm (WOA), which emulates humpback whale hunting behavior. Similarly to other metaheuristics, WOA initializes random solutions and iterates through three phases: prey search, encircling, and spiral bubble-net hunting. Its effectiveness relies on a strong balance between global exploration and local exploitation [27].

Table 1. Comparison of metaheuristic algorithms for test pattern and test suite generation and optimization.

Algorithm	Main Advantages	Main Limitations	Typical Performance Notes
GA	High diversity, robust for discrete problems, widely validated high fault coverage	Slow convergence, many tuning parameters, premature convergence risk	Larger test sets, outperformed in size reduction by newer swarms
PSO	Fast initial convergence, few parameters, effective in hybrid discrete spaces	Prone to local optima trapping, weaker in high-dimensional combinatorial spaces	Good CPU time reduction, moderate suite size minimization in higher interactions
ACO	Excellent for combinatorial coverage problems, builds strong interaction tables	High computational overhead, parameter-sensitive, slower in large search spaces	Effective t-way coverage but typically larger suites and longer runtime
ABC	Balanced exploration/exploitation, good for multimodal minimization problems	Slower in very high dimensions, scout phase inefficiency	Competitive suite size reduction, stable but convergence slower in many combinatorial benchmarks
WOA	Very simple structure, minimal parameters, superior exploration–exploitation balance via bubble-net	Requires discretization for binary/combinatorial	Frequently generates near-optimal test suites, faster convergence and better stability in t-way/higher interactions, outperforms.

compares commonly used metaheuristic algorithms for test pattern/suite generation and optimization. As shown in the table, compared to other algorithms, WOA can generate more compact test suites under higher interaction strengths, with faster convergence and reduced premature convergence. These characteristics make discrete WOA particularly suitable for integration into our dynamic compression framework within PODEM, where efficient and low-overhead vector minimization is critical for safety-critical high-speed railway interlocking applications, without requiring complex parameter tuning.

Recent studies have extended WOA to test suite optimization, particularly in combinatorial and t-way testing, wherein the aim is to generate minimal yet effective test sets that cover parameter interactions. For example, Q-learning-enhanced WOA variants have been proposed to improve convergence and coverage in constrained combinatorial test suite generation [28]. Structurally modified and tolerance-enhanced WOA strategies have demonstrated superior performance in higher-interaction-strength t-way testing, producing more compact test suites while effectively reducing premature convergence [29]. Moreover, input–output relation-based combinatorial testing using WOA has yielded competitive results, generating near-optimal test suites that outperform or match traditional methods such as Greedy and TVG, especially at higher interaction orders [30].

Building on these advancements, this paper proposes a novel dynamic compression ATPG algorithm that integrates a discrete whale optimization algorithm with an enhanced PODEM framework. By incorporating multi-path sensitization and desensitization techniques to replace conventional backtracking, the approach enables the dynamic compression of test vectors during the generation process. The proposed method is applied to the golden model netlist of the TYJL-III (G) computer interlocking equipment, with emphasis on station establishment and unlocking route logic verification. Test vector generation is conducted on the electrical network tables, and the algorithm’s performance is validated through comparative experiments on ISCAS-85 benchmark circuits. Results show 100% fault coverage on the interlocking model, together with substantial reductions in test vector length and generation time compared to traditional PODEM, non-compressed variants, and pseudo-random combined PODEM methods.

The remainder of the paper is structured as follows: Section 2 elaborates on the proposed dynamic compression ATPG algorithm based on discrete whale optimization, including the PODEM fundamentals, desensitization techniques, compression mechanism, and WOA integration. Section 3 reports experimental results on the TYJL-III (G) interlocking golden model and ISCAS-85 benchmarks. Section 4 provides discussion and analysis, and Section 5 concludes with key findings and future directions.

2. Proposed Whale Optimization-Based Dynamic Compression ATPG Algorithm

The ATPG algorithm is designed to generate test vectors for the specified fault set of a circuit. In practical applications, various types of faults may arise, including typical stuck-at faults, open circuit faults, bridge faults, and others. Among these, stuck-at faults are the most prevalent in circuits and can effectively represent the fault types encountered in the majority of circuits. Stuck-at faults refer to conditions where the signal value at a port or line within the circuit remains constant throughout its operational process. Based on logic levels, stuck-at faults can be categorized into two types: stuck-at-1 faults (where the logic level is fixed at 1) and stuck-at-0 faults (where the logic level is fixed at 0) [31]. In implementing the ATPG algorithm, a gate-level netlist of the circuit serves as an input file; this netlist is typically derived from logic synthesis conducted using RTL code written in Verilog language.

2.1. Deterministic Vector Generation Algorithm Based on a PODEM

The PODEM is an improvement of the D algorithm, so it inherits the concepts related to the D algorithm. The five-valued logic (0, 1, X, D, $\overline{\mathrm{D}}$) is used to describe the state of each lead in the circuit under fault conditions. The representation of the five-valued logic is shown in Figure 1:

In the five-value logic, “0” means that in the fault-free circuit the line value is 0, and in the faulty circuit the line value is also 0, “1” means that in the fault-free circuit the line value is 1, and in the faulty circuit the line value is also 1. The above two logic values have the same line values in the faulty circuit and the non-faulty circuit, and cannot reflect the impact of the fault. “D” means that the line value is 1 in the fault-free circuit and 0 in the faulty circuit, “$\overline{\mathrm{D}}$” means that the line value is 0 in the fault-free circuit and 1 in the faulty circuit. The above two logic values indicate that the line values in the faulty circuit and the non-faulty circuit are different, which can reflect the impact of the fault; “X” represents an uncertain value. When the logic value of the main input of the circuit is “X”, it means that the value of the main input is irrelevant to the test of the target fault, and the main input is called a don’t-care bit. The PODEM treats testing as a branch-and-bound problem, so that the backtracking (BACKTRACK) phenomenon only occurs at the main input. Compared with the reverse tracking line confirmation process in the D algorithm, the number of attempts is reduced, and a heuristic algorithm is used for backtracking (BACKTRACE), which increases the heuristics, simplifies the algorithm, and speeds up the test generation process. The flowchart for the backtracking algorithm is given in Algorithm A.

Algorithm A Backtrace to PI—find the best path to PI

1:       Start with objective line value; 2:       While line is not a PI 3:            If all gate inputs must be set (i.e., non-controlling values) 4:                Take the hardest to satisfy; 5:            Else if only one gate input is to be set (i.e., controlling) 6:                Take the easiest to satisfy; 7:            End if; 8:       End while; 9: 10:     Easiest: closer to input, better controllability, etc.; 11:     Hardest: farther from inputs, lower controllability, etc.; 12: 13:     Easiest: if it is satisfied, objective is met; 14:     Hardest: if the objective is not to be satisfied we know sooner;

During the backtracking process, the choice between multiple inputs of a circuit internal node or gate is a problem that must be faced. In most cases, the choice is determined by the difficulty of applying the control value from the circuit input to the internal line or observing the internal line value at the circuit output. These two difficulties are called controllability and observability problems, respectively. The SANDIA Controllability/Observability Analysis Program (SCOAP) is a widely used testability metric that analyzes the controllability and observability of each network in the circuit [32]. Although SCOAP is a classical static testability measure introduced in 1980s, it remains relevant in contemporary ATPG research. Recent works employ SCOAP values to identify hard-to-control/observe nodes for automated test point insertion and scan optimization, guiding ATPG tools toward higher efficiency and fault coverage [33]. SCOAP continues to serve as a lightweight, topology-independent baseline for controllability/observability estimation, particularly in academic benchmarks and initial design-for-testability assessments. It belongs to the category of topology-based analysis and is only related to the topological structure of the circuit. It can complete the parameter calculation while determining the circuit to be tested. It is a static analysis and can exist independently of the ATPG algorithm program. In addition, SCOAP calculates six values for each node N, including combinatorial parameters and timing parameters. However, only these three combinatorial parameter values are considered in this topic: combinatorial 0-controllability of CC0(N)-N, combinatorial 1-controllability of CC1(N)-N, and combinatorial observability of CB(N)-N. The ability to apply an input vector to the main input of a circuit and obtain the appropriate logical value at the expected position of the circuit is called controllability. CC represents the difficulty of controlling the value on that particular node to be 0 or 1. If the value is higher, it is more difficult to control. The value of CC is between 1 and infinity. To calculate the CC value, CC(PI) is set to 1, and the gate propagation rule is followed at each logic level, and the calculation is performed in the direction from PI to the main output (PO). The combinatorial observability (CB) represents the difficulty of PI required to propagate the value on a particular node to PO. The range of CB values is between zero and infinity. To calculate the observability value, CB(PO) is initially set to zero and traced back from PO to PI.

Table 2. Calculation method for SCOAP combination parameters of different types of logic gates.

	Rules for Calculating Controllability Parameters	Observability Parameter Calculation
NOT Gate	CC0(w) = CC1(a) + 1	CB(a) = CB(w) + 1
	CC1(w) = CC0(a) + 1
AND Gate	CC0(w) = min (CC0(a), CC0(b)) + 1	CB(a) = CB(w) + CC1(b) + 1 CB(b) = CB(w) + CC1(a) + 1
	CC1(w) = CC1(a) + CC1(b) + 1
NAND Gate	CC0(w) = CC1(a) + CC1(b) + 1
	CC1(w) = min (CC0(a), CC0(b)) + 1
OR Gate	CC0(w) = CC0(a) + CC0(b) + 1	CB(a) = CB(w) + CC0(b) + 1 CB(b) = CB(w) + CC0(a) + 1
	CC1(w) = min (CC1(a), CC1(b)) + 1
NOR Gate	CC0(w) = min (CC1(a), CC1(b)) + 1
	CC1(w) = CC0(a) + CC0(b) + 1
Fan-out	CC0(s) = CC0(a) = CC0(b)	CB(s) = min (CB(a), CB(b))
	CC1(s) = CC1(a) = CC1(b)
XOR Gate	CC0(w) = min (CC0(a) + CC0(b), CC1(a) + CC1(b)) + 1	CB(a) = CB(w) + min (CC0(b), CC1(b)) + 1
	CC1(w) = min (CC1(a) + CC0(b), CC0(a) + CC1(b)) + 1	CB(b) = CB(w) + min (CC0(a), CC1(a)) + 1

gives the calculation method of the SCOAP combinatorial parameters of different types of logic gates.

As described above, the heuristic algorithm SCOAP can guide the backtracking process well, but if there are fan-out nodes in the circuit, the complexity of test generation will be greatly increased. After the fault is activated, it propagates in the direction of the main output of the circuit. In a circuit with a fan-out node, there are several possible choices for the sensitive path from the fault point to the main output. When the stem of the fan-out node goes through a series of lines and becomes the input of a certain gate, this phenomenon is called reconvergence. Under the required input signal, the choice of value of the reconvergent fan-out structure may cause conflicts and “fault annihilation” and it is necessary to backtrack and choose another path or change the value of the path. This process may involve trial and error, so the existence of fan-out nodes is the main reason for the large complexity of the PODEM. If it can be assumed that each fault can be detected by single-path sensitization, then the path sensitization algorithm will be much simpler, because multi-path sensitization must consider that the number of paths grows exponentially with the circuit size; multi-path sensitization is essential for detecting some faults. Therefore, a complete test generation algorithm must be prepared to explore multiple sensitive paths in most cases.

2.2. “Fault Annihilation” and Desensitization Algorithms

The calculation method for the SCOAP parameters has been explained in Section 2.1. In the actual application of the PODEM, the values of CC0 and CC1 are responsible for guiding the selection of gate inputs in the circuit during the backtracking process, while CB is used to select the fault propagation path. During the backtracking process, if the gate input value required to achieve the output value is a control value (0 for the AND gate and 1 for the NOT gate), the input of the gate that is most easily controlled is selected, otherwise the input of the gate that is least easily controlled is selected for further backtracking. The reason is that in the latter case, we must set all the inputs of the gate to non-control values, starting from the most difficult input to control, and if a failure occurs, the failure will come earlier. The selection of the fault propagation path refers to the concept of the D boundary in the D algorithm. The D boundary (or D edge) is composed of gates in the circuit, and one of the inputs of the gate has at least one D or $\overline{\mathrm{D}}$ that has not yet propagated to the output of the gate. For example, with a two-input AND gate, whose input values are D and X, respectively, and whose output value is also X, this gate belongs to the D boundary. The significance of the existence of the D boundary is to provide a candidate range for the fault propagation path. The gate with the smallest CB parameter value at the output end in the D boundary is selected as the path for the next fault propagation. The smaller the CB value, the easier it is for the fault effect on the line to propagate to the main output of the circuit.

During the fault propagation process, the reconvergent fan-out will lead to “fault annihilation”. “Fault annihilation” refers to the situation where the fault effect disappears at the output end of the gate when a specific input combination appears at the input end of the gate in the D boundary. As shown in Figure 2, there are three situations that cause “fault annihilation”: (a) There are both fault effects (D or $\overline{\mathrm{D}}$) and control values at the gate’s input end. (b) There are the same number of opposite fault effects at the gate’s input end, and the values of the other input ends are non-control values. (c) In case (b), there is a control value at the input end of the gate. All three situations will make the output value of the gate in the D boundary a control value, which is 0 for the AND gate and 1 for the OR gate, and the fault effect disappears during the propagation process of the gate. If all the gates in the D space experience “fault annihilation” during a certain propagation process, then it is said that a certain backtracking line selection failed during the previous backtracking process.

When all gates in the D boundary experience fault annihilation, the fault cannot continue to propagate toward the circuit output. At this time, the PODEM will perform a backoff and a new round of backtracking. It is difficult to guarantee that fault annihilation will not occur again in a new round of backoff and backtracking. Repeated backoff and backtracking will waste a lot of resources and increase algorithm complexity and running time. In this case, we establish a new set of gates in the circuit—the FD boundary [34]. Similarly to the D boundary, the FD boundary is the set of all gates in the circuit that experience fault annihilation. In order to obtain a test vector for a given fault, we must have at least one path that propagates the fault impact to the primary output. If any fault annihilation occurs on reconvergent gates and the D space is not empty, we can still get a test vector because the fault can propagate to the primary output through another path. If the D boundary is empty, the fault cannot propagate to the primary output. In this case, we can select a reconvergent gate with the smallest CB parameter value in the FD boundary, that is, the one closest to the main output, and select some inputs of the gate to be forced to be assigned non-control values, so that the gate meets the D boundary conditions and the fault effect continues to propagate. We call this process “desensitization”, and the desensitization process is shown in Figure 3. After desensitization is completed, start backtracking from the input of the desensitized gate and continue the PODEM algorithm to generate the test vector of the target fault.

2.3. Dynamic Compression of Test Vector Sets

In the ATPG process, the non-deterministic test vector generation algorithm is a common method to reduce the test generation time. It uses a pseudo-random number generator to generate test vectors and calculates the fault coverage of the generated vectors through fault simulation [35]. Since the test vectors generated by pseudo-random testing can quickly reach a high fault coverage in a short time, a time-varying pseudo-random perturbation ATPG algorithm was proposed previously, which combines pseudo-random testing with deterministic testing algorithms, reducing the duration of the test vector generation process and increasing the fault coverage [36].

Although the above method reduces the test time, in the deterministic generation algorithm, a test vector will be generated for each target fault in the fault list. In general, as long as the fault effect is propagated to any main output end of the circuit, it can be proved that the target fault has been detected. In this case, the algorithm only needs to trace back to the main input related to the activation and propagation of the target fault, and the remaining main inputs are in an “undetermined” state. For this target fault, the remaining main inputs are irrelevant bits, which are represented by “X” in the five-value logic. This state is called “incomplete assignment”.

Therefore, the test vector set generated by the pseudo-random generation combined with the deterministic test algorithm will have the following two problems: (1) The test vector generated by the pseudo-random part does not have “don’t-care bits”, that is, all the main inputs of the circuit are assigned values, so the “incompletely assigned” vector generated by the deterministic test contains the test vector generated by the pseudo-random generation part. (2) In the test vector set generated by the deterministic generation part, the number of vectors is the same as the number of faults it detects. In such a test vector set, there are many compatible “incompletely assigned” test vectors. By assigning values to the don’t-care bits, a “completely assigned” test vector is generated. In the test vector set, the “completely assigned” vector is used to replace several compatible “incompletely assigned” vectors to complete the compression of the vector set and shorten the length of the test vector set. The above two problems are shown in Figure 4.

Dynamic compression can be embedded in the ATPG algorithm and compression is completed during the generation process of each test vector. Therefore, the compression method proposed in this paper is as follows: after the PODEM generates an “incompletely assigned” test vector, the irrelevant bits of the vector are assigned, and a “completely assigned” test vector is generated based on this “incompletely assigned” vector. Then, the faults that can be detected by the “completely assigned” test vector are deleted from the fault list. After the dynamic compression of the test vector is completed, the PODEM algorithm continues.

2.4. Whale Optimization

An important issue in the dynamic compression process of the test vector set is how to assign values to the irrelevant bits of the “incompletely assigned” test vector. The test vector generation process can be divided into two parts: fault activation and fault propagation. When a vector is applied to the main input of the circuit, if the line value where the fault to be tested is located is D or in the five-value logic, the fault is said to be successfully stimulated. The process of D or propagating to the main output along a certain path in the circuit is called fault propagation. The more faults a vector activates, the more possible faults can be tested, and the more faults the vector may detect. Therefore, when assigning values to the irrelevant bits of the “incompletely assigned” test vector, it is ensured that the “completely assigned” vector generated after the assignment can activate as many faults to be tested as possible.

The whale optimization algorithm is a swarm intelligence optimization algorithm based on humpback whale hunting behavior in nature. The algorithm is inspired by the various behavioral characteristics of whales in the process of looking for food, such as circling, swimming, diving, etc. These behaviors can help whales find food more effectively. The whale optimization algorithm mainly includes three steps, namely, encirclement hunting, bubble attack, and food searching. The whale optimization algorithm is a global algorithm that ultimately finds the global optimal solution for a problem. The dynamic compression problem in this article is modeled: the combination of all irrelevant bits in a test vector corresponds to a whale population, and the value of each bit corresponds to the position of each individual whale in an iteration. The number of faults that can be triggered by a complete “fully assigned” test vector is used as the fitness value to evaluate an iteration.

The states of the main input of the circuit are only 1 and 0, and the whale optimization algorithm is proposed to solve the problem of continuous search space, so it cannot directly handle binary problems. In order to solve the application of the whale optimization algorithm in binary discrete problems, Abdelazim G. Hussien adapted the original whale optimization algorithm and proposed two transfer functions (S-shaped and V-shaped, as shown in Figure 5) to map the continuous search space to the binary search space [37]. First, use the S function of Formula (1) or the V function of Formula (2) to compress the values in the continuous space into [0, 1].

$$\mathrm{S}\left({\mathrm{x}}_{\mathrm{i}}^{\mathrm{k}}\left(\mathrm{t}\right)\right)={\displaystyle \frac{1}{1+{\mathrm{e}}^{-{\mathrm{d}}_{\mathrm{i}}^{\mathrm{k}}\left(\mathrm{t}\right)}}}$$

(1)

$$\mathrm{V}\left({\mathrm{x}}_{\mathrm{i}}^{\mathrm{k}}\left(\mathrm{t}\right)\right)=\left|\tanh {(\mathrm{x}}_{\mathrm{i}}^{\mathrm{k}}\left(\mathrm{t}\right)\right)|$$

(2)

where ${\mathrm{d}}_{\mathrm{i}}^{\mathrm{k}}\left(\mathrm{t}\right)$ represents the distance between particles.

After compression, the steps of the original whale algorithm are performed. The position of each individual is changed, and a new solution is generated. The new solution is mapped into the binary space by applying the threshold according to the compression function selected from Formula (3) or Formula (4).

$$x_i^k\left(t+1\right)=\left\{\begin{array}{l}0 if rand<S\left(x_i^k\left(t\right)\right)\\ 1 otherwise\end{array}\right.$$

(3)

$$x_i^k\left(t+1\right)=\left\{\begin{array}{l}{\left(x_i^k\left(t\right)\right)}^{-1} if rand<V\left(x_i^k\left(t\right)\right)\\ x_i^k\left(t\right) otherwise\end{array}\right.$$

(4)

where $x_i^k\left(t\right)$ and $x_i^k\left(t+1\right)$ represent the position of the i-th individual at a specific iteration and ${\left(x_i^k\left(t\right)\right)}^{-1}$ dimension is the complement of $x_i^k\left(t\right)$, and rand is a random value taken during the mapping process.

In the process of the PODEM, after generating an “incompletely assigned” vector for a fault in the fault list, the number of individuals in the whale population is set to 15. According to the original whale optimization algorithm, the irrelevant bits are first randomly assigned, and the value of the system timer/counter is used to set the random seed so that the seed changes over time, ensuring that the assignment of each irrelevant bit is generated by a different seed, increasing the randomness between random numbers, and generating random numbers from 0 to 100 to determine whether they are greater than 50 to achieve bit-by-bit random generation of the required vector length 0/1. After each iteration, the remaining faults to be tested are simulated in parallel, and the number of activated faults to be tested is counted as the fitness value of each iteration. If the test vector set does not contain the optimal solution of this iteration, the optimal solution is added to the test vector set and the fault detected by the vector is deleted from the fault set. In order to ensure a good iteration, a sufficient number of iterations can ensure that a better position is found, but too many iterations will consume a long CPU time. This paper sets the number of iterations of the compression process of each “incompletely assigned” vector to 10 to reduce CPU time. The dynamic compression process based on discrete whale optimization is shown in Figure 6. The detailed procedure of dynamic test vector compression using discrete Whale Optimization is presented in Algorithm B.

Algorithm B Dynamic compression process of discrete whale optimization

1:    V_set ← ∅     // Initialize empty test vector set 2:    for each fault f ∈ F do 3:           if PODEM(C, f) returns a partially assigned vector then 4:                 Obtain partially assigned vector V_unspecified and identify don’t-care bits 5:                 // Time-perturbed random initialization of population 6.                 for i = 1 to N_max do 7:                      Randomly fill don’t-care bits (time-varying seed) 8:                      Generate individual X_i 9:                 end for 10:               t ← 0 11:               while t < T_max do 12:                     Evaluate fitness f_i for each X_i via parallel fault simulation 13:                     X_best ← arg max_i f_i // Best individual 14:                     if X_best ∉ V_set then 15:                           V_set ← V_set ∪ {X_best} 16:                           Remove faults detected by X_best from F 17:                     end if 18:                     Update whale positions according to standard WOA rules 19:                     for each bit k of Xi do 20:                           if $\mathrm{S}\left({\mathrm{x}}_{\mathrm{i}}^{\mathrm{k}}\left(\mathrm{t}\right)\right)={\displaystyle \frac{1}{1+{\mathrm{e}}^{-{\mathrm{d}}_{\mathrm{i}}^{\mathrm{k}}\left(\mathrm{t}\right)}}}$ then 21:                                 $x_i^k\left(t+1\right)=\left\{\begin{array}{l}0 if rand<S\left(x_i^k\left(t\right)\right)\\ 1 otherwise\end{array}\right.$ 22:                                     else 23:                                                if $\mathrm{V}\left({\mathrm{x}}_{\mathrm{i}}^{\mathrm{k}}\left(\mathrm{t}\right)\right)=\left|\tanh {(\mathrm{x}}_{\mathrm{i}}^{\mathrm{k}}\left(\mathrm{t}\right)\right)|$ then 24:                                                         $x_i^k\left(t+1\right)=\left\{\begin{array}{l}{\left(x_i^k\left(t\right)\right)}^{-1} if rand<V\left(x_i^k\left(t\right)\right)\\ x_i^k\left(t\right) otherwise\end{array}\right.$ 25:                                                end if 26:                           end if 27:                     end for 28:                     t ← t + 1 29:               end while 30:         end if 31:   end for 32:   return V_set

3. Experimental Results and Analysis

The application of ATPG to high-speed rail equipment requires the design of a corresponding golden model, which is used to obtain the circuit netlist after synthesis. This paper designs the two-by-two redundant architecture and the integrated track circuit, signal machine and switch interlocking logic in the high-speed rail TYJL-III (G)-type track circuit, respectively, realizing the switching of output modules when a fault occurs and the route establishment and route unlocking functions when simulating trains entering and leaving the station. The two-by-two redundant architecture is shown in Figure 7. The safety level of the logic processing host of the TYJL-III (G)-type computer interlocking system is SIL4, so a 2-by-2-out-of-2 (2oo2x2) safety computer platform is used to implement the logic operation function.

As one of the key pieces of technical equipment that ensures the safe operation of trains and trains in stations, the station interlocking system realizes the mutual control between station switches, signal machines and track circuits to ensure the safe operation of trains [38]. Route control is divided into route establishment and route unlocking. According to the requirements of the TBT3027-2015 Railway Station Computer Interlocking Technical Conditions, the station computer interlocking model for trains entering, leaving and passing is established as shown in Figure 8.

First, the designed golden model netlist is used for vector generation, and the algorithm can achieve 100% fault coverage. The small-scale circuit c432 (logic gate number 249), medium-scale circuit c1355 (logic gate number 805) and larger-scale c2670 (logic gate number 1647), c3540 (logic gate number 2248), c5315 (logic gate number 3113) and c7552 (logic gate number 4812) circuits in the ISCAS-85 standard circuit are tested, respectively. When each circuit tests the same fault list, the improved PODEM vector generation (Algorithm 1) and time-varying pseudo-randomization combined with the improved PODEM (Algorithm 2) and the improved PODEM (Algorithm 3) proposed in this paper after whale optimization dynamic compression are compared. The number of logic gates of each circuit, the fault coverage of each algorithm, the CPU time and the number of vectors in the test vector set are shown in

Table 3. Comparison of the results generated by each algorithm.

Circuit Name	Number of Logic Gates	Algorithm Number	Fault Coverage (%)	CPU Time (S)	Number of Test Vectors
c432	249	1	92	1.422	92
		2	97	10.266	48
		3	97	4.688	20
c1355	805	1	64	62.562	64
		2	88	76.458	25
		3	89	26.156	23
c2670	1647	1	91	34.688	91
		2	94	395.167	51
		3	96	21.953	24
c3540	2248	1	78	82.500	78
		2	88	643.156	46
		3	90	32.766	26
c5315	3113	1	95	83.047	95
		2	98	1565.212	35
		3	99	21.547	21
c7552	4812	1	84	457.165	84
		2	91	2191.609	38
		3	94	198.25	25

.

The fault coverage, CPU time and length of the generated test vector set of the three algorithms for each circuit are shown in Figure 9, Figure 10 and Figure 11, respectively.

It can be seen from the generated results that when testing the same fault list, compared with using the improved PODEM alone and the improved PODEM algorithm combined with time-varying pseudo-randomness, the algorithm proposed in this paper has the highest fault coverage rate in medium and large circuits. The CPU time required for operation is reduced by more than 35% and 65%,, respectively, and the length of the generated test vector set is reduced by more than 60% and 30% respectively. The algorithm efficiency is significantly improved. It was also found in the experiment that when the circuit scale is small, circuit c432 as shown in Figure 10 requires more CPU time to apply the algorithm proposed in this article than using the improved PODEM algorithm alone. Circuit c1355 as shown in Figure 11 applies the algorithm of this article to test the vector length and There is no significant reduction compared to Algorithm 2, but based on the three indicators shown in the figure above, c432 reduces the length of the test vector set generated by using the improved PODEM algorithm alone by 78% at the expense of a small increase in CPU time required for testing. C1355 applies the algorithm proposed in this article to reduce the CPU time required for testing by 65% compared to applying time-varying pseudo-random combined with the improved PODEM algorithm. Therefore, comprehensively examining various indicators, the algorithm proposed in this article is better than using the improved PODEM algorithm and time-varying pseudo-randomly alone. Randomly combine improved PODEM algorithm.

4. Discussion

This study addresses the fundamental challenges in test vector generation for safety-critical high-speed railway signaling systems, particularly the excessive CPU time, large test vector volume, and backtracking overhead associated with traditional deterministic ATPG methods when applied to complex interlocking logic circuits. The proposed whale-optimized dynamic compression ATPG algorithm effectively mitigates these issues by integrating a discrete WOA with an enhanced multi-path sensitized PODEM framework and desensitization techniques, enabling dynamic compression during vector generation.

The experimental results confirm the method’s effectiveness. On the Verilog-designed golden model netlist of the TYJL-III (G) computer interlocking equipment—leveraging its two-by-two redundant architecture and focusing on signal machine and turnout interlocking logic—the algorithm achieves 100% fault coverage, ensuring comprehensive detection of all targeted faults in this safety-critical application. Benchmarking on ISCAS-85 circuits (c432, c1355, c2670, c3540, c5315, and c7552) further demonstrates scalability: when testing identical fault lists, the proposed method (Algorithm 3) reduces CPU execution time by more than 35% compared to improved PODEM alone (Algorithm 1) and over 65% compared to the time-varying pseudo-random hybrid (Algorithm 2), while simultaneously reducing test vector set length by over 60% and 30%, respectively. These gains are most pronounced in the medium- and large-scale circuits, where the global search capability of WOA efficiently optimizes don’t-care bit assignments and minimizes redundant vectors without compromising fault detection.

However, the results also reveal scale-dependent trade-offs. In small-scale circuits (e.g., c432), the overhead of WOA population initialization and iterative optimization slightly increases CPU time compared to pure deterministic PODEM, although a 78% reduction in vector length is achieved. For c1355, CPU time decreases significantly relative to the pseudo-random hybrid, but vector length reduction is less pronounced. This indicates that the proposed method is particularly advantageous for circuits of realistic complexity in railway interlocking systems, whereas conventional PODEM may suffice for very small modules.

In addition to CPU time, energy consumption and resource usage are relevant considerations, especially in large-scale computational environments or resource-constrained testing platforms typical of railway signaling verification. While the proposed method significantly reduces CPU execution time for medium- and large-scale circuits, the population-based nature of WOA introduces additional memory usage and potential energy overhead during iterative fitness evaluations via parallel fault simulation. In our experiments, memory consumption remained within acceptable limits, but energy expenditure could increase modestly in small-scale cases due to the fixed iteration overhead. For real-world deployment on embedded or edge devices in HSR testing systems, future optimizations could focus on adaptive population sizing or early termination criteria to balance energy efficiency with performance gains.

Regarding the selection of optimization algorithms for test vector formation and compression, WOA was chosen over other metaheuristics due to its simplicity (minimal parameters), fast convergence, and superior performance in generating compact test suites under high-interaction constraints, as demonstrated in recent combinatorial and t-way testing studies. Alternative methods, such as Cochran’s Q-test-based optimization (commonly used in statistical design-of-experiments for parameter selection and variance analysis), could offer value in adaptive parameter tuning or multi-factor evaluation of ATPG settings. However, Cochran’s approach is primarily statistical and better suited to continuous or experimental design problems, whereas the discrete, high-dimensional binary decision spaces in ATPG favor WOA’s bubble-net mechanism for the effective exploration of don’t-care bit configurations and avoidance of premature convergence. Compared to GA (slow convergence) or PSO (local optima trapping risk), WOA provides a more balanced and efficient search, aligning closely with the dynamic compression objective in this work.

Despite these advantages, limitations remain. The fixed population size and iteration limits may require circuit-specific tuning, potentially introducing variability in resource-constrained or real-time testing scenarios. The method’s performance on sequential or transition faults has not yet been fully evaluated.

This study adopts a single-objective optimization framework in which fault coverage is treated as a primary constraint, while test vector length and CPU time are minimized under this constraint. Such a formulation is appropriate for safety-critical railway signaling systems, where complete fault detection cannot be compromised. Nevertheless, multi-objective optimization may be explored in future work to explicitly model trade-offs between vector length and computational cost [39]. In that context, Pareto-front analysis could be employed to visualize the distribution and sparsity of feasible solutions, providing deeper insight into the solution diversity and convergence characteristics of the proposed algorithm.

The current framework integrates global search capability from discrete WOA, dynamic compression mechanisms compatible with test vector generation, and accelerated backtracking enabled by desensitization techniques. This combination establishes a coherent and efficient optimization structure tailored to structural ATPG in safety-critical applications.

Future research may further enhance this framework through hybrid strategies, such as combining WOA with SAT-based compaction for hard-to-detect faults, incorporating reinforcement learning for adaptive population control, or applying statistical methods for systematic parameter tuning across diverse circuit types. Additional validation on industrial-scale railway interlocking netlists, the integration of energy-aware metrics, and deployment within commercial ATPG environments would further evaluate its practical applicability in high-speed railway systems.

5. Conclusions

In order to reduce the time required for testing high-speed rail-related equipment systems and to minimize the length of test vector sets, this paper proposes a whale-optimized dynamic compression Automatic Test-Pattern Generation (ATPG) algorithm. Additionally, it introduces an improved multi-path sensitized PODEM enhanced by a desensitization technique, as well as a vector dynamic compression method based on the discrete whale optimization algorithm. Firstly, leveraging the two-by-two redundant architecture in the TYJL-III (G) track circuit and the unified track circuit—specifically focusing on signal machine and turnout interlocking logic—the golden model of the circuit is designed using Verilog. The test vectors generated for this golden model achieve a fault coverage rate of 100%. Performance evaluation of various international standard circuits such as c432, c1355, c2670, c3540, c5315, and c7552 from ISCAS-85 was conducted using standardized ATPG algorithms. When testing identical fault lists across each circuit individually, it was observed that CPU operation time decreased by more than 35% and 65%, respectively. Furthermore, there was a reduction in the length of the generated test vector sets by over 60% and 30%, respectively. This approach effectively integrates the global optimization capabilities of discrete whale optimization methods with the compression-compatible vector functions inherent in dynamic compression techniques. Moreover, it incorporates an accelerated backtracking function derived from desensitization algorithms. This comprehensive methodology can be optimally utilized for subsequent testing and verification processes concerning safety equipment within high-speed rail signal systems.