Search Results (36)

Background: We present a miniature (30 × 34 mm) 64-channel data acquisition headstage optimized for high-density surface electromyography. Methods: The headstage is made up of a multi-channel ASIC analogue front-end utilizing only MOS transistors, fabricated in 350 nm CMOS technology (IC die dimensions 6.9 × 1.8 mm), combined with an off-the-shelf multi-channel current-input ADC (DDC264, Texas Instruments). The ASIC analogue front-end employs MOS-based capacitors for both processing and AC-coupling. Results: The combination of these two sub-circuits enables the simultaneous recording of 64 channels at a typical sampling rate of 4 KHz with a maximum analogue bandwidth of 0.5–1500 Hz and a resolution of 20-bits. Typical input-referred-noise, determined by the analogue front-end, is 3.5 μV_RMS for a surface EMG bandwidth of interest of 20–500 Hz. This two-chip solution results in a power consumption of 5 mW per channel. Analogue performance variability of the custom ASIC was characterized across a dataset of 960-channels (15 dies) from two fabrication runs. Conclusions: This work practically demonstrates the viability of using both a MOS-only analogue front-end and commercially available off-shelf high-performance back-end hardware already developed for medical imaging applications to record high-density surface biosignals. The aforementioned techniques can be employed to reduce the size and cost for systems or wearable devices; facilitating the translation of high-density bio-acquisition setups from the research environment to more affordable commercial products. Full article

Hyperspectral images (HSIs) and Light Detection and Ranging (LiDAR) data offer complementary spectral and spatial information and are extensively applied to land cover classification. Nevertheless, current fusion–classification approaches frequently suffer from cross-modal feature entanglement and insufficient exploitation of LiDAR physical priors, particularly the Digital Surface Model (DSM), which limits the interpretability of learned features and restricts classification accuracy. To address these issues, this study presents a Physics-Guided Adaptive Decoupling and Collaborative Enhancement Network (ADCE-Net) that embeds explicit geometric guidance into multimodal feature learning. In ADCE-Net, the DSM serves as an explicit geometric conditioning signal to guide feature decoupling, decomposing input representations into modality-shared semantic features (SSF) and modality-specific discriminative features (MSF), thereby mitigating cross-modal interference at an early stage. Based on this decomposition, an adaptive collaborative enhancement mechanism is designed using bidirectional cross-attention and dynamic gating to achieve context-aware mutual refinement between SSF and MSF, facilitating more effective utilization of cross-modal complementary information. Furthermore, a multi-level collaborative classification architecture is constructed to integrate multi-scale contextual representations, enhancing spatial consistency and boundary delineation. Extensive experiments on three benchmark datasets—Trento, Houston 2013, and Muufl Gulfport—demonstrate that ADCE-Net achieves overall accuracies of 99.69%, 97.37%, and 94.90%, respectively, surpassing multiple representative methods including support vector machines, 3D convolutional neural networks, transformer-based models, and recurrent neural networks. Noticeable improvements are also achieved for minority classes and classes with highly similar spectral signatures. The DSM-driven physics guidance boosts both classification performance and feature interpretability, providing a reliable and explainable paradigm for multimodal remote sensing classification. Full article

In the last few years, Thin Film Transistors (TFTs) based on materials such as amorphous Indium–Gallium–Zinc Oxide (a-IGZO) have gained interest in large-area and low-cost electronics due to their high carrier mobility, high on/off current ratio, low off-state current, and steep subthreshold slope. These characteristics make IGZO TFTs suitable for radio-frequency identification (RFID) tags, analog-to-digital converters (ADCs), logic circuits, sensors, and analog components, including operational amplifiers (OPAMPs). This work presents the implementation and characterization of an OPAMP based on n-type a-IGZO TFTs fabricated on glass substrate. Two previously reported design strategies were integrated: a positive feedback network to increase the output impedance and a topology to enhance the transconductance of the driver transistors, both in the differential input stage. A gain of 26 dB, a bandwidth of 2.4 kHz, a gain–bandwidth product (GBWP) of 48 kHz, and a phase margin of 64° were obtained, which confirms the reliability of the design and the fabrication process. Full article

For the application of a high-performance shortwave infrared (SWIR) detector, a fully integrated analog front-end (AFE) circuit is proposed in this paper, which includes a readout integrated circuit (ROIC) and a 12-bit/100 kHz two-step single-slope analog-to-digital converter (TS-SS ADC). The ROIC adopts a direct injection (DI) structure with a pixel size of only 10 µm × 10 µm. The column processing circuit uses a passive correlated double-sampling (CDS) circuit to reduce noise and improve dynamic range. The comparator of four inputs in the ADC solves the problem of linearity reduction caused by charge redistribution during coarse quantization. In addition, the current steering digital-to-analog converter (DAC) is used to compensate for the non-ideal characteristics of the switch, which effectively optimizes the differential nonlinearity (DNL) and integral nonlinearity (INL). The AFE is implemented using SMIC 180 nm 1P6M technology. The post-simulation results show that at a power supply voltage of 3.3 V, the AFE has a frame rate of 100 Hz and a full well capacity (FWC) of 2.8 Me⁻. The linearity can reach 99.59%, and the equivalent output noise is 243 µV. The dynamic range is 73.8 dB. Meanwhile, the signal-to-noise distortion ratio (SNDR) and effective number of bits (ENOB) are 68.38 dB and 11.06 bits, respectively. Full article

This paper presents a microcontroller-based technique for accurately measuring resistive sensors over a wide dynamic range using an adaptive constant current source. Unlike conventional voltage dividers or fixed-current methods—often limited by reduced resolution and saturation when sensor resistance varies across several decades—the proposed system dynamically adjusts the excitation current to maintain optimal Analog-to-Digital Converter (ADC) input conditions. The measurement circuit employs a fixed reference resistor and an inverting amplifier configuration, where the excitation current is generated by one or more pulse-width modulated (PWM) signals filtered through low-pass RC networks. A microcontroller selects the appropriate PWM channel to ensure that the output voltage remains within the ADC’s linear range. To support multiple sensors, an analog switch enables sequential measurements using the same dual-PWM current source. The full experimental implementation uses four op-amps to support modularity, buffering, and dual-range operation. Experimental results show accurate measurement of resistances from 1 kΩ to 100 kΩ, with maximum relative errors of 0.15% in the 1–10 kΩ range and 0.33% in the 10–100 kΩ range. The method provides a low-cost, scalable, and digitally controlled solution suitable for embedded resistive sensing applications without the need for high-resolution ADCs or programmable gain amplifiers. Full article

This paper proposes a dual-mode CMOS analog front-end (AFE) circuit for short-wave infrared (SWIR) image sensors, which integrates a hybrid readout circuit (ROIC) and a 12-bit two-step single-slope analog-to-digital converter (TS-SS ADC). The ROIC dynamically switches between buffered-direct-injection (BDI) and direct-injection (DI) modes, thus balancing injection efficiency against power consumption. While the DI structure offers simplicity and low power, it suffers from unstable biasing and reduced injection efficiency under high background currents. Conversely, the BDI structure enhances injection efficiency and bias stability via an input buffer but incurs higher power consumption. To address this trade-off, a dual-mode injection architecture with mode-switching transistors is implemented. Mode selection is executed in-pixel via a low-leakage transmission gate and coordinated by the column timing controller, enabling low-current pixels to operate in low-noise BDI mode, whereas high-current pixels revert to the low-power DI mode. The TS-SS ADC employs a four-terminal comparator and dynamic reference voltage compensation to mitigate charge leakage and offset, which improves signal-to-noise ratio (SNR) and linearity. The prototype occupies 2.1 mm × 2.88 mm in a 0.18 µm CMOS process and serves a 64 × 64 array. The AFE achieves a dynamic range of 75.58 dB, noise of 249.42 μV, and 81.04 mW power consumption. Full article

This paper presents a prototype open-loop pipelined stage in a 45 nm CMOS process for supporting 1.8 GS/s and 10-bit design specifications of pipelined ADCs. In order to alleviate the severe non-linearity expressed by open-loop MDACs, an innovative current-mode harmonic compensation is proposed to provide input related third harmonic terms to cancel non-linearity. In addition, an effective double-sampling scheme is optimized by modifying compensation timing and input of a residual amplifier so that the pipelined stage can be immune to memory effect and improve power efficiency. The memory effect compensation scheme can provide a 21 dB improvement on output SNDR of the double-sampling pipelined stage. The simulation results illustrate that the open-loop pipelined ADC stage achieves an output SNDR of at least 52 dB with 840 mV input amplitude and 240 fF load while consuming only 11.24 mW. Full article

Grouting technology is widely used in construction and civil engineering, where evaluating grouting effectiveness is crucial due to the uncertainty of subsurface conditions. Existing methods face drawbacks such as destructiveness, high cost, poor durability, and limited data collection. To address these issues, this paper proposes a novel wireless real-time monitoring system based on a ZigBee sensor network framework. The sensor system integrates a direct current method in geophysics with apparent resistivity measurement to assess grouting effectiveness in real time. It consists of multichannel data acquisition units with electrodes for sensing underground currents and a user control unit for centralized management and data processing. A system acquisition performance test confirmed that the differential input channel’s equivalent input noise of the ADC was only 175 μV and 188 μV, and the average error of the captured sine wave data was 4.51 mV and 4.19 mV, ensuring the voltage measurement accuracy of the data acquisition units. Stability testing of the equipment in road and construction environments showed an average RSD of 2.86% and 2.92%, respectively, indicating good stability of the measurements. ZigBee network performance tests in three simulated environments and a field test showed that the packet loss rate (PLR) was less than 2% from 0 to 50 m, ensuring network communication in grouting project scenarios. On-site experiments demonstrate that the system can simultaneously monitor multiple profiles and perform inversions in the grouting area, which can be assembled into 3D inversion images for evaluating grout diffusion, offering valuable insights for optimizing construction operations, and enhancing grouting efficiency. Full article

Low-pass filters with bandwidths larger than several GHz are required in many applications, such as anti-aliasing filters in high-speed ADCs and pulse-shaping filters in high-speed DACs. In highly integrated applications, low area occupation and power consumption are key specifications, so inductor-less implementations are to be preferred. Furthermore, full CMOS implementations provide an advantage in terms of technology availability and cost. In this paper, we present an inductor-less CMOS biquad stage based on the super source follower topology that provides an 8 GHz cutoff frequency and a low power consumption of 0.42 mW per pole, showing remarkable performance also in terms of bandwidth and dynamic range. The availability of two separate current sources allows independent tuning of natural frequency and quality factor. The stage can be implemented in two complementary ways, exploiting NMOS and PMOS input devices, respectively, thus simplifying cascadability. The two complementary biquads have been implemented in the STMicroelectronics FDSOI 28 nm CMOS process and extensively simulated and provide stable performance under PVT variations and mismatches. The area occupation is about 387.5 μm² per biquad, one of the lowest in the literature. The figures-of-merit are remarkable, as the filters achieve excellent power efficiency, very low area occupation, and good dynamic range. Full article

This paper presents a low-power photoplethysmography (PPG) readout system designed for wearable health monitoring. The system employs a differential current mirror (DCM) to convert single-ended PPG currents into differential voltages, inherently suppressing DC components. A wide common-mode input range (WCMIR) SAR ADC processes the differential signals, ensuring accurate analog-to-digital conversion. The DCM eliminates the need for DC cancelation loops, simplifying the design and reducing power consumption. Implemented in a 0.18 µm CMOS process, the system occupies only 0.30 mm², making it suitable for multi-channel applications. The system achieves over 60 dB DC dynamic range and consumes only 9.6 µW, demonstrating its efficiency for portable devices. The simulation results validate its ability to process PPG signals across various conditions, offering a scalable solution for advanced biomedical sensing platforms. Full article

Carbon nanotube field-effect transistors (CNT-FETs) have shown great promise in infrared image detection due to their high mobility, low cost, and compatibility with silicon-based technologies. This paper presents the design and simulation of a column-level analog front-end (AFE) circuit tailored for carbon-based short-wave infrared (SWIR) photodetectors. The AFE integrates a Capacitor Trans-impedance Amplifier (CTIA) for current-to-voltage conversion, coupled with Correlated Double Sampling (CDS) for noise reduction and operational amplifier offset suppression. A 10-bit/125 kHz Successive Approximation analog-to-digital converter (SAR ADC) completes the signal processing chain, achieving rail-to-rail input/output with minimized component count. Fabricated using 0.18 μm CMOS technology, the AFE demonstrates a high signal-to-noise ratio (SNR) of 59.27 dB and an Effective Number of Bits (ENOB) of 9.35, with a detectable current range from 500 pA to 100.5 nA and a total power consumption of 7.5 mW. These results confirm the suitability of the proposed AFE for high-precision, low-power SWIR detection systems, with potential applications in medical imaging, night vision, and autonomous driving systems. Full article

A 16-channel front-end readout chip for a radiation detector is designed for portable or wearable healthcare monitoring applications. The proposed chip reads the signal of the radiation detector and converts it into digital serial-out data by using a nonbinary successive approximation register (SAR) analog-to-digital converter (ADC) that has a 1-MS/s sampling rate and 10-b resolution. The minimum-to-maximum differential and integral nonlinearity are measured as −0.32 to 0.33 and −0.43 to 0.37 least significant bits, respectively. The signal-to-noise-and-distortion ratio and effective number of bits are 57.41 dB and 9.24 bits, respectively, for an input frequency of 500 kHz and a sampling rate of 1 MS/s. The SAR ADC has a 38.9-fJ/conversion step figure of merit at the sampling rate of 1 MS/s. The proposed chip can read input signals with peak currents ranging from 20 to 750 μA and convert the analog signal into a 10-bit serial-output digital signal. The input dynamic range is 2–75 pC. The resolution of the peak current is 208.3 nA. The chip, which has an area of 1.444 mm × 10.568 mm, is implemented using CMOS 0.18-μm 1P6M technology, and the power consumption of each channel is 19 mW. This design is suitable for wearable devices, especially biomedical devices. Full article

In this paper, we propose a compact and low-power mixed-signal approach to implementing convolutional operators that are often responsible for most of the chip area and power consumption of Convolutional Neural Network (CNN) processing chips. The convolutional operators consist of several multiply-and-accumulate (MAC) units. MAC units are the primary components that process convolutional layers and fully connected layers of CNN models. Analog implementation of MAC units opens a new paradigm for realizing low-power CNN processing chips, benefiting from less power and area consumption. The proposed mixed-signal convolutional operator comprises low-power binary-weighted current steering digital-to-analog conversion (DAC) circuits and accumulation capacitors. Compared with a conventional binary-weighted DAC, the proposed circuit benefits from optimum accuracy, smaller area, and lower power consumption due to its symmetric design. The proposed convolutional operator takes as input a set of 9-bit digital input feature data and weight parameters of the convolutional filter. It then calculates the convolutional filter’s result and accumulates the resulting voltage on capacitors. In addition, the convolutional operator employs a novel charge-sharing technique to process negative MAC results. We propose an analog max-pooling circuit that instantly selects the maximum input voltage. To demonstrate the performance of the proposed mixed-signal convolutional operator, we implemented a CNN processing chip consisting of 3 analog convolutional operators, with each operator processing a 3 × 3 kernel. This chip contains 27 MAC circuits, an analog max-pooling, and an analog-to-digital conversion (ADC) circuit. The mixed-signal CNN processing chip is implemented using a CMOS 55 nm process, which occupies a silicon area of 0.0559 mm² and consumes an average power of 540.6 μW. The proposed mixed-signal CNN processing chip offers an area reduction of 84.21% and an energy reduction of 91.85% compared with a conventional digital CNN processing chip. Moreover, another CNN processing chip is implemented with more analog convolutional operators to demonstrate the operation and structure of an example convolutional layer of a CNN model. Therefore, the proposed analog convolutional operator can be adapted in various CNN models as an alternative to digital counterparts. Full article

This paper proposes a 10-bit 400 MS/s dual-channel time-interleaved (TI) successive approximation register (SAR) analog-to-digital converter (ADC) immune to offset mismatch between channels. A novel comparator multiplexing structure is proposed in our design to mitigate comparator offset mismatch between channels and improve ADC dynamic performance. Compared to traditional TI-SAR ADC utilizing offset calibration technique, hardware and power consumption overhead are minimized in our design. In addition, a split capacitive digital-to-analog converter (CDAC) and a double-tail dynamic comparator using the clock decoupling technique were applied to eliminate comparator common mode input voltage shift, ensuring conversion accuracy and boosting speed. A 400 MS/s 10-bit dual-channel TI-SAR ADC with comparator multiplexing was designed in 40 nm CMOS and compared to the conventional one. The simulated ADC ENOB and SFDR with 6σ offset mismatch were improved from 5.0-bit and 32.2 dB to 9.7-bit and 77.2 dB, respectively, confirming the merits of the proposed design compared to current state-of-the-art works. Full article

The Hyper-Kamiokande is a next-generation neutrinos and nucleon decay experiment. It consists of a huge Water Cherenkov detector and a high-intensity neutrino beam factory with a neutrino near detector complex. We are constructing the detector and planning to start operation in 2027. The photo sensor is one of the key components of the Water Cherenkov detector, and we decided to use large aperture PMTs of $50\mathrm{cm}$ diameter. It is required to prepare suitable digitizer for this particular PMT signal, which has twice as a good performance as those of the current PMTs. They should have sub-ns timing resolution and a wide dynamic range from $𝒪\left(\mathrm{mV}\right)$ to $𝒪\left(\mathrm{V}\right)$. We have developed three designs using different technologies. The first design processes the input signal in a pipeline of charge-to-time conversion and time-to-digital conversion. The second digitizes the input signal with flash-ADC. The third one uses the discrete components of discriminator and sampling ADC to record the timing and the charge of the input signal. Through a detailed evaluation, we have selected the “discrete design” for our readout system. Full article