Radiation Detector Front-End Readout Chip with Nonbinary Successive Approximation Register Analog-to-Digital Converter for Wearable Healthcare Monitoring Applications

Abstract

A 16-channel front-end readout chip for a radiation detector is designed for portable or wearable healthcare monitoring applications. The proposed chip reads the signal of the radiation detector and converts it into digital serial-out data by using a nonbinary successive approximation register (SAR) analog-to-digital converter (ADC) that has a 1-MS/s sampling rate and 10-b resolution. The minimum-to-maximum differential and integral nonlinearity are measured as −0.32 to 0.33 and −0.43 to 0.37 least significant bits, respectively. The signal-to-noise-and-distortion ratio and effective number of bits are 57.41 dB and 9.24 bits, respectively, for an input frequency of 500 kHz and a sampling rate of 1 MS/s. The SAR ADC has a 38.9-fJ/conversion step figure of merit at the sampling rate of 1 MS/s. The proposed chip can read input signals with peak currents ranging from 20 to 750 μA and convert the analog signal into a 10-bit serial-output digital signal. The input dynamic range is 2–75 pC. The resolution of the peak current is 208.3 nA. The chip, which has an area of 1.444 mm × 10.568 mm, is implemented using CMOS 0.18-μm 1P6M technology, and the power consumption of each channel is 19 mW. This design is suitable for wearable devices, especially biomedical devices.

1. Introduction

As integrated chip technology has developed, many large and costly machines have become smaller and less expensive. In the biomedical field, progressive wireless technology and modalities such as electroencephalography [1], electrocardiography [2,3,4,5,6], and magnetic resonance imaging [7] are being integrated into wireless body sensor networks [5,6,8]. Wearable devices are becoming even smaller because digital signal processors and data storage can be outsourced to external devices. Technological developments are leading to considerable benefits in terms of wearable healthcare monitoring.

The use of radiation detector devices in medicine [9,10] is limited by the large size of these devices. Integrated chip technology offers a means of scaling down instruments, and smaller radiation detector devices would have a greater scope of application. Communication within the Internet of Things (IoT) is convenient and rapid, and integrated chip technology enables the use of radiation detector devices in wearable healthcare monitoring and the IoT [11,12,13,14]. The conversion blocks that have been employed to convert analog signals to digital signals are analog-to-digital converters (ADCs) [11,12,13], digital delay-locked loop circuits [14], and time-to-digital converters [15].

In designing wearable healthcare monitoring applications, the objectives are a sampling rate of several megasamples per second and low power consumption.

Pipeline ADCs have high speed, with high sampling rates (~100 MS/s), medium resolution (8–12 b), and high power consumption (dozens of milliwatts). Delta-sigma ADCs have low speed, with sampling rates in the dozens of kilosamples per second, high resolution (12–20 b), and moderate power consumption (several milliwatts). SAR ADCs have medium speed, with sampling rates of several megasamples per second, moderate resolution (8–12 b), and low power consumption (dozens of microwatts). SAR ADCs are thus more suitable than pipelined ADCs or delta-sigma ADCs for wearable healthcare monitoring applications.

This study proposes a front-end readout circuit for a radiation detector; this circuit contains a nonbinary successive approximation register (SAR) ADC [16]. In radiation applications, a particle can cause bit flips in digital circuits and voltage spikes in analog circuits. These flips and spikes can be considered a noise effect. Because of its nonbinary structure, the SAR ADC has a correction mechanism that can minimize the effect of the digital-to-analog converter (DAC), settling incomplete errors and the effects of noise from the DAC and comparator [17]. The results of simulations are depicted in Figure 1 and Figure 2. Figure 1 presents a comparison of the effective number of bits (ENOB) for a binary SAR ADC versus a nonbinary SAR ADC when some noise is present in the comparator input. The ENOB of the nonbinary SAR ADC is 0.17 b higher than that of the binary SAR ADC with an 8-least-significant-bit (LSB) noise effect. Figure 2 presents a comparison of the ENOB for binary and nonbinary SAR ADCs for various settling ratios. The settling ratio means that the ratio of DAC voltage settles to the correct value. The ENOB of the nonbinary SAR is still 9 b when the DAC settling ratio is 80%. The ENOB of the binary SAR ADC is 9 b at a settling ratio of 97.5%, whereas at an 80% settling ratio, it is only 5.12 b.

Figure 3 and Figure 4 present the results of Matlab simulations quantifying the performance of a radiation detection front-end circuit using a nonbinary SAR ADC versus that using a binary SAR ADC. The ideal conversion code count in this simulation is 552, and the result for the binary SAR ADC case is a 1-LSB error, even when the noise effect is only at 0.25 LSB. Conversely, for the nonbinary SAR ADC case, correct conversion results are obtained with up to a 1.5-LSB noise effect. With up to a 7.5-LSB noise effect, the conversion errors for the binary and nonbinary SAR ADCs are 10 and 2 LSB, respectively. With incomplete DAC settling, no conversion errors are found to occur for the binary and nonbinary SAR ADC cases until the settling ratios of 87.5% and 83.8%, respectively, are reached. For the binary SAR ADC case, a 1-LSB conversion error occurs until a settling ratio of 72% is reached, at which point the error increases to an 11-LSB conversion error. By contrast, the nonbinary SAR ADC continues to have a conversion error of only 1 LSB.

Because most applications of radiation detector front-end readout chips require multiple channels, the chip proposed in the present study is a 16-channel front-end readout chip. The use of multiple channels causes a cross-talk effect and reduces the accuracy of an SAR ADC. The cross-talk signal is noise to the SAR ADC, and the SAR ADC thus requires a correction mechanism to reduce the effect of this noise. Section 2 of this paper describes the block diagram of the proposed chip. Section 3 describes how the chip is implemented. Section 4 discusses the chip’s performance in tests. Finally, Section 5 concludes the paper.

2. Proposed Structure

The block diagram of a 16-channel front-end readout circuit for a radiation detector is depicted in Figure 5. The circuit comprises an amplifier, a trigger generator, an integrator, an ADC, a reset signal generator (RSG), a parallel-in serial-out shifter register (PSSR), and a bias circuit. When the radiation detector responds to radiation, a current signal is generated and sent to the amplifier. The amplifier converts the current signal into a voltage signal and transfers this signal to the trigger generator and integrator. The integrator then begins integration, and simultaneously, the ADC begins tracking the integrator’s output signal. The trigger generator is a differential difference comparator and thus has two differential inputs and a single output. The trigger signal is high when the input signal is higher than the reference voltage and low otherwise. When the radiation detector turns off, the trigger generator’s output signal ceases. The ADC then stops its signal tracking and conversion. After it has converted an analog signal, the ADC transfers the parallel digital data to the PSSR and sends a reset signal to the RSG. The RSG resets the integrator after turning off the signal of the trigger generator and the reset signal of the ADC. The amplifier, trigger generator, ADC, and RSG enter into sleep mode until the radiation detector responds again. A flowchart of this process is depicted in Figure 6. The input signal’s CLK periodically controls the PSSR’s renewal of parallel-in digital data from the ADC and transferal of serial-out data, a serial-out clock, and a sampling clock. The sampling clock is the time at which parallel-in digital data should be renewed, whereas the serial-out clock is the time at which serial digital data are read out. Each serial-out datum follows each trigger signal.

The integrator comprises an amplifier, an input resistor, and multiple-integrated-slope switched capacitors. The multiple integrated slopes of these switched capacitors are changed by switches S₁ and S₂. The original integrated slope works with one capacitor when the control signals s₁ and s₂ are low. The integrated slope works with two capacitors when the control signals s₁ and s₂ are high and low, respectively. When the control signals s₁ and s₂ are respectively low and high or are both high, the integrated slope works with three or four capacitors. The multiple integrated slopes can cover a substantial input-signal-to-digital-output conversion range and thus support numerous applications.

A 4-bit binary SAR ADC with a split capacitor DAC [18] is depicted in Figure 7. The power efficiency of the SAR ADC with split capacitor technology is greater than that of a conventional SAR ADC. The capacitors in a conventional 4-bit SAR ADC are denoted C₂, C₁, C₀, and C_D, and the weighted sizes are 8, 4, 2, and 2. By contrast, in the SAR ADC with split capacitor technology, the DAC structure contains C₂ and C_2b instead of C₂, C₁ and C_1b instead of C₁, and C₀ and C_0b instead of C₀. The normal conversion process of a binary SAR ADC with split capacitors is depicted in Figure 8a, and the conversion process with most significant bit (MSB) error decisions is illustrated in Figure 8b. The digital outputs of the 4-bit binary SAR ADC with split capacitors are b₃, b₂, b₁, and b₀, and the mapping code weights are 8, 4, 2, and 1, respectively. Thus, the digital result is 8 × b₃ + 4 × b₂ + 2 × b₁ + 1 × b₀. The correction results of conversion—b₃, b₂, b₁, and b₀—are 1, 0, 0, and 1, respectively, leading to a calculation result of 9. If an MSB error decision occurs, however, the conversion results are 0, 1, 1, and 1, and the calculation result is 7. The MSB error decision causes an incorrect conversion result.

A 4-bit nonbinary SAR ADC with split capacitors is depicted in Figure 9. The DAC structure splits two redundant capacitors, C₃ and C_3b, to obtain more redundancy code for error correction. The capacitors of the 4-bit nonbinary SAR ADC with split capacitors are C₃, C_3b, C₂, C_2b, C₁, C_1b, C₀, C_0b, and C_D, and their respective weight sizes are 3, 3, 2, 2, 1, 1, 1, 1, and 2. The digital outputs of the 4-bit nonbinary SAR ADC with split capacitors are b₄, b₃, b₂, b₁, and b₀, and the respective mapping code weights are 6, 4, 2, 2, and 1. Thus, the digital result is 6 × b₄ + 4 × b₃ + 2 × b₂ + 2 × b₁ + 1 × b₀. The redundant code weight of b₄ is the summation of the other code weights minus the code weight of b₄ (4 + 2 + 2 + 1 + 1 − 6 = 4). The other redundant code weights are 2, 2, and 0 (calculations: 2 + 2 + 1 + 1 − 2 = 2; 2 + 1 + 1 − 2 = 2; and 1 + 1 − 2 = 0). Because the binary SAR ADC with split capacitors has no redundant capacitors, it has no redundant code weights. The normal conversion process of a 4-bit nonbinary SAR ADC with split capacitors is depicted in Figure 10a. The correction conversion results are 1, 0, 1, 0, and 1, and the calculation result is 9. The conversion process of a 4-bit nonbinary SAR ADC with split capacitors and MSB error decisions is presented in Figure 10b. The conversion results are 0, 1, 1, 1, and 1, and the calculation result is 9. The MSB error decision can be corrected with redundant code weights.

The code weights and redundant code weights of 10-bit binary and nonbinary SAR ADCs are listed in

Table 1. Bit weights of binary and nonbinary SAR ADCs.

Bit	Binary Code Weight	Redundant Code Weight	Nonbinary Code Weight	Redundant Code Weight
b11	-	-	404	216
b10	-	-	248	124
b9	512	0	152	68
b8	256	0	88	44
b7	128	0	52	28
b6	64	0	32	16
b5	32	0	20	8
b4	16	0	12	4
b3	8	0	8	0
b2	4	0	4	0
b1	2	0	2	0
b0	1	0	1	0
Dummy	1	0	1	0

. When redundant code weights are larger, more redundant bits must be added in the conversion process. In the case of the 10-bit SAR ADC, adding two redundant bits leads to a 20% gain in redundant code weights available for correcting error decisions. The large values of the redundant code weights listed in Table 1 can guarantee larger error correction ranges. Series capacitor technology is employed in this study to reduce the capacitor array of the DAC, which is depicted in Figure 11. The capacitors C₀ and C_0b comprise two series unit capacitors; this means that the size of the capacitor array in the DAC is halved because the equivalent capacitance of this array with two series unit capacitors is a half-unit capacitor [17,19].

3. Circuit Design and Implementation

This section describes the circuit structure and how each stage of the block diagram is designed and implemented, from the input signal to the first stage to the output signal from the last stage.

3.1. Amplifier

The amplifier, which is the signal-receiving stage in the proposed block diagram, has the circuit structure depicted in Figure 12. It comprises input resistors R_i and R_d, a fully differential amplifier M₁–M₅, and common feedback resistors R₁ and R₂. The current signal is converted into a voltage signal by input resistor R_i, and the voltage signal is amplified by the amplifier. A trade-off is made between the noise contributed by the input resistance and the range over which the received current signal is converted into the voltage signal. When the input resistance is 1 kΩ, it contributes noise of 13 μV_rms when the operating frequency is 10 MHz, as revealed in Equation (1) [20]. Because the converted voltage range for an input current signal of 1 μA to 1 mA is 0.1–1.0 V, the noise contribution of the input resistor can be ignored. In the 16-channel design, the offset between channels must be considered. The large mismatch contribution in the amplifier is the threshold voltage (denoted V_TH) difference between the input pair M₂ and M₃. To ensure that the offset tolerance between each channel is acceptable, 1σ < 0.5 mV_rms, the width and length of the input pair must be sufficiently large, as expressed in Equation (2) [20]. Figure 13 depicts the results of an Hspice Monte Carlo simulation of the amplifier with 1000 samples. The input-referred offset voltage is 0.265 mV_rms, and the input signal has a voltage of 20 mV.

$$\sqrt{\overline{v^2}}=\sqrt{4kTR\Delta f}=\sqrt{1.66\times {10}^{-20}\times 1\times {10}^3\cdot 10\times {10}^6}\approx 13 {\mathsf{\mu }\mathrm{V}}_{\mathrm{rms}}$$

(1)

$$\Delta {\mathrm{V}}_{\mathrm{TH}}=\frac{{\mathrm{A}}_{\mathrm{ATH}}}{\sqrt{\mathrm{WL}}}$$

(2)

3.2. Integrator

The integrator (illustrated in Figure 14) comprises the input resistors R₃ and R₄, which are switched by M₆ and M₇, respectively; a fully differential amplifier M₈–M₁₂; the common feedback resistors R₅ and R₆; the reset switches M₁₃ and M₁₄; and multiple slopes integrated by capacitors C₁–C₆ and switches M₁₅–M₂₀. The integrator integrates when M₆ and M₇ turn on and M₁₃ and M₁₄ turn off, whereas it stops integrating when M₆, M₇, M₁₃, and M₁₄ turn off. Integration is reset when M₆ and M₇ turn off and M₁₃ and M₁₄ turn on. The output voltage of the integrator is integrated by input signal V_IN, switched capacitors C_int, and input resistors R₄ and R₆, as shown in Equation (3). C_int comprises C₁–C₆. The multiple integrated slopes switch to different integrated slopes when M₁₅–M₂₀ work in a different mode. When M₁₅ and M₁₈ always turn on and M₁₆, M₁₇, M₁₉, and M₂₀ turn off, the integrated slope is the largest of the multiple integrated slopes. Under this condition, C_int is C₁. For the design, each switched capacitor in the integrator has the same turn-on resistance. In the device, the design size ratio of M₁₇:M₁₆:M₁₅ is 2:1:1. The second integrated slope occurs when M₁₆ and M₁₉ turn on and M₁₇ and M₂₀ turn off. C_int is then C₁ + C₂. The third occurs when M₁₆ and M₁₉ turn off and M₁₇ and M₂₀ turn on, in which case C_int is C₁ + C₃. The last occurs when M₁₆–M₁₇ and M₁₉–M₂₀ turn on, resulting in C_int being C₁ + C₂ + C₃. Because the capacitance ratio of C₁ to (C₁ + C₂) to (C₁ + C₃) to (C₁ + C₂ + C₃) is 1:2:3:4, the ratio between integrated slopes is 12:6:4:3.

$${\mathrm{V}}_{OUT}{=\mathrm{V}}_{OUTP}-{\mathrm{V}}_{OUTN}=-\frac{1}{R_4{C}_{\mathrm{int}}}{\displaystyle \int V_{INN}}dt+\frac{1}{R_6{C}_{\mathrm{int}}}{\displaystyle \int V_{INP}}dt=\frac{1}{R_4{C}_{\mathrm{int}}}{\displaystyle \int V_{IN}}dt$$

(3)

3.3. Trigger Generator

The trigger generator comprises a differential difference amplifier M₂₁–M₂₈, R₇ [21], R₈, and a comparator M₂₉–M₄₁, as illustrated in Figure 15. The positive output terminal of the differential difference amplifier is the gate of M₃₀, and the negative output terminal is the gate of M₃₁. The voltage of the positive output terminal is expressed in Equation (4), the voltage of the negative output terminal is expressed in Equation (5), and the differential voltage of the output terminal is expressed in Equation (6). Using the result of the differential difference amplifier, the comparator generates a trigger signal.

$$v_{op}=-\left(v_{INN}\times g_{mp}+v_{ref1}\times g_{mp}\right)\times r_{on}$$

(4)

$$v_{on}=-\left(v_{INP}\times g_{mp}+v_{ref2}\times g_{mp}\right)\times r_{on}$$

(5)

$$v_{op}-v_{on}=\left[\left(v_{INP}-v_{INN}\right)-\left(v_{ref1}-v_{ref2}\right)\right]\times g_{mp}\times r_{on}$$

(6)

The comparator comprises differential inputs (M₃₀ and M₃₁), a cross-coupled latch (M₃₆ and M₃₇), a diode-connected load (M₃₃ and M₃₄), a current summary (M₃₄, M₃₅, M₃₈, and M₃₉), and an inverter-based output buffer (M₄₀ and M₄₁). When the gate voltage of M₃₀ is higher than that of M₃₁, the drain current of M₃₀ is lower than that of M₃₁; the cross-coupled latch then reduces the drain voltage of M₃₀ and increases the drain voltage of M₃₁. The current summary part summarizes the drain currents of the diode-connected loads M₃₂ and M₃₃, and the inverter-based output buffer increases the level of the output voltage to the supply voltage level. If the gate voltage of M₃₀ is lower than that of M₃₁, the level of the output voltage of the comparator decreases to the ground voltage level.

3.4. Bias Circuit

The bias circuit, depicted in Figure 16 [20], has a bias part and a start-up part. Because the bias part comprises P-type and N-type current mirror structures of M_b1–M_b6 and R_b, the circuit operates in two static states. One static state involves current, whereas the other does not. The circuit requires a start-up circuit to push the bias part into the correct operation mode. When the supply voltage turns on and the bias part is in the incorrect operation mode, the voltages V_B2 and V_B3 are low. When V_B3 is low, M_s5 turns off, the diode-connected M_s1 turns on M_s2, and M_s2 and the diode-connected M_s3 turn on M_s4 to increase V_B2 and V_B3 to the correct operation voltage. Because V_B3 is in the correct operation mode, M_s5 turns on and M_s2 turns off, and M_s4 turns off. The start-up part turns off, and the bias part is then operating in the correct mode. The bias circuit biases the amplifier depicted in Figure 12, the integrator displayed in Figure 14, and the trigger generator illustrated in Figure 15. To ensure favorable matching of the bias device M_b2, the amplifier’s M₁, the integrator’s M₈, and the trigger generator’s M₂₁, M₂₆, and M₂₉ must have the same width, length, symmetry, and device layout direction, but the device multiple can be different. Without using resistor R_b, the current mirror loop involving M_b1–M_b6 gives positive feedback. Adding the resistor R_b and the multiple M_b6 results in the loop giving negative feedback. The bias current I_b2 is determined by the resistance R_b and the size of M_b5–M_b6, as expressed in Equation (7) [20]. The bias current I_b2 has extremely low sensitivity to supply voltage variation and noise.

$$I_{b2}=\frac{2}{{\mu }_n{C}_{ox}{\left(W/L\right)}_{b5}}\cdot \frac{1}{R_b}\left(1-\frac{1}{\sqrt{{{\left(W/L\right)}_{b6}/\left(W/L\right)}_{b5}}}\right)$$

(7)

3.5. Reset Circuit

The integrator illustrated in Figure 14 starts to integrate when it receives the trigger signal and retains the result until the SAR ADC has completed its conversion. The reset circuit displayed in Figure 17 combines the trigger signal from the trigger circuit with the reset signal from the SAR ADC and then generates the reset signals int and intb, which reset the integrator. The reset circuit operates in four states: reset, hold after reset, trigger, and hold after trigger. In the reset state, a reset signal pulse enters node rst. And the node trig is 0. M₄₃, M₄₄, M₄₆, and M₄₉ turn on, and the others turn off. The node int changes to 0, and the node intb changes to 1. In the hold after reset state, the nodes rst and trig are 0, and M₄₆–M₄₇ turn off. M₄₂–M₄₅ and M₄₈–M₄₉ comprise a latch circuit and keep the int and intb voltage levels at 0 and 1, respectively. In the trigger state, a trigger signal pulse is sent to the node trig. In the meantime, the node rst is 0. M₄₂, M₄₅, M₄₇, and M₄₈ turn on, and the others turn off. The node int changes to 1, and the node intb changes to 0. In the hold after trigger state, the latch circuit keeps the int and intb voltage levels at 1 and 0, respectively.

3.6. Nonbinary SAR ADC

The block diagram of the SAR ADC is presented in Figure 18. The SAR ADC comprises a comparator, a clock generator, a capacitor array DAC (CDAC), and a nonbinary-to-binary converter (NBC). The clock generator is initiated when the falling edge of the trigger signal is reached and generates the timing clock that controls the CDAC, comparator, and NBC. The comparator detects the difference in voltage between the positive terminal and negative terminal of the CDAC. The CDAC follows the signal from the clock generator and comparator to switch the capacitors; the weight size of the capacitors is depicted in Figure 11. The data output from the ADC to the PSSR input are 10b binary code, which is depicted in Equation (8).

$$\begin{array}{ll}AD{C}_{OUT}=& 512\cdot d_9+256\cdot d_8+128\cdot d_7+64\cdot d_6+32\cdot d_5\\ & +16\cdot d_4+8\cdot d_3+4\cdot d_2+2\cdot d_1+1\cdot d_0\end{array}$$

(8)

3.7. NBC

The NBC, illustrated in Figure 19, comprises many counters that convert the nonbinary comparator results into binary digital code. The input of the NBC is depicted in Equation (9). Each piece of nonbinary code can be split into binary parts; for example, 404 × b₁₁, 248 × b₁₀, 152 × b₉, 88 × b₈, 52 × b₇, 20 × b₅, and 12 × b₄ can be split into (256 + 128 + 16 + 4) × b₁₁, (128 + 64 + 32 + 16 + 8) × b₁₀, (128 + 16 + 8) × b₉, (64 + 16 + 8) × b₈, (32 + 16 + 4) × b₇, (16 + 4) × b₅, and (8 + 4) × b₄, respectively. The nonbinary code is split into binary parts. Counters are then employed to summarize the same-order binary parts. The results of the counter are a binary result and carry-out data. The carry-out data must be summarized with the next-order binary code. Because the comparator results for b₀ and b₁ are binary, they do not need to be converted. In the last stage, an OR gate is used to obtain a summary of the carry-out data (denoted c₇₂) and the carry-out data of the full adder [17].

$$\begin{array}{ll}NB{C}_{IN}=& 404\cdot b_{11}+248\cdot b_{10}+152\cdot b_9+88\cdot b_8+52\cdot b_7+32\cdot b_6\\ & +20\cdot b_5+12\cdot b_4+8\cdot b_3+4\cdot b_2+2\cdot b_1+1\cdot b_0\end{array}$$

(9)

3.8. PSSR

Because the application has 16 channels, the area cost of the parallel-out data solution is enormous, and the data transmission line is overly large. This study employs serial-out data to prevent those problems. The PSSR illustrated in Figure 20 is used to convert the data from the parallel-in to the serial-out form. An off-chip clock is required to control the PSSR. An AND gate and the D-flip-flops (DFFs) DF₂₀–DF₂₃ divide the input clock by 12, and DF₂₄ generates the sampling clock for loading parallel data. The NOR gate generates the serial-out clock for off-chip digital I/O reception of serial-out data. The PSSR stores data in parallel by using DFFs DF₀–DF₉ and transfers the serial-out data by using multiplexes and DFFs DF₁₀–DF₁₉.

4. Measurement Results

The designed chip is implemented with CMOS 0.18 μm 1P6M technology. A photograph of the die is presented in Figure 21. The chip is 1.444 mm × 10.568 mm and contains a 16-channel front-end readout circuit for a radiation detector. Regarding the chip’s static-state performance, the minimum differential nonlinearity (DNL) and integral nonlinearity (INL) of the nonbinary SAR ADC are −0.32 and −0.43 LSB, whereas the maxima of these indicators are 0.33 and 0.37 LSB, respectively, as revealed in Figure 22. Regarding the chip’s dynamic performance, the spurious-free dynamic range, signal-to-noise ratio, signal-to-noise-and-distortion ratio, and effective number of bits (ENOB) of the nonbinary SAR ADC when a 500-KHz sine signal with a 1 MS/s sampling rate is input are 68.8 dB, 57.41 dB, 57.41 dB, and 9.24 b, respectively, as detailed in Figure 23. The power consumption of the SAR ADC is 23.5 μW. The figure of merit (FoM) is calculated using Equation (10) from [22]. The FoM of the SRA ADC is 38.9 fJ/conversion step.

$$Fo{M}_W=\frac{Power}{2^{ENOB}\times f_{Sampling}} J/conv.-step$$

(10)

The environment used for measurement in this study is depicted in Figure 24. The input signal of the chip on board device under test is provided by a function generator. The output signal is input to an oscilloscope. Analog power and digital power are supplied by respective power supplies.

The entire chip test is depicted in Figure 25. When the input signal rises and falls, the trigger signal turns on and off, respectively. The serial-out data transfer the detection result with the sampling clock and the serial-out clock. Conversion curves with different integrated slopes are displayed in Figure 26. The maximum cover range of the peak-to-peak current pulse is 750 μA. The resolution of the conversion curve and the minimum coverage of testing, described in Figure 27, are 208.3 nA and 20 μA, respectively. When the shaping time is 200 ns, the input dynamic is 2–75 pC. The nonlinearity of the conversion curve versus the peak current in the digital output is depicted in Figure 28; the maximum nonlinearity is 1.8%. The conversion curves of 16 channels from the input peak current to the digital output are depicted in Figure 29. Because of the process variation of resistors and capacitors in the integrator, the slope for each channel is different. The nonlinearity of the aforementioned conversion curves is depicted in Figure 30. The maximum nonlinearity is found to be 1.8%.

The power consumption is 19 mW/channel for a 3-V supply voltage. The power consumption of the amplifier, integrator, trigger, ADC, and PSSR is 3.14, 4.98, 8.20, 0.03, and 0.1 mW, respectively. The proportion of power consumed by each block is depicted in Figure 31.

The performance of the proposed design and that of other designs [11,12,13,23,24] are summarized in

Table 2. Summary of performance of proposed and other designs.

	This Work	[11]	[12]	[13]	[23]	[24]
Technology	0.18 μM	0.35 μM	0.18 μM	0.18 μM	-	0.35 μM
Supply voltage (V)	3/1 V	3.3	3.3	1.8	±15/3 V	5/1 V
Power per channel (mW)	19	15	15	0.02	-	30
Number of channels (unit)	16	10	64	1	1	8
Shaping time (ns)	200	280	300	100	10,000	5/10
Input charge range (pC)	2/75	2.4/104	0.48/520	0.25/17	0.01/33	0/3
Nonlinearity of converting curve (%)	1.8	<3		1.7	5	-
ADC type	SAR	-	Pipeline	Integrated	SAR	TDC
Sampling rate per channel (MS/s)	1	-	0.39	1	20 k
DNL of ADC (LSB)	−0.32/0.33	-	−0.62/0.67	−0.36/0.12	-
INL of ADC (LSB)	−0.43/0.37	-	−0.39/0.72	−0.38/0.5	-
Resolution of ADC (b)	10	-	8	8	12	40 psec
ENOB of ADC (b)	9.24	-	6.03	-	-
ADC power per channel (μW)	23.5	-	390.63	20	-	-
FoM of ADC (pJ/conversion step)	0.0389	-	15.303	-	-	-

. The number of channels in the proposed design is 16, which is higher than the number in the previously reported designs [11,13,23,24]. The input charge range, 2/75 pC, is larger than that in three other designs [13,23,24]. The nonlinearity of the conversion curve, 1.8%, is smaller than that in two other designs [11,23] and close to that in another [13]. The sampling rate per channel, 1 MS/s, is better than that in two other designs [12,23] and the same as that in another [13]. The DNL and INL in the present study—in the ranges −0.32 to 0.33 and −0.43 to 0.37, respectively—are better than those in two other designs [11,12,13]. The resolution of the ADC, 10 b, is better than that in two other designs [12,13]. The ENOB, 9.24 b, is better than that in one other design [12]. The ADC power consumption per channel, 23.5 μW, is better than that in one other design [12] and close to that in another [13]. The FoM of the proposed ADC, 0.0389 pJ/conversion step, is better than that in another design [12].

5. Conclusions

To scale down a radiation detector such that it can be incorporated into a wearable device, in this study, integrated circuit technology was employed to fabricate a 16-channel front-end readout chip for such a detector, and chip performance tests were conducted. The DNL, INL, ENOB, and power consumption of the proposed ADC are −0.32 to 0.33, −0.43 to 0.37, 9.24 b, and 23.5 μW, respectively. The resolution is 208.3 nA, and the cover range of the input current pulse from peak to peak is 20–750 μA with multiple integrated slopes. The equal input dynamic range is 2–75 pC, and the maximum nonlinearity is 1.8%. This chip is suitable for use in radiation detection, the IoT, and wearable biomedical applications.