A Linearized Open-Loop MDAC with Memory Effect Compensation Technique for High-Speed Pipelined ADC Stage

Abstract

This paper presents a prototype open-loop pipelined stage in a 45 nm CMOS process for supporting 1.8 GS/s and 10-bit design specifications of pipelined ADCs. In order to alleviate the severe non-linearity expressed by open-loop MDACs, an innovative current-mode harmonic compensation is proposed to provide input related third harmonic terms to cancel non-linearity. In addition, an effective double-sampling scheme is optimized by modifying compensation timing and input of a residual amplifier so that the pipelined stage can be immune to memory effect and improve power efficiency. The memory effect compensation scheme can provide a 21 dB improvement on output SNDR of the double-sampling pipelined stage. The simulation results illustrate that the open-loop pipelined ADC stage achieves an output SNDR of at least 52 dB with 840 mV input amplitude and 240 fF load while consuming only 11.24 mW.

1. Introduction

Modern advanced signal processing systems impose higher speed requirements on analog-to-digital converters (ADCs), and pipeline ADCs are the best compromise between speed and accuracy. As a critical component in pipelined ADCs, the settling speed and accuracy of the multiplying digital-to-analog converter (MDAC) seriously affect the performance of the ADC. There are two main problems with traditional closed-loop structures: Firstly, with advancements in CMOS technology, the gate length of MOS transistors has decreased, and supply voltages have also been reduced. As a result, achieving high DC gain directly has become increasingly difficult, which directly affects the linearity related to static error [1,2]. If high DC gain is obtained through an auxiliary gain boosting circuit, it will also increase the power consumption [3]. The second issue is that even though there are many methods available to avoid instability in closed-loop amplifiers, this problem will still become prominent in high-speed application scenarios [4].

Recently, the academic community has proposed many effectively improved MDAC structures. For example, the closed-loop structure-based ring amplifier provides a large slew rate for fast settling while achieving power efficiency [5,6,7]. However, the ring amplifier faces challenges, such as difficulties in the configuration of the dead-zone voltage and relative sensitivity to process, voltage, and temperature (PVT) variations. The research on open-loop MDACs mainly includes two types of residual amplifiers: incomplete-settled and complete-settled. The incomplete-settled residual amplifier significantly mitigates the issue of high-power consumption in pipeline ADCs because it only operates during the amplification phase [8,9,10]. However, due to the correlation between the gain of residual amplifier and the integration time, a shorter amplification phase duration requires a steeper gain-time integration slope. Consequently, the gain error caused by jitter becomes larger. The complete-settled residual amplifier is immune to the aforementioned clock jitter issue; as long as the operation state of the amplifier is established, it is independent of time changes. The main problem for open-loop complete-settled residual amplifiers is that the transconductance G_m, which is purely determined in the voltage domain, varies with signal due to the large-signal characteristics of MOS transistors [11,12,13,14,15]. This problem can be alleviated by either high-order gain calibration or linearization techniques in the analog domain.

In this work, a high-speed, medium-precision open-loop pipelined stage is presented. This open-loop MDAC effectively avoids the risk of instability in high-frequency signal processing compared to close-loop MDAC and can output 8-bit residual signals without any digital correction. Furthermore, it innovatively employs a current-mode compensation technique, which reduces gain sensitivity to process–voltage–temperature (PVT) variations. In addition, the amplifier sharing technique is adopted to improve power efficiency, and the memory effect cancellation method mentioned in this paper avoids the problem of requiring additional long reset times in traditional double-sampling MDACs.

2. Architecture of the Proposed Pipelined ADC Stage

The block diagram of the proposed pipelined ADC stage is given in Figure 1. The complete stage includes a gate voltage bootstrap S/H circuit, high-speed sub-ADC, CDAC, memory charge cancellation circuit, and open-loop residual amplifier. In order to alleviate the accuracy requirement for an open-loop amplifier, the pipelined ADC stage is designed as a 2.5-bit/stage, converting 3-bit output codes that include 1-bit redundancy. As stated in [11], the employment of top-plate sampling for incorporating a reset period can reduce the use of clocks that turn off prematurely, but it will compress amplification time and increase the impact of channel charge injection effects. Since the open-loop residual amplifier is quite sensitive to the input common-mode voltage, the prototype MDAC still employs bottom-plate sampling and is assisted with a memory effect cancellation circuit. In order to meet the requirements of matching and ADC speed, as well as suppress sampling noise in the switched capacitor circuit, the unit capacitance C₀ of the CDAC is chosen to be 60 fF, which results in a total differential sampling capacitance of 960 fF for the pipelined ADC stage. The CDAC is constructed in the form of a thermometer code, which determines whether the capacitors in the MDAC are connected to +V_REF or −V_REF. The final conversion result is transmitted into the residual amplifier after being subtracted from the sampled input signal. The proposed pipelined ADC stage benefits from a linearized design, allowing the residual output to achieve at least 0.85 V of swing under a power supply voltage of 1.2 V.

3. The Open-Loop Amplifier Linearized Through Harmonic Compensation

3.1. Performance Limitation of MDAC

The performance of pipeline ADC is often limited by its first stage. For a pipelined ADC with N-bit total resolution and k-bit per-stage resolution, since the first stage needs to provide a (N-k) bit accurate input signal for the second stage, the precision requirement amplifier can be effectively relaxed due to its 2^k gain. For a single pole 2.5-bit/stage MDAC system, the residual output voltages can be given by the following equation:

$$V_{out}=\left({\displaystyle \frac{C_{S}A}{C_P+C_S}}\cdot V_{in}-{\displaystyle \frac{A\cdot {\displaystyle \sum _{i=1}^8{D}_i{V}_{ref}{C}_i}}{C_P+C_S}}\right)\cdot \left(1-e^{-t_S\cdot BW}\right)$$

(1)

where V_ref is the reference voltage, t_S is the small signal settling time, BW is the main pole bandwidth, and C_P and C_S are parasitic capacitance and sampling capacitance, respectively. The equation reveals that the error in V_out primarily comprises two components: firstly, the DC gain error in term $C_{S}A/\left(C_P+C_S\right)$ caused by nonlinearity, and secondly, the dynamic gain error term $1-e^{-t_S\cdot BW}$ due to small-signal settling errors. Taking the MDAC designed for a 10-bit resolution ADC in this work as an example, and assuming the magnitudes of these two errors are equal, the nonlinear error $\Delta A/A$ in DC gain must satisfy:

$${\epsilon }_{DC}={\displaystyle \frac{\Delta A}{A}}\le {\displaystyle \frac{1}{2^{j+1}}}\times {\displaystyle \frac{LSB}{V_{FS}}}\times 2^{k-1}=0.1953$$

(2)

where $\Delta A$ is the DC gain error, ${\displaystyle \frac{LSB}{V_{FS}}}={\displaystyle \frac{1}{2^N}}$, and j is the additional peak-to-peak DNL/INL accuracy required for the quantization margin; if the additional requirement is 0.5 LSB, then j is 1.

Similarly, the amplifier’s allowed settling error needs to be:

$${\epsilon }_{settle}=e^{-t_S\cdot BW}\le {\displaystyle \frac{1}{2^{j+1}}}\times {\displaystyle \frac{LSB}{V_{FS}}}\times 2^{k-1}$$

(3)

Therefore, when the settling time t_S needs to be less than 450 ps, the required bandwidth can be calculated as BW = 2.206 GHz. However, since a typical MDAC is a multi-pole system, the actual required bandwidth will be higher. With the limitation of linearity and bandwidth, we have the specifications needed to design the MDAC’s amplifier.

3.2. Amplifier Linearity Analysis

An effective method for linearizing the voltage amplifier utilizing post-correction is shown in Figure 2. The main design idea is to consider the two-stage amplifier as a cascade of a V-I converter and an I-V converter, where the two converters have opposite curvature variations. It allows the compressed linearity to be well-corrected.

As shown in [15], traditional operational amplifiers exhibit compressing V-I characteristics due to the limitation of the fixed tail current source. Therefore, the linearization design discussed in this paper primarily focuses on the I-V module. Any MOS transistor integrated in a circuit will cause nonlinearity due to its channel modulation effect and the variation of g_m with the input. Now, if the large-signal model of a G_m unit with third-order nonlinearity is expanded in polynomial form, the V-I characteristics can be obtained:

$$I_{out1}=a_1{V}_{in1}-a_3{V}_{in1}^3$$

(4)

$$V_{out2}=b_1{I}_{out1}+b_3{I}_{out1}^3$$

(5)

where a₁ and a₃ have the same polarities, and a₁ represents the equivalent transconductance of the first stage, and a₃ indicates the compressing characteristic of the V-I transfer. Similarly, b₁ represents the equivalent transimpedance of the second stage, and b₃ is the Nonlinear coefficient of the second stage. The corrected output voltage can be obtained by substituting Equation (4) into Equation (5):

$$\begin{array}{cc}\hfill V_{out2}& =a_1{b}_1\cdot V_{in1}-(a_3{b}_1-a_1^3{b}_3)\cdot V_{in1}^3-3a_1^2{a}_3{b}_3\cdot V_{in1}^5+\hfill \\ & 3a_1{a}_3^2{b}_3\cdot V_{in1}^7-a_3^3{b}_3\cdot V_{in1}^9\hfill \end{array}$$

(6)

where A = a₁b₁ is the target gain for the amplifier design and $-(a_3{b}_1-a_1^3{b}_3)$ is the total third-order nonlinearity at the amplifier output. To ideally cancel the effect of the original $-a_3{V}_{in1}^3$, b₁ and b₃ need to satisfy:

$$(a_3{b}_1-a_1^3{b}_3)\cdot V_{in1}^3=0$$

(7)

thus, obtaining the ideal values for b₁ and b₃:

$$\left\{\begin{array}{l}{b}_1={\displaystyle \frac{A}{a_1}}\\ b_3={\displaystyle \frac{a_{3}A}{a_1^4}}\end{array}\right.$$

(8)

In practical design, since a₁ has an impact in the form of a square in the fifth-order term of $3a_1^2{a}_3{b}_3\cdot V_{in1}^5$, a₁ is set slightly smaller, while b₁ is set slightly larger.

3.3. Current-Mode Harmonic Compensation Circuit Design

From the above analysis, it can be seen that in order to cancel the nonlinearity of the third-order term, a positive b₃ is required. Since it is difficult to directly obtain a cubic current signal in CMOS circuits, a method of obtaining the cubic term through two successive current squaring circuits is considered in this work.

To reduce additional nonlinearity caused by unnecessary MOS transistors, the current squaring circuit needs to use the simplest structure to obtain reliable squared current signals. The current square circuit [16] shown in Figure 3 is used in this paper. Under the conditions of the large-signal model, assuming that the input current, which is the output current of the first stage I_in = I_D + i_D, where I_D is the fixed DC current part and i_D is the AC current part., then, the output current I_out is given by:

$$I_{out}=m\cdot [2I_0+{\displaystyle \frac{{(I_D+i_D)}^2}{8I_0}}]$$

(9)

In Figure 3, m is the current mirror multiplication factor, and I₀ is the bias current. To obtain a positive cubic term, the mirrored first-stage output current nI_in in Figure 4 must be subtracted from I_out:

$$I_{out}-n{I}_{in}=I_{out}-n\cdot (I_D+i_D)$$

(10)

However, such current subtraction requires additional current steering circuits, which inevitably increases the power consumption of the circuit and introduces non-ideal effects. Therefore, by utilizing the symmetric property of the differential circuit, the output current I_out of the first current squaring circuit is added with the mirrored current from the other side of the original first-stage output. In this case, we have:

$$I_{out}+n{I}_{in}=I_{out}+n\cdot (I_D-i_D)$$

(11)

and expanding this expression gives:

$$I_{out}+n\cdot (I_D-i_D)={\displaystyle \frac{m\cdot i_D^2}{8I_0}}+({\displaystyle \frac{m\cdot I_D}{4I_0}}-n)\cdot i_D+2m{I}_D+{\displaystyle \frac{m\cdot I_D^2}{8I_0}}+n{I}_D$$

(12)

From the above equation, it can be seen that the constant term must be positive, and the necessary requirement for the compensation design is that m/8I₀ and (mI_D/4I₀ − n) have opposite symbols. If the first-stage nonlinearity of an open-loop amplifier requires significant compensation, a larger n should be necessary to obtain a larger positive cubic term in the final compensation result.

For simplicity and to ensure sufficient gain, the second current squaring circuit adopts a common-source amplifier structure, as shown in Figure 4. The current signal is firstly converted into an equivalent voltage signal before performing the squaring operation. In order to achieve better squaring property to improve compensation capability, the common-source transistor M₁ needs to operate near the subthreshold region, and the size of M₁ must be carefully chosen as a compromise due to bandwidth issues. Since the second squaring circuit is a simple common-source structure, it introduces inherent nonlinearity to this configuration, which degrades the overall harmonic compensation efficiency. Therefore, transconductance compensation is applied to M₁ by using another transistor M₃ working in class-C to compensate during large output swings. V_p and V_n are the voltages of the corresponding nodes in the differential circuit.

The result of the second squaring and unfolding of the current $I_{out}+n{I}_{in}=I_{out}+n\cdot (I_D-i_D)$ is:

$$\begin{array}{l}{k}_n\cdot {\left\{\left[I_{out}+n\cdot (I_D-i_D)\right]\cdot R_1-V_T\right\}}^2=\\ k_n\cdot \left\{\left[2\cdot {\displaystyle \frac{m}{8I_0}}\cdot \left({\displaystyle \frac{m{I}_D}{4I_0}}-n\right)\cdot R_1^2{i}_D^3\right]+\cdots -2V_T{R}_1\cdot \left[{\displaystyle \frac{m{i}_D^2}{8I_0}}+({\displaystyle \frac{m{I}_D}{4I_0}}-n)\cdot i_D+2m{I}_D+{\displaystyle \frac{m{I}_D^2}{8I_0}}+n{I}_D\right]+V_T^2\right\}\end{array}$$

(13)

where k_n is the inherent parameters of transistors, and V_T is the threshold voltage of M₁. In Equation (10), the third-order current component $I=2k_n\cdot {\displaystyle \frac{m}{8I_0}}\cdot \left({\displaystyle \frac{m{I}_D}{4I_0}}-n\right)\cdot R_1^2{i}_D^3$ will exhibit positive polarity after being reconverted to voltage through $V_{out}=V_{DD}-I{R}_2$.

The entire current-mode harmonic compensation circuit uses NMOS transistors as much as possible, so most transistors exhibit similar mobility variations across different process corners, resulting in a more stable compensation effect.

3.4. First-Stage Amplifier

The first-stage amplifier employs the simple differential source degeneration structure shown in Figure 5. The first stage requires a trade-off between bandwidth, gain, and linearity during the design. The transconductance of this stage can be figured from the following equation:

$$G_m={\displaystyle \frac{g_m}{1+g_m{R}_S}}$$

(14)

A larger R_s would improve linearity but would also lead to a decrease in G_m, as well as a decrease in the dominant pole and gain. Therefore, in this work, R_s does not need to be very large; it only needs to alleviate the pressure on the current-mode harmonic compensation stage. In summary, R_s is set to 1.38 kΩ in this work. On the other hand, due to the high precision requirements of the first-stage CDAC, which is susceptible to the parasitic capacitance at the input of the amplifier, the gain of the first-stage amplifier should not be set too large. In this design, the gain of the first stage is approximately 1.2.

3.5. Open-Loop Amplifier with Current-Mode Harmonic Compensation

The overall two-stage open-loop amplifier structure is shown in Figure 6. In order to drive the large sampling capacitor of the subsequent pipelined stage, an additional buffer is added. The total gain of the amplifier is 4.466, which will be corrected with CDAC gain calibration [11,14] to achieve an inter-stage gain of about 4. The static current of this design is 5.88 mA, resulting in a power consumption of 7.056 mW for a single amplifier.

Employing conventional noise analysis techniques allows us to show how input referred thermal noise density is approximately given by the following expression:

$$\overline{V_{n,in}^2}=4KT\cdot [{\displaystyle \frac{\frac{\frac{\gamma }{g_{m22}^2{R}_2{R}_4}+\frac{\gamma }{g_{m22}{R}_2}+\frac{1}{R_2}+\gamma \cdot (g_{m9}+g_{m22})}{m^2}}{{(\frac{g_{m2}}{g_{m2}{R}_S+1})}^2}}+{\displaystyle \frac{\gamma \cdot (g_{m18}+g_{m8}+g_{m4}+2g_{m16})+\frac{g_{m2}^2{R}_S}{{(g_{m2}{R}_S+1)}^2}}{{(\frac{g_{m2}}{g_{m2}{R}_S+1})}^2}}+{\displaystyle \frac{\gamma }{g_{m2}}}]$$

(15)

where k is the Boltzmann constant, and γ is the process-dependent noise coefficient. From the above analysis, the most effective method to reduce the overall noise of the amplifier is to increase the small-signal transconductance of MOS transistors M₂ and M₂₂, and to increase the current scaling coefficient m, while decreasing the small signal transconductance of M₄, M₈, M₉, M₁₆, and M₁₈.

4. Memory Effect Compensation

4.1. Memory Effect Analysis

All multiplexing sampling systems are inevitably affected by the memory effect, and pipelined ADCs operating in double-sampling mode are no exception. When only considering the influence between adjacent phases, the output voltage of a conventional double-sampling system, as shown in Figure 7, which includes inter-channel crosstalk in each cycle [17], can be expressed as:

$$V_{out2}={\displaystyle \frac{V_{out1}}{A}}\cdot {\displaystyle \frac{C_p}{\frac{C_s+C_p}{A}-C_s}}-V_{in2}\cdot {\displaystyle \frac{C_p}{\frac{C_s+C_p}{A}-C_s}}$$

(16)

where C_s and C_p are the sampling capacitor and input parasitic capacitor of the amplifier, respectively, A is the open-loop gain of the amplifier, and the term containing V_out1 represents the memory effect interference. It can be seen that the magnitude of the inter-channel crosstalk in the output of conventional closed-loop sampling systems is greatly influenced by the open-loop gain A. Therefore, the memory effect can be attenuated with a large DC gain of the op-amp and small parasitic capacitance. However, for the same V_out1, the inter-channel crosstalk has more severe impacts on V_out2 in an open-loop MDAC, because of the relatively low amplifier gain; therefore, a precise compensation scheme is necessary.

4.2. Memory Effect Compensation Scheme

The most ideal and simplest way to eliminate crosstalk caused by memory effects is resetting, but inserting an additional reset phase would significantly reduce the time available for the amplification phase because of the particularity of double sampling. In order to avoid occupying time from the amplification phase, this work adopts a memory charge cancellation technique.

The pipelined ADC stage implemented based on this scheme is shown in Figure 8. The timing logic is shown in Figure 8b, where Φ₁′ and Φ₂′ control the memory effect cancellation for channel 1 and channel 2, respectively. Figure 8c illustrates the configuration of input terminals of the improved open-loop amplifier. The input transistors of the conventional open-loop amplifier are split into four parts: A, B, C, and D, each with a size equivalent to half of the original. The four input terminals are alternately paired in two adjacent amplification phases to achieve memory charge cancellation at the input of the amplifier.

During phase Φ₂, channel 2 samples the signal onto C_s, while the residual signal generated at the end of the previous phase Φ₁ is amplified in channel 1 and simultaneously charges the input parasitic capacitance of the amplifier. Since the amplifier operates in fully differential mode, the charges stored on the capacitors at terminals A, B, C, and D of the amplifier are opposite polarity, and the charge amounts are assumed to be +Q and −Q, respectively. In the subsequent Φ₁ phase, the amplifier input terminals B and C are switched to paths opposite to those in the Φ₂ phase before the residual signal of channel 2 is amplified. The charges stored on the input capacitors of terminals A and C have opposite polarities but equal amounts, thus, the memory charge will be canceled out. The same effect also occurs at terminals B and D.

The memory effect in open-loop pipelined ADC with double-sampling is more severe compared to that in a closed-loop structure. By advancing the memory effect compensation control signal to a brief period before the actual turn-on moment of the amplification phases Φ₁/Φ₂, charge cancellation can be performed prior to inputting the residual voltage of the corresponding channel, thereby further improving the accuracy of compensation. On the other hand, the switch configurations for each of the amplifier input terminals A, B, C, and D are set to be identical, which minimizes differences in input parasitic capacitance C_p between the terminals. This method prevents incomplete charge cancellation caused by input capacitance mismatch.

5. Simulation Results

The pipelined ADC stage based on an open-loop structure is manufactured in 45 nm CMOS technology. The layout of the pipelined ADC stage is shown in Figure 9, and it includes gate voltage bootstrap S/H circuits, a double-sampling MDAC, and a high-speed dynamic comparator in a fully differential structure. Each module is carefully laid out to minimize mismatch, and the occupied area of the proposed ADC stage is 0.06 mm².

5.1. Simulation Results of the Open-Loop Amplifier

Figure 10 illustrates the relationship of DC gain versus input amplitude of an open-loop amplifier. Figure 10a shows that the open-loop amplifier maintains good DC gain flatness under both TT and SF process corners. The DC gain flatness decreases under SS and FF process corners, while the FS process corner exhibits poor DC gain flatness performance, which is therefore not presented in the figure. The carrier mobility of PMOS deviates more significantly compared to NMOS under slow corner conditions, resulting in substantial DC operating point drift in the amplifier despite the implementation of common-mode feedback. This operating point drift becomes particularly pronounced when the carrier mobilities of NMOS and PMOS change in opposite directions. Figure 10b further indicates that the dynamic error of SFDR also worsens under the SS corner due to relatively poor gain flatness.

To further illustrate the impact of process variations and device mismatches on SFDR performance, Figure 11 presents approximately 250 Monte Carlo simulation results under a 900 MHz input signal scenario. The results demonstrate that the output SFDR of the MDAC is higher than 50 dB.

When the input differential amplitude is 100 mV and the initial gain is 4.466, the output V_PP should be 893.2 mV. The normalized maximum gain deviation is 0.001138 under the TT corner, which meets the 9-bit accuracy requirement. If reducing the input amplitude to improve accuracy, when the input differential amplitude is 95 mV and the initial gain is 4.466, then the output V_PP should be 848.54 mV. The normalized maximum gain deviation is 0.000078, which meets the 13-bit accuracy requirement.

In terms of dynamic error, since the open-loop amplifier adopts a fully open-loop structure, the dominant pole of the circuit is determined by both the load and output resistance of the amplifier. The dominant pole can be figured out by analyzing Figure 6, which is expressed as:

$${\omega }_{p1}={\displaystyle \frac{1}{R_{out}{C}_L}}={\displaystyle \frac{\left(1 + g_{m27}{r}_{o27}\right)\left(1 + g_{m29}{r}_{o29}\right)}{\left[\left(1 + g_{m29}{r}_{o29}\right)r_{o27}+r_{o29}\right]\cdot C_L}}$$

(17)

Figure 12a shows the AC response of the harmonic-compensated open-loop amplifier, and it can be observed that the −3 dB bandwidth is approximately 2.366 GHz, with a GBW of 7.67 GHz. In order to more intuitively reflect the impact of bandwidth on dynamic errors, the simulation result of transient response is shown in Figure 12b. The input signal is a step wave with a differential amplitude of 100 mV, and the load is set to 120 fF. From the step response waveform, it can be seen that the input signal undergoes a jump at 2 ns, and the output signal can complete the settling and meet the 10-bit accuracy requirement of dynamic error within approximately 250 ps.

5.2. Simulation Results of the Memory Effect Compensation Circuit

To verify the effectiveness of the memory effect compensation circuit, this work simulates the output spectrum of the double-sampling amplification mode under two conditions: with and without the memory effect compensation circuit. The comparison results of the spectrum are shown in Figure 13. In the simulation, an 80 MHz sine wave is applied to channel 1, and a 55 MHz sine wave is applied to channel 2, both having differential amplitudes of 90 mV, while the output of sub-DAC is manually set to zero. The simulation comparison results show that without the memory effect compensation, the SNDR is compressed to only 37.33 dB because of channel crosstalk. However, when the memory effect compensation circuit is active, the crosstalk signal is canceled before amplification, resulting in an output SNDR of 58.33 dB, which is an improvement of 21 dB compared to the previous case.

5.3. Simulation Results Comparison

Figure 14 illustrates the relationship between the output SNDR of the pipelined stage and the input signal frequency at an equivalent sampling rate of 1.8 GS/s. The figure shows that the proposed open-loop MDAC provides an output SNDR of at least 50 dB under the double-sampling mode, equivalent to an 8-bit ENOB settling precision, which can satisfy the design requirements for the first stage of a 10-bit ENOB pipelined ADC.

Table 1. MDAC performance comparison of pipelined ADC stage.

	[11]	[8]	[14]	[27]	This Work
Process	65 nm	28 nm	65 nm	28 nm	45 nm
Supply (V)	1.2	1	1.2	0.9	1.2
Input amplitude (mV)	800	1200	1600	1100	850
Sampling rate (GS/s)	1.8	1	0.3	1	1.8
Output accuracy of residual amplifier (bit)	7	9	7	11	8
Power	9.92 mW	2.5 mW	8.12 mW	2.37 mW	11.24 mW 1

¹ Excluding power supply on clock generator and digital circuit biases.

shows a comparison between the state-of-the-art pipelined ADC [8,11,14,18,19,20,21,22,23,24,25,26,27] and this work.

6. Conclusions

This paper proposes a prototype open-loop pipelined ADC stage. An innovative linearization technique based on the current-mode compensation circuit is employed for the MDAC. The current-mode compensation circuit can provide positive third-order harmonics related to the input signal to counteract the negative third-order harmonics derived from the gain compression of the preceding amplifier. In addition, the memory effect cancellation technique can alleviate the severe inter-channel crosstalk of the open-loop MDAC in the double-sampling mode. This scheme is optimized by tuning the timing of compensation and aligning the input capacitance of the amplifier, achieving a 21 dB improvement on the output SNDR of the MDAC. The open-loop pipelined ADC stage obtains the least output SNDR of 52.46 dB at 1.8 GS/s while consuming 11.24 mW. The prototype pipelined stage is proven to be sufficient to support the design requirements for a 10-bit pipelined ADC.