Search Results (16)

We proposed a novel technique for detecting optical filter shift in ROADMs in optical transmission lines by applying machine learning on DP-16QAM constellation data captured just after Analogue-to-Digital Converters (ADCs) in a digital coherent receiver. For this purpose, we implemented Docker container applications in WhiteBox Cassini to acquire the real-time raw digital data. By using the captured data, we generated CNN models for the detections in off-line processing and used them for real-time detections. As preliminary results, we confirmed the successful detection of optical filter shift in real-time with an accuracy of 51 GHz. To enhance the detection accuracy, we challenged ourselves to reproduce digital coherent constellation data by using a Generative Adversarial Network (GAN) for real-time optical filter shift detection for the first time. By utilizing a GAN, we successfully generated clone data based on actual constellation data. By adding the cloned data onto the actually captured data, we successfully enhanced detection sensitivity to as high as 26 GHz. As a result, we reduced the amount of required data for the high detection accuracy by 68% with the help of GAN-supported data augmentation. Furthermore, we confirmed our augmentation method enables the prediction of faults before they occur by enabling high enough detection sensitivity to detect an optical filter shift before degradation of Bit Error Rates (BERs) appears. This demonstrates the potential of GAN-based data augmentation in optimizing the efficiency and precision of optical network impairment sensing by using captured digital coherent optical signal. Full article

The design of conventional digital predistortion (DPD) requires an analogue-to-digital converter (ADC) with a sampling frequency that is multiple times the signal bandwidth, which is extremely challenging for sub-Nyquist sampling systems with undersampled signals. To address this, this paper proposes a neural network (NN)-assisted wideband power amplifier (PA) DPD method for sub-Nyquist sampling systems, wherein a dual-stage architecture is designed to handle the ambiguity caused by subsampled communications signals. In the first stage, the time-delayed polynomial reconstruction method is employed to estimate the wideband DPD nonlinearity coarsely with the undersampled signals with limited pilots. In the second stage, an NN-based DPD method is proposed for the virtual training of the DPD, which learns the up-sampled DPD behavior by taking advantage of the pre-estimated DPD model and the input data signals, which reduces the length of the training sequence significantly and refines the DPD behavior efficiently. Simulation results demonstrate the efficacy of the proposed method in tackling the wideband PA nonlinearity and its ability to outperform the conventional method in terms of power spectrum, error vector magnitude, and bit error rate. Full article

This article is about the design, development and validation of a new monitoring architecture for individual cells and stacks to facilitate the study of proton exchange fuel cells. The system consists of four main elements: input signals, signal processing boards, analogue-to-digital converters (ADCs) and a master terminal unit (MTU). The latter integrates a high-level graphic user interface (GUI) software developed by National Instruments LABVIEW, while the ADCs are based on three digital acquisition units (DAQs). Graphs showing the temperature, currents and voltages in individual cells as well as stacks are integrated for ease of reference. The system validation was carried out both in static and dynamic modes of operation using a Ballard Nexa 1.2 kW fuel cell fed by a hydrogen cylinder, with a Prodigit 32612 electronic load at the output. The system was able to measure the voltage distributions of individual cells, and temperatures at different equidistant points of the stack both with and without an external load, validating its use as an indispensable tool for the study and characterization of these systems. Full article

SALT, a new dedicated readout Application Specific Integrated Circuit (ASIC) for the Upstream Tracker, a new silicon detector in the Large Hadron Collider beauty (LHCb) experiment, has been designed and developed. It is a 128-channel chip using an innovative architecture comprising a low-power analogue front-end with fast pulse shaping and a 40 MSps 6-bit Analog-to-Digital Converter (ADC) in each channel, followed by a Digital Signal Processing (DSP) block performing pedestal and Mean Common Mode (MCM) subtraction and zero suppression. The prototypes of SALT were fabricated and tested, confirming the full chip functionality and fulfilling the specifications. A signal-to-noise ratio of about 20 is achieved for a silicon sensor with a 12 pF input capacitance. In this paper, the SALT architecture and measurements of the chip performance are presented. Full article

The low-level radio frequency (LLRF) control system is one of the fundamental parts of a particle accelerator, ensuring the stability of the electro-magnetic (EM) field inside the resonant cavities. It leverages on the precise measurement of the field by in-phase/quadrature (IQ) detection of an RF probe signal from the cavities, usually performed using analogue downconversion. This approach requires a local oscillator (LO) and is subject to hardware non-idealities like mixer nonlinearity and long-term temperature drifts. In this work, we experimentally evaluate IQ detection by direct sampling for the LLRF system of the Polish free electron laser (PolFEL) now under development at the National Centre for Nuclear Research (NCBJ) in Poland. We study the impact of the sampling scheme and of the clock phase noise for a 1.3-GHz input sub-sampled by a 400-MSa/s analogue-to-digital converter (ADC), estimating amplitude and phase stability below 0.01% and nearly 0.01°, respectively. The results are in line with state-of-the-art implementations, and demonstrate the feasibility of direct sampling for GHz-range LLRF systems. Full article

This paper presents a fully integrated 64-channel neural recording system for local field potential and action potential. It mainly includes 64 low-noise amplifiers, 64 programmable amplifiers and filters, 9 switched-capacitor (SC) amplifiers, and a 10-bit successive approximation register analogue-to-digital converter (SAR ADC). Two innovations have been proposed. First, a two-stage amplifier with high-gain, rail-to-rail input and output, and dynamic current enhancement improves the speed of SC amplifiers. The second is a clock logic that can be used to align the switching clock of 64 channels with the sampling clock of ADC. Implemented in an SMIC 0.18 μm Complementary Metal Oxide Semiconductor (CMOS) process, the 64-channel system chip has a die area of 4 × 4 mm² and is packaged in a QFN−88 of 10 × 10 mm². Supplied by 1.8 V, the total power is about 8.28 mW. For each channel, rail-to-rail electrode DC offset can be rejected, the referred-to-input noise within 1 Hz–10 kHz is about 5.5 μV_rms, the common-mode rejection ratio at 50 Hz is about 69 dB, and the output total harmonic distortion is 0.53%. Measurement results also show that multiple neural signals are able to be simultaneously recorded. Full article

There has been considerable interest in applying electroencephalography (EEG) and functional near-infrared spectroscopy (fNIRS) simultaneously for multimodal assessment of brain function. EEG–fNIRS can provide a comprehensive picture of brain electrical and hemodynamic function and has been applied across various fields of brain science. The development of wearable, mechanically and electrically integrated EEG–fNIRS technology is a critical next step in the evolution of this field. A suitable system design could significantly increase the data/image quality, the wearability, patient/subject comfort, and capability for long-term monitoring. Here, we present a concise, yet comprehensive, review of the progress that has been made toward achieving a wearable, integrated EEG–fNIRS system. Significant marks of progress include the development of both discrete component-based and microchip-based EEG–fNIRS technologies; modular systems; miniaturized, lightweight form factors; wireless capabilities; and shared analogue-to-digital converter (ADC) architecture between fNIRS and EEG data acquisitions. In describing the attributes, advantages, and disadvantages of current technologies, this review aims to provide a roadmap toward the next generation of wearable, integrated EEG–fNIRS systems. Full article

A novel transmission technique—namely, a DFT-spread spectrally overlapped hybrid OFDM–digital filter multiple access (DFMA) PON based on intensity modulation and direct detection (IMDD)—is here proposed by employing the discrete Fourier transform (DFT)-spread technique in each optical network unit (ONU) and the optical line terminal (OLT). Detailed numerical simulations are carried out to identify optimal ONU transceiver parameters and explore their maximum achievable upstream transmission performances on the IMDD PON systems. The results show that the DFT-spread technique in the proposed PON is effective in enhancing the upstream transmission performance to its maximum potential, whilst still maintaining all of the salient features associated with previously reported PONs. Compared with previously reported PONs excluding DFT-spread, a significant peak-to-average power ratio (PAPR) reduction of over 2 dB is achieved, leading to a 1 dB reduction in the optimal signal clipping ratio (CR). As a direct consequence of the PAPR reduction, the proposed PON has excellent tolerance to reduced digital-to-analogue converter/analogue-to-digital converter (DAC/ADC) bit resolution, and can therefore ensure the utilization of a minimum DAC/ADC resolution of only 6 bits at the forward error correction (FEC) limit (1 × 10⁻³). In addition, the proposed PON can improve the upstream power budget by >1.4 dB and increase the aggregate upstream signal transmission rate by up to 10% without degrading nonlinearity tolerances. Full article

This paper presents a 10-bit 0.909-MHz 8-channel dual-mode successive approximation (SAR) analogue-to-digital converter (ADC) for brushless direct current (BLDC) motor drive, using a Taiwan Semiconductor Manufacturing (TSMC) 0.25 μm 1P3M Complementary Metal Oxide Semiconductor (CMOS) process. The sample-and-hold (S/H) circuit operates with two sampling modes. One is individually sampling eight channels in sequence with an S/H circuit and the other is sampling four channels simultaneously with four S/H circuits. All sampled data will be digitized with high-speed SAR ADC in time division multiplexing (TDM). A dynamic latch-type comparator is utilized to latch the output at an upper or lower level. The advantage of the designed comparator is that it performs with positive feedback to quickly complete the latch function. The double-tail latch-type architecture is utilized to mitigate the significant kickback effect by separating the pre-amplifier stage from the latch. By integrating an input NMOSFET with an input PMOSFET, the designed latch-type comparator can perform with full-swing input voltage. Measurements show that the signal-to-noise ratio (SNR), signal-to-noise-and-distortion ratio (SNDR), effective number of bits (ENOB), power consumption, and chip area are 50.56 dB, 57.03 dB, 8.11 bits, 833 μW, and 1.35 × 0.98 mm², respectively. The main advantages of the proposed multichannel dual-mode SAR ADC are its low power consumption of 833 μW and high measured resolution of 8.11 bits. Full article

Analogue-to-digital converters (ADC) using oversampling technology and the Σ-∆ modulation mechanism are widely applied in digital audio systems. This paper presents an audio modulator with high accuracy and low power consumption by using a discrete second-order feedforward structure. A 5-bit successive approximation register (SAR) quantizer is integrated into the chip, which reduces the number of comparators and the power consumption of the quantizer compared with flash ADC-type quantizers. An analogue passive adder is used to sum the input signals and it is embedded in a SAR ADC composed of a capacitor array and a dynamic comparator which has no static power consumption. To validate the design concept, the designed modulator is developed in a 180 nm CMOS process. The peak signal to noise distortion ratio (SNDR) is calculated as 106 dB and the total power consumption of the chip is recorded as 3.654 mW at the chip supply voltage of 1.8 V. The input sine wave of 0 to 25 kHz is sampled at a sampling frequency of 3.2 Ms/s. Moreover, the results achieve a 16-bit effective number of bits (ENOB) when the amplitude of the input signal is varied between 0.15 and 1.65 V. By comparing with other modulators which were realized by a 180 nm CMOS process, the proposed architecture outperforms with lower power consumption. Full article

This paper describes the design, implementation, and testing of a novel multi-function software defined Radio Frequency (RF) system designed for small airborne drone applications. The system was created using an inexpensive Field Programmable Gate Array (FPGA) to combine a coherent linear frequency modulated radar transmitter and receiver, with a Digital Radio Frequency Memory (DRFM) jammer for use with a common RF aperture in simultaneous operation. The system was implemented on a Xilinx Kintex-7 FPGA with a wideband analogue-to-digital/ digital-to-analogue (ADC/DAC) converter mezzanine board and tested using hardware-in-the-loop mode to validate its performance. This is the first known account of an integrated multifunction electronic attack and radar system on a single chip, capable of performing a simultaneous, not time shared, operation. Full article

A 12-bit 200 MS/s pipelined successive-approximation-register (SAR) analogue-to-digital-converter (ADC) implemented in 40 nm CMOS is presented. Such an ADC consists of two asynchronous SAR ADCs and a dynamic amplifier, which consumes a static power of 1.2 mW (the total power is 8 mW) and occupies an area of 0.046 mm². The inter-stage gain is affected by the parasitic capacitance in SAR ADCs as well as the gain of the dynamic amplifier, which is variable with respect to process-voltage-temperature (PVT). A background calibration of the inter-stage gain is proposed to adjust the inter-stage gain and to track the PVT variables. The measurement results show that, with calibration, the spurious-free-dynamic-range (SFDR) and signal-to-noise-and-distortion-ratio (SINAD) can be improved from 68 dB and 61 dB to 78 dB and 63 dB, respectively. The dynamic performance was stable under different VT conditions. Full article

In the present work, two approaches for the phase current measurement of a permanent magnet synchronous motor (PMSM) were compared. The measured phase current was distorted by glitches, and a software method to eliminate these glitches was necessary. An averaging of samples was carried out, and the experimental results indicated that averaging was essential for further calculations. Moreover, the PMSM operated smoothly, and the difference between the set point and the actual speed was reduced for the full range of loads from the free run up to a full load. The increasing popularity of field-programmable gate array (FPGA) devices has encouraged developments in PMSM controllers using a direct hardware approach and the classic software approach utilizing a digital signal processor unit. In this study, the selected performance of TMS320F2812 and Spartan-3E were compared. This paper proposes an original adaptive correction method for a current transducer. Full article

The capacity region of a two-transmitter Gaussian multiple access channel (MAC) under average input power constraints is studied, when the receiver employs a zero-threshold one-bit analogue-to-digital converter (ADC). It is proven that the input distributions of the two transmitters that achieve the boundary points of the capacity region are discrete. Based on the position of a boundary point, upper bounds on the number of the mass points of the corresponding distributions are derived. Furthermore, a lower bound on the sum capacity is proposed that can be achieved by time division with power control. Finally, inspired by the numerical results, the proposed lower bound is conjectured to be tight. Full article

In this study, an in-duct ultrasonic airflow measurement device has been designed, developed and tested. The airflow measurement results for a small range of airflow velocities and temperatures show that the accuracy was better than 3.5% root mean square (RMS) when it was tested within a round or square duct compared to the in-line Venturi tube airflow meter used for reference. This proof of concept device has provided evidence that with further development it could be a low-cost alternative to pressure differential devices such as the orifice plate airflow meter for monitoring energy efficiency performance and reliability of ventilation systems. The design uses a number of techniques and design choices to provide solutions to lower the implementation cost of the device compared to traditional airflow meters. The design choices that were found to work well are the single sided transducer arrangement for a “V” shaped reflective path and the use of square wave transmitter pulses ending with the necessary 180° phase changed pulse train to suppress transducer ringing. The device is also designed so that it does not have to rely on high-speed analogue to digital converters (ADC) and intensive digital signal processing, so could be implemented using voltage comparators and low-cost microcontrollers. Full article