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A 1 GS/s 12-Bit Pipelined/SAR Hybrid ADC in 40 nm CMOS Technology
Open AccessArticle

A 12-Bit 200 MS/s Pipelined-SAR ADC Using Back-Ground Calibration for Inter-Stage Gain

National ASIC system engineering research center, Southeast University, Nanjing 210096, China
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Electronics 2020, 9(3), 507; https://doi.org/10.3390/electronics9030507
Received: 18 February 2020 / Revised: 17 March 2020 / Accepted: 17 March 2020 / Published: 19 March 2020
(This article belongs to the Special Issue Analog/Digital Mixed Circuit and RF Transceiver Design)
A 12-bit 200 MS/s pipelined successive-approximation-register (SAR) analogue-to-digital-converter (ADC) implemented in 40 nm CMOS is presented. Such an ADC consists of two asynchronous SAR ADCs and a dynamic amplifier, which consumes a static power of 1.2 mW (the total power is 8 mW) and occupies an area of 0.046 mm2. The inter-stage gain is affected by the parasitic capacitance in SAR ADCs as well as the gain of the dynamic amplifier, which is variable with respect to process-voltage-temperature (PVT). A background calibration of the inter-stage gain is proposed to adjust the inter-stage gain and to track the PVT variables. The measurement results show that, with calibration, the spurious-free-dynamic-range (SFDR) and signal-to-noise-and-distortion-ratio (SINAD) can be improved from 68 dB and 61 dB to 78 dB and 63 dB, respectively. The dynamic performance was stable under different VT conditions. View Full-Text
Keywords: pipelined-SAR ADC; background calibration; inter-stage Gain; dynamic amplifier pipelined-SAR ADC; background calibration; inter-stage Gain; dynamic amplifier
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Wu, J.; Wu, J. A 12-Bit 200 MS/s Pipelined-SAR ADC Using Back-Ground Calibration for Inter-Stage Gain. Electronics 2020, 9, 507.

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