# A Low Power Sigma-Delta Modulator with Hybrid Architecture

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## Abstract

**:**

## 1. Introduction

## 2. Improved Σ-Δ Modulator Based on SAR Quantization Structure

_{S}samples the integrator output. After this sampling operation, the SAR ADC quantizes the sampled signal in a binary search mode and outputs it through the Digital to Analogue Converter (DAC)Finally, a residual voltage V

_{RES}is generated on the top plate of the capacitor array.

_{IN}is the input sample signal, and V

_{DAC_OUT}is the output voltage of the DAC. The residual voltage is then processed by a two-stage integrator in the integration phase of the ADC. Meanwhile, the digital output of the current sample V

_{DAC_OUT}(k) can be expressed as

_{S}can greatly reduce the requirements for the second-stage integrator.

## 3. The Overall Circuit Design of the Modulator

## 4. Quantizer Circuit Module Analysis and Optimization Design

#### 4.1. Sampling Module

_{S}is connected to a common-mode voltage and the lower plate is connected to the integrator output voltages outp and outn. After sampling the integrator, switch S1 is turned off, and the input signal is sampled by the quantizer. Switch S2 is closed, and the voltage value of the upper plate of the capacitor C

_{S}becomes the sampled voltage values Vin and Vip, and the lower plate is suspended. By combining the sampling structure of the input signal with the sampling structure of the output of the integrator, the quantizer sampling circuit is formed as shown in Figure 4.

#### 4.2. SAR Comparator Module

## 5. Integrator Circuit Module Analysis and Optimization Design

#### 5.1. Design of Transconductance Operational Amplifier Circuit

#### 5.2. Design of Reference Voltage Source

_{2}is formed by connecting four VT

_{1}in parallel to ensure the proportion.

## 6. Pre-Circuit Simulation and Verification

## 7. Layout Design

^{2}and the core area is 966 × 748 µm

^{2}.

## 8. Chip Testing and Comparison of Previous Works

## 9. Conclusions

## Author Contributions

## Funding

## Acknowledgments

## Conflicts of Interest

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**Figure 3.**Modulator timing diagram. Where φs is the quantization sampling clock, φd is the quantization conversion clock and Clkc is the comparison clock of the successive approximation register (SAR) comparator [26].

**Figure 13.**Modulator chip layout, where (1) is the multiplexed sampled capacitor array, (2) is the 2nd-order integrator, (3) is the comparator and (4) is the power supply.

**Figure 14.**Output power spectrum of the modulator at different input frequencies. (

**a**) Spectrum output of the modulator at 23 K input frequency. (

**b**) Spectrum output of the modulator at 13 K input frequency. (

**c**) Spectrum output of the modulator at 5.1 K input frequency.

**Figure 15.**Measured relationship between input signal frequency and signal to noise distortion ratio (SNDR).

Name | Representative Significance | Name | Representative Significance |
---|---|---|---|

RESET | Modulator reset signal | CLK | Total clock input signal |

outn0 | Negative feedforward of integrator | VREFP | Voltage reference |

outp0 | Integrator forward feed | VCM | Common-mode voltage |

VIN | Negative input signal | VREFN | Terminal voltage at ground |

VIP | Positive input signal | Von1 | DAC negative feedback |

B0~B4 | Five-bit quantization | Vop1 | DAC positive feedback |

DATA | Quantization result output clock | vip0 | Negative input of integrator |

SARIN | Comparator negative signal | vin0 | Positive input of integrator |

SAROUT | Positive signal of comparator | clk2p | Integrator integrated phase clock |

Power Consumption (mW) | Frequency (MHz) | FOMs (dB) | CMOS Technology (μm) | SNDR (dB) | OSR | AREA (mm^{2}) | |
---|---|---|---|---|---|---|---|

[34] | 14.7 | 8.0 | 172.2 | 0.18 | 105.9 | 128 | - |

[35] | 8.1 | - | - | 0.18 | 81.0 | - | - |

[36] | 6.65 | 960 | 150.7 | 0.028 | - | 48 | 0.015625 |

[37] | 12.7 | 0.64 | 165.0 | 0.35 | - | 320 | 11.48 |

[38] | 475 | 2.5 | - | 0.25 | 100.0 | - | - |

[39] | 18.5 | - | - | 0.65 | 72.3 | - | 0.25 |

[40] | 5 | 256 | 160.4 | 0.13 | 74.4 | 64 | 0.33 |

[41] | 16 | 600 | 166.0 | 0.090 | 78 | 30 | 0.36 |

[42] | 3.2 | 1 | 165.6 | 0.35 | 100.2 | 250 | 3.8 |

This work | 3.65 | 3.2 | 169.4 | 0.18 | 106 | 128 | 0.56 |

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**MDPI and ACS Style**

An, S.; Xia, S.; Ma, Y.; Ghani, A.; See, C.H.; Abd-Alhameed, R.A.; Niu, C.; Yang, R.
A Low Power Sigma-Delta Modulator with Hybrid Architecture. *Sensors* **2020**, *20*, 5309.
https://doi.org/10.3390/s20185309

**AMA Style**

An S, Xia S, Ma Y, Ghani A, See CH, Abd-Alhameed RA, Niu C, Yang R.
A Low Power Sigma-Delta Modulator with Hybrid Architecture. *Sensors*. 2020; 20(18):5309.
https://doi.org/10.3390/s20185309

**Chicago/Turabian Style**

An, Shengbiao, Shuang Xia, Yue Ma, Arfan Ghani, Chan Hwang See, Raed A. Abd-Alhameed, Chuanfeng Niu, and Ruixia Yang.
2020. "A Low Power Sigma-Delta Modulator with Hybrid Architecture" *Sensors* 20, no. 18: 5309.
https://doi.org/10.3390/s20185309