Search Results (39)

This paper presents a numerical investigation of all-optical NAND and XNOR logic gates implemented with a single optically pumped semiconductor optical amplifier integrated into a Mach–Zehnder interferometer (OP-SOA-MZI) at 120 Gb/s. Conventional approaches require two cascaded MZI stages to obtain both logic functions. The present work demonstrates that a single OP-SOA-MZI suffices for both gates under appropriate operating conditions. The quality factor (QF) serves as the primary performance metric. The NAND gate yields a QF of 28.6, while the XNOR gate yields a QF of 18.7. A comparison with the conventional electrically pumped SOA–MZI (EP-SOA–MZI) configuration shows that the OP-SOA–MZI architecture consistently produces higher QF values and exhibits superior tolerance to noise and high-speed operation. This improvement stems from enhanced carrier replenishment and improved phase stability provided by optical pumping. The study further examines the dependence of the QF on five operational parameters: absorption coefficient, pump power, data rate, phase noise, and amplified spontaneous emission noise. The results quantify the parametric sensitivity of each logic gate and establish operating regimes for reliable high-speed performance. Full article

Edge Internet of Things (IoT) blockchain deployments increasingly rely on continuous transaction ingestion from resource-constrained IoT devices to nearby edge gateways over heterogeneous wireless links. In this setting, transient channel noise and packet corruption can inject invalid payloads into the edge processing pipeline and trigger unnecessary buffering, parsing, and, most critically, computationally expensive cryptographic operations such as digital signature verification. This leads to wasted computation, increased latency, and reduced energy efficiency at the edge, particularly under dense IoT traffic. This paper presents an energy-aware and fault-tolerant Quantum-Dot Cellular Automata (QCA)-based integrity pre-filter for IoT-to-edge blockchain transaction ingestion. At the circuit level, we adapt and modify a previously reported fault-tolerant five-input majority gate (MV5) structure and use it as a robust primitive for nanoscale integrity-screening circuits. Building on this modified MV5, we design a set of QCA integrity blocks, including a parity checker, a compact XNOR gate circuit, a parity-bit generation circuit, and a sender-to-channel/receiver nano-communication integrity workflow suitable for early screening of corrupted payloads. Compared with the best previously reported baseline considered in this study, the modified MV5 achieves 76.47% tolerance to single-cell omission defects, corresponding to a 17.47 percentage-point increase and an approximately 29.61% relative improvement over the prior 59% omission-tolerance result, while preserving 100% tolerance against extra-cell deposition defects. At the system level, the proposed circuit is discussed as a potential early screening stage for edge-IoT blockchain transaction ingestion. A bounded analytical model is used to estimate the possible reduction in unnecessary signature-verification workload under assumed corruption and detection conditions. This analysis is not intended as a deployment-level validation; full edge-node implementation, throughput measurement, queueing-delay evaluation, real traffic traces, retransmission behavior, and empirical signature-verification profiling remain future work. The proposed parity/chunk-parity pre-filter is designed for low-cost detection of random transmission-induced corruption and does not replace cryptographic authentication, hashing, digital signatures, CRC-based detection, or blockchain validation. All proposed designs are validated using QCADesigner tools. Full article

Polarity-tunable photocurrents provide an intrinsic decision variable that enables in-sensor computing within a single device, moving beyond simple intensity detection toward next-generation intelligent vision, yet traditional photodetectors are limited by static doping profiles and fixed junction polarities. To overcome this bottleneck, we propose a Te_0.61Se_0.39 nanowire device with polarity-tunable photoresponse for broadband optoelectronic logic operation via photocarrier diffusion under localized light illumination. By simultaneously harnessing temporal (pulse width), spatial (light positions), amplitude (light intensity), and bias, our polarity-tunable devices deterministically realize the four fundamental Boolean logic gates (AND, NAND, XNOR, XOR), with a responsivity of 1.39 A/W and a specific detectivity of 1.75 × 10¹⁰ Jones across the visible to mid-wave infrared spectrum. We further showcased its scalability by constructing a two-layer composite Boolean circuit through the integration of optoelectronic AND and NAND gates. Practical applications in optical encoding/decoding transmission and differential perception highlight its broad functional adaptability. This work establishes a paradigm for broadband polarity devices in low-dimensional nanowires, providing a versatile platform for optoelectronic logic and differential imaging applications. Full article

All-optical logic gates have emerged as a critical technology for enabling broadband, low-loss, and high-speed communication systems, addressing the inherent bandwidth limitations of electronic counterparts. Here, we propose a Y-shaped structure leveraging unidirectional modes in the terahertz regime, which enables the realization of multifunctional all-optical logic gates within the lower- and upper-frequency bandwidth regions, including, but not limited to, AND, OR, NOT, and XNOR gates. Numerical simulations and theoretical analyses confirm that the proposed logic gates exhibit robust one-way propagation characteristics, with electromagnetic signals demonstrating complete immunity to backscattering even in the presence of structural defects. Furthermore, nonlocal effects are found to have a negligible impact on the operational bandwidths of our design. Building upon this Y-shaped configuration, we further develop an all-optical digital logic system (AODLS) capable of supporting bifrequency multi-input and multi-output logic operations. When lower- and upper-frequency signals are injected into separate input ports, their corresponding output signals remain fully independent, eliminating cross-talk and enabling true parallel computation. This dual-band parallel processing capability represents a significant advance over conventional single-band all-optical logic systems, opening new avenues for high-throughput all-optical computing and integrated photonic circuits. Full article

Increasing data rates in optical networks require ultra-fast all-optical logic gates to avoid electro-optic conversion bottlenecks. This work presents a numerical simulation and performance analysis of an all-optical XNOR logic gate operating at 250 Gb/s, implemented using a single quantum-dot semiconductor optical amplifier (QD-SOA) embedded in a Mach–Zehnder interferometer (MZI). Using the QD-SOA’s ultrafast carrier dynamics and high nonlinearity, the gate achieves a quality factor (QF) of 26.30 at 250 Gb/s, corresponding to a theoretical bit-error rate below 10⁻⁹. A systematic numerical investigation examines performance dependence on six critical parameters. Data rate analysis shows that the gate maintains QF > 6 up to 700 Gb/s, with QF = 10.47 at this maximum reliable speed, providing a safety margin of approximately 1.8× above the QF = 6 threshold. Performance degrades progressively thereafter, with QF falling to 5.18 at 800 Gb/s and 0.73 at 1 Tb/s due to finite carrier recovery dynamics. Pulse energy optimization identifies an optimum at 0.20 pJ, beyond which gain saturation and nonlinear effects degrade performance below QF = 6 at 0.40 pJ. Continuous-wave probe power exhibits optimal operation at 0.40 mW, with failure above 0.80 mW. Injection current density analysis establishes an optimal bias at 4 kA/cm², where balanced gain and nonlinearity yield peak performance. Noise tolerance assessment demonstrates operation up to a spontaneous emission factor of 6 and phase noise below 6 × 10⁻¹⁴ rad²/Hz, beyond which signal integrity collapses. This parameter sweep delineates the operational envelope and optimization guidelines for QD-SOA-MZI-based all-optical logic, confirming its potential as a compact core component for future ultra-high-speed optical communication and signal processing systems. Full article

Reconfigurable logic is crucial for future adaptive computing, but is challenging to realize with conventional complementary metal-oxide-semiconductor technology due to the limited field-effect characteristics of the fundamental silicon devices. Two-dimensional materials offer a promising platform, yet enhancing their functional versatility requires novel operational mechanisms. Here, we demonstrate a single WSe₂/h-BN/graphene heterojunction capable of dynamically switching between distinct logic functions—XNOR and IMP (implication gate or “IF-THEN” gate)—simply by modulating the drain-source voltage. At a low bias of 0.3 V, the carrier distribution is governed by capacitive coupling, realizing an XNOR gate. Increasing the bias to 3 V activates Fowler–Nordheim tunneling between the graphene floating gate and the drain, enabling IMP logic operation. The interplay and voltage-induced transition between these two physical mechanisms underpin the device’s multifunctional capability. This work introduces a novel operational strategy for two-dimensional material-based reconfigurable logic, providing a pathway toward compact, adaptive hardware for post-CMOS computing. Full article

The von Neumann architecture faces severe bottlenecks in energy efficiency. Computing-in-Memory (CiM) addresses this by performing computations within memory arrays, yet analog CiM solutions suffer from precision loss and high overhead from analog-to-digital converters and digital-to-analog converters (ADCs/DACs). This paper proposes a novel ADC-free CiM architecture based on Ferroelectric Field-Effect Transistors (FeFETs). Logic circuits (NOR, NAND, XNOR) that store weight vectors within FeFETs were designed. Compared with analog CiM circuits, the FeFETs-CiM circuits proposed in this paper can reduce power consumption by 901.1 times and latency by 272.7 times. Furthermore, the design of 3-bit FeFETs-CiM gates was extended, demonstrating flexible configurability for scalable edge computing applications. Finally, an application specific FeFETs-CiM subtractor for k-nearest neighbor (kNN) distance calculation was designed, which energy consumption is as low as 85.02 fJ/OP and latency is as low as 0.56 ns under 500 MHz operation frequency. The calculation robustness of the FeFETs-CiM kNN distance calculator was ensured by simulating under different process corners and temperatures. The performance improvements owing to the proposed FeFETs-CiM CMOS circuits were evaluated by taking the kNN algorithm as an example, which can ensure the data access reduction by more than 300 times compared to von Neumann architecture. Full article

Semiconductor optical amplifiers (SOAs) are central to the development of ultrafast, low-power all-optical signal processing systems. Their strong nonlinear response, compact size, and compatibility with photonic integration platforms make them key enablers for implementing all-optical logic functions beyond the limitations of electronic switching. This review offers a comprehensive analysis of the principal SOA technologies used in all-optical logic gate implementations, including conventional bulk and quantum well SOAs, quantum dot SOAs (QD-SOAs), photonic crystal SOAs (PhC-SOAs), reflective SOAs (RSOAs), and carrier reservoir SOAs (CR-SOAs). For each architecture, we examine the carrier dynamics, gain recovery mechanisms, saturation behavior, and fabrication considerations, together with their associated nonlinear effects such as cross-gain modulation, cross-phase modulation, and four-wave mixing. We further evaluate reported implementations of key logic operations—AND, NAND, OR, NOR, XOR, and XNOR—highlighting performance trade-offs in terms of speed, extinction ratio, operational power, integration complexity, and scalability. The review concludes with current challenges and emerging research directions aimed at realizing fully integrated, high-speed, and energy-efficient all-optical logic systems based on next-generation SOA technologies. Full article

Recent advancements in nanotechnology have intensified research efforts to address security concerns like hardware trojans and intellectual property (IP) piracy, particularly by exploring novel alternatives to traditional MOSFET devices. Spin-based devices, known for their low power consumption, non-volatility, and seamless integration with silicon substrates, have emerged as promising candidates. This research proposes a novel approach to enhance the security of integrated circuits using spin-based devices known as magnetic tunnel junctions (MTJs). A Non-volatile Polymorphic Logic (NPL) is optimized and designed to perform multiple operations, effectively concealing its true functionality. The analytical studies conducted on the Cadence Virtuoso platform using TSMC 65 nm MOS technology demonstrate the feasibility and efficacy of the proposed approach. The proposed NPL circuit enables polymorphism by allowing the circuit to perform all one- and two-input Boolean logic operations, including NOT, AND/NAND, OR/NOR, and XOR/XNOR, through adjustments of applied keys. This dynamic functionality makes it challenging for attackers to determine the circuit’s true operation. The proposed design exhibits similar timing characteristics for different logic operations, which further complicates the tampering attempts. Additionally, the circuit’s layout is designed to be symmetric, ensuring the execution of all possible operations by the same physical layout. This provides post-manufacturing security from reverse engineering and finds its applications in securing custom IC designs against the evolving landscape of hardware-based threats. Full article

As optical networks continue to evolve toward higher speed and larger capacity, conventional security mechanisms relying on optoelectronic conversion are facing increasing limitations. The optical photonic firewall, as an emerging optical-layer security device, enables direct inspection in the optical domain, making its core technology—All-Optical Pattern Matching (AOPM)—a focal point of current research. This review provides a comprehensive survey of AOPM systems. It first introduces the main components of AOPM, namely symbol matching and system architectures, and analyzes their representative implementations. For low-order modulation formats such as OOK and BPSK, the review highlights matching schemes enabled by semiconductor optical amplifier (SOA) and highly nonlinear fiber (HNLF) logic gates, as well as their potential for reconfigurable extension. Building upon this foundation, the paper focuses on systems for high-order modulation formats including QPSK, 8PSK, and 16QAM, covering dimensionality-reduction-based approaches (e.g., PSA-based phase compression, squarer-based phase multiplication, constellation-mapping-based format conversion), direct symbol matching methods (e.g., phase interference, generalized XNOR, real-time Fourier transform correlation), and reconfigurable designs for multi-format adaptability. Furthermore, the review discusses optimization challenges under non-ideal conditions, such as noise accumulation, phase misalignment, and phase-locking-free operation. Finally, it outlines future directions in robust high-order modulation handling, photonic integration, and AI-driven intelligent matching, offering guidance for the development of optical-layer security technologies. Full article

With the increasing demand for ultrafast optical signal processing, silicon-on-silica (SoS) waveguides with ring resonators have emerged as a promising platform for integrated all-optical logic gates (AOLGs). In this work, we design and simulate a SoS-based waveguide structure, operating at the telecommunication wavelength of 1550 nm, consisting of a circular ring resonator coupled to straight bus waveguides using Lumerical FDTD solutions. The design achieves a high Q-factor of 11,071, indicating low optical loss and strong light confinement. The evanescent coupling between the ring and waveguides, along with optimized waveguide dimensions, enables efficient interference, realizing a complete suite of AOLGs (XOR, AND, OR, NOT, NOR, NAND, and XNOR). Numerical simulations demonstrate robust performance across all gates, with high contrast ratios between 11.40 dB and 13.72 dB and an ultra-compact footprint of 1.42 × 1.08 µm². The results confirm the device’s capability to manipulate optical signals at data rates up to 55 Gb/s, highlighting its potential for scalable, high-speed, and energy-efficient optical computing. These findings provide a solid foundation for the future experimental implementation and integration of SoS-based photonic logic circuits in next-generation optical communication systems. Full article

The performance bottleneck arising from the speed disparity between the CPU and DRAM highlights the inherent limitations of the von Neumann architecture. To address this issue, we propose a PIM architecture based on a 2T DRAM structure. The proposed PIM design performs Boolean operations directly within the 2T DRAM array, thereby minimizing data movement between the CPU and DRAM and effectively alleviating the bottleneck. The 2T DRAM array was implemented using the mixed-mode simulation capability of SILVACO TCAD, and its read, write, and hold operations were successfully verified. Building on this foundation, OR and AND logic operations were realized by modulating the gate voltages of MOSFETs within the 2T DRAM array. To enable XNOR functionality, an auxiliary circuit consisting of three additional MOSFETs was integrated. Furthermore, as the ultimate goal of PIM is to enable memory to perform computational tasks, support for MAC operations becomes essential. To facilitate this, we designed a refresh circuit capable of maintaining multi-state data, which is critical for MAC operations. This circuit, also composed of three MOSFETs, functions as a key component for multi-state data retention within the 2T DRAM array. In summary, we demonstrate the implementation of Boolean logic operations using the 2T DRAM array and a three-MOSFET auxiliary circuit and propose a compact refresh circuit to support MAC operations, advancing the potential of PIM architectures. Full article

The increasing demand for high-performance and low-power hardware in artificial intelligence (AI) applications—such as speech recognition, facial recognition, and object detection—has driven the exploration of advanced memory designs. Convolutional neural networks (CNNs) and deep neural networks (DNNs) require intensive computational resources, leading to significant challenges in terms of memory access time and power consumption. Compute-in-Memory (CIM) architectures have emerged as an alternative by executing computations directly within memory arrays, thereby reducing the expensive data transfer between memory and processor units. In this work, we present a 6T SRAM-based CIM architecture implemented using FinFET technology, aiming to reduce both power consumption and access delay. We explore and simulate three different SRAM cell structures—PLNA (P-Latch N-Access), NLPA (N-Latch P-Access), and SE (Single-Ended)—to assess their suitability for CIM operations. Compared to a reference 10T XNOR-based CIM design, our results show that the proposed structures achieve an average power consumption approximately 70% lower, along with significant delay reduction, without compromising functional integrity. A comparative analysis is presented to highlight the trade-offs between the three configurations, providing insights into their potential applications in low-power AI accelerator design. Full article

This article studies the structure and properties of real-ordered Hilbert spaces, highlighting the roles of the XOR and XNOR logical operators in conjunction with the Yosida and Cayley approximation operators. These fundamental elements are utilized to formulate the Yosida–Cayley Variational Inclusion Problem (YCVIP) and its associated Yosida–Cayley Resolvent Equation Problem (YCREP). To address these problems, we develop and examine several solution methods, with particular attention given to the convergence behavior of the proposed algorithms. We prove both the existence of solutions and the strong convergence of iterative sequences generated under the influence of the aforesaid operators. The theoretical results are supported by a numerical result, demonstrating the practical applicability and efficiency of the suggested approaches. Full article

We propose a high-speed all-optical logic gate design based on silicon racetrack and ring resonators patterned on a silica substrate. The architecture features racetrack resonators at both the input and output, with a central ring resonator enabling the required phase-sensitive interference for logic processing. Logic operations are achieved through the interplay of constructive and destructive interference induced by phase-shifted input beams. Using the finite-difference time-domain (FDTD) method in Lumerical software, we simulate and demonstrate seven fundamental Boolean logic functions, namely XOR, AND, OR, NOT, NOR, NAND, and XNOR, at an operating wavelength of 1.33 µm. The system supports a data rate of 47.94 Gb/s, suitable for ultrafast optical computing. The performance is quantitatively evaluated using the contrast ratio (CR) as the reference metric, with more than acceptable values of 13.09 dB (XOR), 13.84 dB (AND), 13.14 dB (OR), 13.80 dB (NOT), 14.53 dB (NOR), 13.80 dB (NAND), and 14.67 dB (XNOR), confirming strong logic level discrimination. Comparative analysis with existing optical gate designs underscores the advantages of our compact silicon-on-silica structure in terms of speed, CR performance, and integration potential. This study validates the effectiveness of racetrack–ring configurations for next-generation all-optical logic circuits. Full article