Search Results (34)

Reconfigurable logic is crucial for future adaptive computing, but is challenging to realize with conventional complementary metal-oxide-semiconductor technology due to the limited field-effect characteristics of the fundamental silicon devices. Two-dimensional materials offer a promising platform, yet enhancing their functional versatility requires novel operational mechanisms. Here, we demonstrate a single WSe₂/h-BN/graphene heterojunction capable of dynamically switching between distinct logic functions—XNOR and IMP (implication gate or “IF-THEN” gate)—simply by modulating the drain-source voltage. At a low bias of 0.3 V, the carrier distribution is governed by capacitive coupling, realizing an XNOR gate. Increasing the bias to 3 V activates Fowler–Nordheim tunneling between the graphene floating gate and the drain, enabling IMP logic operation. The interplay and voltage-induced transition between these two physical mechanisms underpin the device’s multifunctional capability. This work introduces a novel operational strategy for two-dimensional material-based reconfigurable logic, providing a pathway toward compact, adaptive hardware for post-CMOS computing. Full article

The von Neumann architecture faces severe bottlenecks in energy efficiency. Computing-in-Memory (CiM) addresses this by performing computations within memory arrays, yet analog CiM solutions suffer from precision loss and high overhead from analog-to-digital converters and digital-to-analog converters (ADCs/DACs). This paper proposes a novel ADC-free CiM architecture based on Ferroelectric Field-Effect Transistors (FeFETs). Logic circuits (NOR, NAND, XNOR) that store weight vectors within FeFETs were designed. Compared with analog CiM circuits, the FeFETs-CiM circuits proposed in this paper can reduce power consumption by 901.1 times and latency by 272.7 times. Furthermore, the design of 3-bit FeFETs-CiM gates was extended, demonstrating flexible configurability for scalable edge computing applications. Finally, an application specific FeFETs-CiM subtractor for k-nearest neighbor (kNN) distance calculation was designed, which energy consumption is as low as 85.02 fJ/OP and latency is as low as 0.56 ns under 500 MHz operation frequency. The calculation robustness of the FeFETs-CiM kNN distance calculator was ensured by simulating under different process corners and temperatures. The performance improvements owing to the proposed FeFETs-CiM CMOS circuits were evaluated by taking the kNN algorithm as an example, which can ensure the data access reduction by more than 300 times compared to von Neumann architecture. Full article

Semiconductor optical amplifiers (SOAs) are central to the development of ultrafast, low-power all-optical signal processing systems. Their strong nonlinear response, compact size, and compatibility with photonic integration platforms make them key enablers for implementing all-optical logic functions beyond the limitations of electronic switching. This review offers a comprehensive analysis of the principal SOA technologies used in all-optical logic gate implementations, including conventional bulk and quantum well SOAs, quantum dot SOAs (QD-SOAs), photonic crystal SOAs (PhC-SOAs), reflective SOAs (RSOAs), and carrier reservoir SOAs (CR-SOAs). For each architecture, we examine the carrier dynamics, gain recovery mechanisms, saturation behavior, and fabrication considerations, together with their associated nonlinear effects such as cross-gain modulation, cross-phase modulation, and four-wave mixing. We further evaluate reported implementations of key logic operations—AND, NAND, OR, NOR, XOR, and XNOR—highlighting performance trade-offs in terms of speed, extinction ratio, operational power, integration complexity, and scalability. The review concludes with current challenges and emerging research directions aimed at realizing fully integrated, high-speed, and energy-efficient all-optical logic systems based on next-generation SOA technologies. Full article

Recent advancements in nanotechnology have intensified research efforts to address security concerns like hardware trojans and intellectual property (IP) piracy, particularly by exploring novel alternatives to traditional MOSFET devices. Spin-based devices, known for their low power consumption, non-volatility, and seamless integration with silicon substrates, have emerged as promising candidates. This research proposes a novel approach to enhance the security of integrated circuits using spin-based devices known as magnetic tunnel junctions (MTJs). A Non-volatile Polymorphic Logic (NPL) is optimized and designed to perform multiple operations, effectively concealing its true functionality. The analytical studies conducted on the Cadence Virtuoso platform using TSMC 65 nm MOS technology demonstrate the feasibility and efficacy of the proposed approach. The proposed NPL circuit enables polymorphism by allowing the circuit to perform all one- and two-input Boolean logic operations, including NOT, AND/NAND, OR/NOR, and XOR/XNOR, through adjustments of applied keys. This dynamic functionality makes it challenging for attackers to determine the circuit’s true operation. The proposed design exhibits similar timing characteristics for different logic operations, which further complicates the tampering attempts. Additionally, the circuit’s layout is designed to be symmetric, ensuring the execution of all possible operations by the same physical layout. This provides post-manufacturing security from reverse engineering and finds its applications in securing custom IC designs against the evolving landscape of hardware-based threats. Full article

As optical networks continue to evolve toward higher speed and larger capacity, conventional security mechanisms relying on optoelectronic conversion are facing increasing limitations. The optical photonic firewall, as an emerging optical-layer security device, enables direct inspection in the optical domain, making its core technology—All-Optical Pattern Matching (AOPM)—a focal point of current research. This review provides a comprehensive survey of AOPM systems. It first introduces the main components of AOPM, namely symbol matching and system architectures, and analyzes their representative implementations. For low-order modulation formats such as OOK and BPSK, the review highlights matching schemes enabled by semiconductor optical amplifier (SOA) and highly nonlinear fiber (HNLF) logic gates, as well as their potential for reconfigurable extension. Building upon this foundation, the paper focuses on systems for high-order modulation formats including QPSK, 8PSK, and 16QAM, covering dimensionality-reduction-based approaches (e.g., PSA-based phase compression, squarer-based phase multiplication, constellation-mapping-based format conversion), direct symbol matching methods (e.g., phase interference, generalized XNOR, real-time Fourier transform correlation), and reconfigurable designs for multi-format adaptability. Furthermore, the review discusses optimization challenges under non-ideal conditions, such as noise accumulation, phase misalignment, and phase-locking-free operation. Finally, it outlines future directions in robust high-order modulation handling, photonic integration, and AI-driven intelligent matching, offering guidance for the development of optical-layer security technologies. Full article

With the increasing demand for ultrafast optical signal processing, silicon-on-silica (SoS) waveguides with ring resonators have emerged as a promising platform for integrated all-optical logic gates (AOLGs). In this work, we design and simulate a SoS-based waveguide structure, operating at the telecommunication wavelength of 1550 nm, consisting of a circular ring resonator coupled to straight bus waveguides using Lumerical FDTD solutions. The design achieves a high Q-factor of 11,071, indicating low optical loss and strong light confinement. The evanescent coupling between the ring and waveguides, along with optimized waveguide dimensions, enables efficient interference, realizing a complete suite of AOLGs (XOR, AND, OR, NOT, NOR, NAND, and XNOR). Numerical simulations demonstrate robust performance across all gates, with high contrast ratios between 11.40 dB and 13.72 dB and an ultra-compact footprint of 1.42 × 1.08 µm². The results confirm the device’s capability to manipulate optical signals at data rates up to 55 Gb/s, highlighting its potential for scalable, high-speed, and energy-efficient optical computing. These findings provide a solid foundation for the future experimental implementation and integration of SoS-based photonic logic circuits in next-generation optical communication systems. Full article

The performance bottleneck arising from the speed disparity between the CPU and DRAM highlights the inherent limitations of the von Neumann architecture. To address this issue, we propose a PIM architecture based on a 2T DRAM structure. The proposed PIM design performs Boolean operations directly within the 2T DRAM array, thereby minimizing data movement between the CPU and DRAM and effectively alleviating the bottleneck. The 2T DRAM array was implemented using the mixed-mode simulation capability of SILVACO TCAD, and its read, write, and hold operations were successfully verified. Building on this foundation, OR and AND logic operations were realized by modulating the gate voltages of MOSFETs within the 2T DRAM array. To enable XNOR functionality, an auxiliary circuit consisting of three additional MOSFETs was integrated. Furthermore, as the ultimate goal of PIM is to enable memory to perform computational tasks, support for MAC operations becomes essential. To facilitate this, we designed a refresh circuit capable of maintaining multi-state data, which is critical for MAC operations. This circuit, also composed of three MOSFETs, functions as a key component for multi-state data retention within the 2T DRAM array. In summary, we demonstrate the implementation of Boolean logic operations using the 2T DRAM array and a three-MOSFET auxiliary circuit and propose a compact refresh circuit to support MAC operations, advancing the potential of PIM architectures. Full article

The increasing demand for high-performance and low-power hardware in artificial intelligence (AI) applications—such as speech recognition, facial recognition, and object detection—has driven the exploration of advanced memory designs. Convolutional neural networks (CNNs) and deep neural networks (DNNs) require intensive computational resources, leading to significant challenges in terms of memory access time and power consumption. Compute-in-Memory (CIM) architectures have emerged as an alternative by executing computations directly within memory arrays, thereby reducing the expensive data transfer between memory and processor units. In this work, we present a 6T SRAM-based CIM architecture implemented using FinFET technology, aiming to reduce both power consumption and access delay. We explore and simulate three different SRAM cell structures—PLNA (P-Latch N-Access), NLPA (N-Latch P-Access), and SE (Single-Ended)—to assess their suitability for CIM operations. Compared to a reference 10T XNOR-based CIM design, our results show that the proposed structures achieve an average power consumption approximately 70% lower, along with significant delay reduction, without compromising functional integrity. A comparative analysis is presented to highlight the trade-offs between the three configurations, providing insights into their potential applications in low-power AI accelerator design. Full article

This article studies the structure and properties of real-ordered Hilbert spaces, highlighting the roles of the XOR and XNOR logical operators in conjunction with the Yosida and Cayley approximation operators. These fundamental elements are utilized to formulate the Yosida–Cayley Variational Inclusion Problem (YCVIP) and its associated Yosida–Cayley Resolvent Equation Problem (YCREP). To address these problems, we develop and examine several solution methods, with particular attention given to the convergence behavior of the proposed algorithms. We prove both the existence of solutions and the strong convergence of iterative sequences generated under the influence of the aforesaid operators. The theoretical results are supported by a numerical result, demonstrating the practical applicability and efficiency of the suggested approaches. Full article

We propose a high-speed all-optical logic gate design based on silicon racetrack and ring resonators patterned on a silica substrate. The architecture features racetrack resonators at both the input and output, with a central ring resonator enabling the required phase-sensitive interference for logic processing. Logic operations are achieved through the interplay of constructive and destructive interference induced by phase-shifted input beams. Using the finite-difference time-domain (FDTD) method in Lumerical software, we simulate and demonstrate seven fundamental Boolean logic functions, namely XOR, AND, OR, NOT, NOR, NAND, and XNOR, at an operating wavelength of 1.33 µm. The system supports a data rate of 47.94 Gb/s, suitable for ultrafast optical computing. The performance is quantitatively evaluated using the contrast ratio (CR) as the reference metric, with more than acceptable values of 13.09 dB (XOR), 13.84 dB (AND), 13.14 dB (OR), 13.80 dB (NOT), 14.53 dB (NOR), 13.80 dB (NAND), and 14.67 dB (XNOR), confirming strong logic level discrimination. Comparative analysis with existing optical gate designs underscores the advantages of our compact silicon-on-silica structure in terms of speed, CR performance, and integration potential. This study validates the effectiveness of racetrack–ring configurations for next-generation all-optical logic circuits. Full article

For data-intensive applications like edge AI and image processing, we present a new reconfigurable 8T SRAM-based in-memory computing (IMC) macro designed for high-performance and energy-efficient operation. This architecture mitigates von Neumann limitations through numerous major breakthroughs. We built a new architecture with an adjustable capacitance array to substantially increase the multiply-and-accumulate (MAC) engine’s accuracy. It achieves 10–20 TOPS/W and >95% accuracy for 4–10-bit operations and is robust across PVT changes. By supporting binary and ternary neural networks (BNN/TNN) with XNOR-and-accumulate logic, a dual-mode inference engine further expands capabilities. With sub-5 ns mode switching, it can achieve up to 30 TOPS/W efficiency and >97% accuracy. In-memory Hamming error correction is implemented directly using integrated XOR circuitry. This technique eliminates off-chip ECC with >99% error correction and >98% MAC accuracy. Machine learning-aided co-optimization ensures sense amplifier dependability. To ensure CMOS compatibility, the macro may perform Boolean logic operations using normal 8T SRAM cells. Comparative circuit-level simulations show a 31.54% energy efficiency boost and a 74.81% delay reduction over other SRAM-based IMC solutions. These improvements make our macro ideal for real-time AI acceleration, cryptography, and next-generation edge computing, enabling advanced compute-in-memory systems. Full article

Microring resonators, known for their compact size, wavelength selectivity, and high-quality factor, enable efficient light manipulation, making them ideal for photonic logic applications. This paper presents the design and simulation of seven fundamental all-optical logic gates—XOR, AND, OR, NOT, NOR, NAND, and XNOR—using a seven-microring silicon-on-silica waveguide. Operating at the standard telecommunication wavelength of 1.55 µm, the proposed design exploits constructive and destructive interferences caused by phase changes in the input optical beams to perform logic operations. Numerical simulations, conducted using Lumerical FDTD Solutions, validate the performance of the logic gates, with the contrast ratio (CR) as the primary evaluation metric. The proposed design achieves CR values of 14.04 dB for XOR, 15.14 dB for AND, 15.85 dB for OR, 13.42 dB for NOT, 12.02 dB for NOR, 12.75 dB for NAND, and 14.10 dB for XNOR, significantly higher than those reported in previous works. This results in a data rate of 199.8 Gb/s, facilitated by a compact waveguide size of 1.30 × 1.35 μm². These results highlight the potential of silicon photonics and microring resonators in enabling high-performance, energy-efficient, and densely integrated optical computing and communication systems. Full article

All-optical encoders and comparators are essential components for high-speed optical computing, enabling ultra-fast data processing with minimal latency and low power consumption. This paper presents a numerical analysis of an all-optical encoder and comparator architecture operating at 120 Gb/s, based on carrier reservoir semiconductor optical amplifier-assisted Mach–Zehnder interferometers (CR-SOA-MZIs). Building upon our previous work on all-optical arithmetic circuits, this study extends the application of CR-SOA-MZI structures to implement five key logic operations between two input signals (A and B): $\overline{\mathrm{A}}\mathrm{B}$, $\mathrm{A}\overline{\mathrm{B}}$, AB (AND), $\overline{\mathrm{A}}\hspace{0.17em}\overline{\mathrm{B}}$ (NOR), and AB + $\overline{\mathrm{A}}\hspace{0.17em}\overline{\mathrm{B}}$ (XNOR). The performance of these logic gates is evaluated using the quality factor (QF), yielding values of 17.56, 17.04, 19.05, 10.95, and 8.33, respectively. We investigate the impact of critical design parameters on the accuracy and stability of the logic outputs, confirming the feasibility of high-speed operation with robust signal integrity. These results support the viability of CR-SOA-MZI-based configurations for future all-optical logic circuits, offering promising potential for advanced optical computing and next-generation photonic information processing systems. Full article

With the increasing demand for efficient deep learning models in resource-constrained environments, Binary Neural Networks (BNNs) have emerged as a promising solution due to their ability to significantly reduce computational complexity while maintaining accuracy. Their integration into embedded and edge computing systems is essential for enabling real-time AI applications in areas such as autonomous systems, industrial automation, and intelligent security. Deploying BNN on FPGA using RISC-V, rather than directly deploying the model on FPGA, sacrifices detection speed but, in general, reduces power consumption and on-chip resource usage. The AI-extended RISC-V core is capable of handling tasks beyond BNN inference, providing greater flexibility. This work utilises the lightweight Zero-Riscy core to deploy a BNN on FPGA. Three custom instructions are proposed for convolution, pooling, and fully connected layers, integrating XNOR, POPCOUNT, and threshold operations. This reduces the number of instructions required per task, thereby decreasing the frequency of interactions between Zero-Riscy and the instruction memory. The proposed solution is evaluated on two case studies: MNIST dataset classification and an intrusion detection system (IDS) for in-vehicle networks. The results show that for MNIST inference, the hardware resources required are only 9% of those used by state-of-the-art solutions, though with a slight reduction in speed. For IDS-based inference, power consumption is reduced to just 13% of the original, while resource usage is only 20% of the original. Although some speed is sacrificed, the system still meets real-time monitoring requirements. Full article

In this article, we introduce and study a generalized Cayley variational inclusion problem incorporating XOR and XNOR operations. We establish an equivalent fixed-point formulation and demonstrate the Lipschitz continuity of the generalized Cayley approximation operator. Furthermore, we analyze the existence and convergence of the proposed problem using an implicit iterative algorithm. The iterative algorithm and numerical results presented in this study significantly enhance previously known findings in this domain. Finally, a numerical result is provided to support our main result and validate the proposed algorithm using MATLAB programming. Full article