Energy-Efficient Architectures and Memory Innovations for High-Performance Computing and Distributed Systems

A special issue of Electronics (ISSN 2079-9292). This special issue belongs to the section "Circuit and Signal Processing".

Deadline for manuscript submissions: 15 April 2026 | Viewed by 974

Special Issue Editor

School of Integrated Circuits, Peking University, Beijing 100084, China
Interests: neuromorphic computing; homimorphic computing; computer architecture; artificial intelligence security; compute in memory

Special Issue Information

Dear Colleagues,

With the rapid advancement of datasets and artificial intelligence, there is a growing need to design highly efficient hardware architectures to enhance performance. Several promising research directions include the following:

In/Near-Memory Processing: Currently, the performance of most applications is limited by data transfer bottlenecks. Moving computer units inside or closer to memory can significantly mitigate memory-bound issues and improve efficiency.

Software–Hardware Co-Design: By tightly integrating software algorithms with hardware capabilities, it is possible to optimize performance and energy efficiency. This approach involves designing hardware that is specifically tailored to the requirements of AI workloads, while simultaneously developing software that can fully leverage the hardware's unique features.

Dr. Ling Liang
Guest Editor

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Keywords

  • in/near-memory processing
  • software–hardware co-design
  • hardware architecture

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Published Papers (1 paper)

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Research

14 pages, 3081 KB  
Article
Design of Ferroelectric Field-Effect Transistor (FeFET)-Based Computing-in-Memory Architecture with Energy-Efficient and Low Latency for Edge AI Computing
by Chengyu He, Wei Li, Jianjun Li, Qiquan Li, Zhiang Xie and Tao Du
Electronics 2026, 15(4), 841; https://doi.org/10.3390/electronics15040841 - 16 Feb 2026
Viewed by 591
Abstract
The von Neumann architecture faces severe bottlenecks in energy efficiency. Computing-in-Memory (CiM) addresses this by performing computations within memory arrays, yet analog CiM solutions suffer from precision loss and high overhead from analog-to-digital converters and digital-to-analog converters (ADCs/DACs). This paper proposes a novel [...] Read more.
The von Neumann architecture faces severe bottlenecks in energy efficiency. Computing-in-Memory (CiM) addresses this by performing computations within memory arrays, yet analog CiM solutions suffer from precision loss and high overhead from analog-to-digital converters and digital-to-analog converters (ADCs/DACs). This paper proposes a novel ADC-free CiM architecture based on Ferroelectric Field-Effect Transistors (FeFETs). Logic circuits (NOR, NAND, XNOR) that store weight vectors within FeFETs were designed. Compared with analog CiM circuits, the FeFETs-CiM circuits proposed in this paper can reduce power consumption by 901.1 times and latency by 272.7 times. Furthermore, the design of 3-bit FeFETs-CiM gates was extended, demonstrating flexible configurability for scalable edge computing applications. Finally, an application specific FeFETs-CiM subtractor for k-nearest neighbor (kNN) distance calculation was designed, which energy consumption is as low as 85.02 fJ/OP and latency is as low as 0.56 ns under 500 MHz operation frequency. The calculation robustness of the FeFETs-CiM kNN distance calculator was ensured by simulating under different process corners and temperatures. The performance improvements owing to the proposed FeFETs-CiM CMOS circuits were evaluated by taking the kNN algorithm as an example, which can ensure the data access reduction by more than 300 times compared to von Neumann architecture. Full article
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