Search Results (33)

Multiplication is an arithmetic operation that has a significant impact on the performance of several real-life applications such as digital signals, image processing, and machine learning. The main concern of electronic system designers is energy optimization with minimal penalties in terms of speed and area for designing portable devices. In this work, a very-large-scale integration (VLSI) design and delay/area performance comparison of array, Wallace tree, and radix-4 Booth multipliers was performed. This study employs different word lengths, with an emphasis on the design of floating-point multipliers. All multiplier circuits were designed and synthesized using Alliance open-source tools in 350 nm process technology with the minimum delay constraint. The findings indicate that the array multiplier has the highest delay and area for all the multiplier sizes. The Wallace multiplier exhibited the lowest delay in the mantissa multiplication of single-precision floating-point numbers. However, no significant difference was observed when compared with the double-precision floating-point multipliers. The Wallace multiplier uses the lowest area in both the single- and double-precision floating-point multipliers. Full article

An approximate compact model was developed to provide a convenient method of exploring the initial design space when investigating the performance of micro-electronic devices such as nano-scaled piezoelectronic transistors, where fast ball-park estimates can be very helpful. First of all, the compact model was verified by comparing its predictions with those of accurate axi-symmetric finite element analysis (FEA) using special boundary and interface conditions that enable the replication of the analytical model behaviour. Verification is achieved for a radio frequency (RF) switch and a smaller very-large-scale integrated (VLSI) device, where percentage differences between the compact and FEA model predictions are of the order 10⁻⁴ for the RF switch and 10⁻⁵ for the VLSI device. This confirms the consistency of complex property data (especially electro-thermo-elastic constants) and geometrical parameter input to both types of models and convincingly demonstrates that the analytical models and FEA for the two devices have been implemented correctly. A second type of boundary and interface condition is also used that is designed to replicate the actual behaviour of the devices in practice. The boundary and interface constraints applied for the verification procedure are relaxed so that there is perfect interface bonding between layers. For this unconstrained case, the resulting deformation is very complex, involving both bending effects and edge effects arising from property mismatches between neighbouring layers. The results for the RF switch show surprisingly good agreement between the predictions of the analytical and FEA results, provided the thickness of the piezoelectric layer is not too thick, implying that the analytical model should help to reduce the parameter design space for such devices. However, for the VLSI device, our results indicate that the compact model leads to much larger errors. For such systems, the compact model is unlikely to be able to reliably reduce the parameter design space, implying that accurate FEA will then need to be used. Full article

This research presents a sleep posture monitoring system designed to assist the elderly and patient attendees. Monitoring sleep posture in real time is challenging, and this approach introduces hardware-based edge computation methods. Initially, we detected the postures using minimally optimized sensing modules and fusion techniques. This was achieved based on subject (human) data at standard and adaptive levels using posture-learning processing elements (PEs). Intermittent posture evaluation was performed with respect to static and adaptive PEs. The final stage was accomplished using the learned subject posture data versus the real-time posture data using posture classification. An FPGA-based Hierarchical Binary Classifier (HBC) algorithm was developed to learn and evaluate sleep posture in real time. The IoT and display devices were used to communicate the monitored posture to attendant/support services. Posture learning and analysis were developed using customized, reconfigurable VLSI architectures for sensor fusion, control, and communication modules in static and adaptive scenarios. The proposed algorithms were coded in Verilog HDL, simulated, and synthesized using VIVADO 2017.3. A Zed Board-based field-programmable gate array (FPGA) Xilinx board was used for experimental validation. Full article

Side-channel attacks (SCAs) are powerful techniques used to recover keys from electronic devices by exploiting various physical leakages, such as power, timing, and heat. Although heat is one of the less frequently analyzed channels due to the high noise associated with thermal traces, it poses a significant and growing threat to the security of very large-scale integrated (VLSI) microsystems, particularly system in package (SiP) technologies. Thermal side-channel attacks (TSCAs) exploit temperature variations, risking not only hardware damage from excessive heat dissipation but also enabling the extraction of sensitive data, like cryptographic keys, by observing thermal patterns. This dual threat underscores the need for a synergistic approach to thermal management and security in designing integrated microsystems. In response, this paper presents a novel approach that improves the early detection of abnormal thermal fluctuations in SiP designs, preventing cybercriminals from exploiting such anomalies to extract sensitive information for malicious purposes. Our approach employs a new concept called Thermal Digital Twin (TDT), which integrates two previously separate methods and techniques, resulting in successful outcomes. It combines the gradient direction sensor scan (GDSSCAN) to capture thermal data from the physical field programmable gate array (FPGA), which guarantees rapid thermal scan with a measurement period that could be close to $10 \mathsf{\mu }\mathrm{s},$ a resolution of ${0.5 }^{\circ }$C, and a temperature range from −${40 }^{\circ }$C to ${140 }^{\circ }$C; once the data are transmitted in real time to a Digital Twin created in COMSOL Multiphysics^® 6.0 for simulation using the Finite Element Method (FEM), the real time required by the CPU to perform all the necessary calculations can extend to several seconds or minutes. This integration allows for a detailed analysis of thermal transfer within the SiP model of our FPGA. Implementation and simulations demonstrate that the Thermal Digital Twin (TDT) approach could reduce the risks associated with TSCA by a significant percentage, thereby enhancing the security of FPGA systems against thermal threats. Full article

The proliferation of battery-operated end-user electronic devices due to technological advancements, especially in medical image processing applications, demands low power consumption, high-speed operation, and efficient coding. The design of these devices is centered on the Application-Specific Integrated Circuits (ASIC), General Purpose Processors (GPP), and Field Programmable Gate Array (FPGA) frameworks. The need for low-power functional blocks arises from the growing demand for high-performance computational units that are part of high-speed processors operating at high clock frequencies. The operational speed of the processor is determined by the computational unit, which is the workhorse of high-speed processors. A novel approach to integrating Very Large-Scale Integration (VLSI) ASIC design and the concepts of low-power VLSI compatible with medical image compression was embraced in this research. The focus of this study was the design, development, and implementation of a Power Delay Product (PDP) optimized computational unit targeted for medical image compression using ASIC design flow. This stimulates the research community’s quest to develop an ideal architecture, emphasizing on minimizing power consumption and enhancing device performance for medical image processing applications. The study uses area, delay, power, PDP, and Peak Signal-to-Noise Ratio (PSNR) as performance metrics. The research work takes inspiration from this and aims to enhance the efficiency of the computational unit through minor design modifications that significantly impact performance. This research proposes to explore the trade-off of high-performance adder and multiplier designs to design an ASIC-based computational unit using low-power techniques to enhance the efficiency in power and delay. The computational unit utilized for the digital image compression process was synthesized and implemented using gpdk 45 nm standard libraries with the Genus tool of Cadence. A reduced PDP of 46.87% was observed when the image compression was performed on a medical image, along with an improved PSNR of 5.89% for the reconstructed image. Full article

Security and privacy concerns pose significant obstacles to the widespread adoption of IoT technology. One potential solution to address these concerns is the implementation of cryptographic protocols on resource-constrained IoT edge nodes. However, the limited resources available on these nodes make it challenging to effectively deploy such protocols. In cryptographic systems, finite-field multiplication plays a pivotal role, with its efficiency directly impacting overall performance. To tackle these challenges, we propose an innovative and compact bit-serial systolic layout specifically designed for Montgomery multiplication in the binary-extended field. This novel multiplier structure boasts regular cell architectures and localized communication connections, making it particularly well suited for VLSI implementation. Through a comprehensive complexity analysis, our suggested design demonstrates significant improvements in both area and area–time complexities when compared to existing competitive bit-serial multiplier structures. This makes it an ideal choice for cryptographic systems operating under strict area utilization constraints, such as resource-constrained IoT nodes and tiny embedded devices. Full article

Memristors have garnered considerable attention within the scientific community as devices for emerging construction of Very Large Scale Integration (VLSI) systems. Owing to their inherent properties, they appear to be promising candidates for pivotal components in computational architectures, offering alternatives to the conventional von Neumann architectures. This work has focused on exploring potential applications of Self-Directed Channel (SDC) memristors as novel RRAM memory cells. The introductory section of the study is dedicated to evaluating the repeatability of the tested memristors. Subsequently, a detailed account of the binary programming testing process for memristors is provided, along with illustrative characteristics depicting the impact of programming pulses on a memory cell constructed from a memristor. A comprehensive data analysis was then conducted, comparing memristors with varying types of doping. The results revealed that SDC memristors exhibit a high level of switching, certainty between the Low Resistance State (LRS) and High Resistance State (HRS), suggesting their capability to facilitate the storage of multiple bits within a single memory cell. Full article

The growing popularity of edge computing goes hand in hand with the widespread use of systems based on artificial intelligence. There are many different technologies used to accelerate AI algorithms in end devices. One of the more efficient is CMOS technology thanks to the ability to control the physical parameters of the device. This article discusses the complexity of the semiconductor implementation of TinyML edge systems in relation to various criteria. In particular, the influence of the model parameters on the complexity of the system is analyzed. As a use case, a CMOS preprocessor device dedicated to detecting heart rate in wearable devices is used. The authors use the current and weak inversion operating modes, which allow the preprocessor to be powered by cells of the human energy harvesting class. This work analyzes the influence of tuning hyperparameters of the learning process on the performance of the final device. This article analyzes the relationships between the model parameters (accuracy and neural network size), input data parameters (sampling rates) and CMOS circuit parameters (circuit area, operating frequency and power consumption). Comparative analyses are performed using TSMC 65 nm CMOS technology. The results presented in this article may be useful to direct this work with the model in terms of the final implementation as the integrated circuit. The dependencies summarized in this work can also be used to initially estimate the costs of the hardware implementation of the model. Full article

There is always a need for low-power, area-efficient VLSI (Very Large-Scale Integration) design and this need is increasing day by day. However, conventional design methods based on Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) devices and Complementary Metal-Oxide-Semiconductor Transistor (CMOS) technology cannot meet the performance requirements. The memristor, as a promising computing and memory integration device, offers a new research idea for conventional logic circuit structure and architecture innovation, given its non-volatility, scalability, low power consumption, fast switching speed, etc. This paper proposes a brief overview of the characteristics and current status of memristor-based logic circuits and analyzes their applications in numerical expression and memory. The benefits and drawbacks of various analog logic circuit structures are summarized and compared. In addition, some solution strategies for these issues are presented. Finally, this paper offers prospects for the applications of memristors in the logic implementation of large-scale memristor arrays, the novel structure of in-memory computing, and neural network computing. Full article

The theory and application of cellular automata (CA) for a stream cipher-based encryption principle are presented in this study. Certain fundamental transformations are developed based on CA theory regarding decentralized computation for modeling different system’s behavior. The changes governing state transitions rely on simple evolution rules, which can easily be translated into functions using logic operators. A class of linear hybrid cellular automata (LHCA) based on rules 90 and 150 is used to implement these functions. Symmetric key systems theory is the foundation of the suggested algorithm. The algorithm functions use the proprieties provided by the LHCA evolution in order to convert plain text into cipher text and vice versa, in each case starting from the same initial state of the system and performing the same number of steps for each operation. Cellular automata’s parallel information processing property, in addition to their regular and dynamical structure, makes hardware implementation of such schemes best suited for VLSI implementation. Testing of the proposed algorithm was performed by developing both software and hardware solutions. Hardware implementation of the presented cryptosystem was developed using VHDL hardware description language and a FPGA device (XILINX Spartan3E XC3S500E). Design and software simulations have been carried out using the C# programming language. Full article

Reliability is a fundamental requirement in microprocessors that guarantees correct execution over their lifetimes. The reliability-related design rules depend on the process technology and device operating conditions. To meet reliability requirements, advanced process nodes impose challenging design rules, which place a major burden on the VLSI implementation flow because they impose severe physical constraints. This paper focuses on electromigration (EM), one of the critical factors affecting semiconductor reliability. EM is the aging process of on-die wires in integrated circuits (ICs). Traditionally, EM issues have been handled at the physical design level, which enforces reliability rules using worst-case scenario analysis to detect and solve violations. In this paper, we offer solutions that exploit architectural characteristics to reduce EM impact. The use of architectural methods can simplify EM solutions, and such methods can be incorporated with standard physical-design-based solutions to enhance current methods. Our comprehensive physical simulation results show that, with minimal area, power, and performance overhead, the proposed solution can relax EM design efforts and significantly extend a microprocessor’s lifetime. Full article

As technology scales down, digital VLSI circuits are prone to many manufacturing defects. These defects may result in functional and delay-related circuit failures. The number of test escapes grows when technology is downscaled. Small delay defects (SDDs) and hidden delay defects (HDDs) are of critical importance in industries today since they are the source of most test escapes and reliability problems. Improving test quality and creating new test methods, algorithms, and test designs requires a comprehensive study of these delay defects. This article reviews the effect and impact of SDD and HDD in logic circuits. It also analyzes the relevant fault models, automatic test pattern generation (ATPG) methods, faster-than-at-speed testing (FAST), cell-aware (CA) based delay tests, test quality metrics, diagnosis of SDDs and HDDs, and commercially available Electronic Design Automation (EDA) tools. Based on the analysis, the benefits and drawbacks of several accessible approaches are addressed. Full article

This research work presents a thorough analysis of Traditional Organic Solar Cell (TOSC) and novel designed Inverted OSC (IOSC) using Bulk Hetero-Junction (BHJ) structure. Herein, 2D photovoltaic device models were used to observe the results of the semiconducting Single Wall Carbon Nanotube (s-SWCNT):C₆₀-based organic photovoltaic. This work has improved the BHJ photodiodes by varying the active layer thickness. The analysis has been performed at various active layer thicknesses from 50 to 300 nm using the active material s-SWCNT:C₆₀. An analysis with various parameters to determine the most effective parameters for organic photovoltaic performance has been conducted. As a result, it has been established that IOSC has the maximum efficiency of 10.4%, which is higher than the efficiency of TOSC (9.5%). In addition, the active layer with the highest efficacy has been recorded using this material for both TOSC and IOSC Nano Photodiodes (NPDs). Furthermore, the diode structure and geometrical parameters have been optimized and compared to maximize the performance of photodiodes. Full article

A complete comparison for 14 nm FinFET and NWFET with stacked nanowires was carried out. The electrical and thermal performances in two device structures were analyzed based on TCAD simulation results. The electro-thermal TCAD models were calibrated to data measured on 30–7 nm FinFETs and NWFETs. The full set of output electrical device parameters I_on, I_off, SS, V_th, and maximal device temperature Tmax was discussed to achieve the optimum VLSI characteristics. Full article

The rapid evolution of Internet of Things (IoT) applications, such as e-health and the smart ecosystem, has resulted in the emergence of numerous security flaws. Therefore, security protocols must be implemented among IoT network nodes to resist the majority of the emerging threats. As a result, IoT devices must adopt cryptographic algorithms such as public-key encryption and decryption. The cryptographic algorithms are computationally more complicated to be efficiently implemented on IoT devices due to their limited computing resources. The core operation of most cryptographic algorithms is the finite field multiplication operation, and concise implementation of this operation will have a significant impact on the cryptographic algorithm’s entire implementation. As a result, this paper mainly concentrates on developing a compact and efficient word-based serial-in/serial-out finite field multiplier suitable for usage in IoT devices with limited resources. The proposed multiplier structure is simple to implement in VLSI technology due to its modularity and regularity. The suggested structure is derived from a formal and systematic technique for mapping regular iterative algorithms onto processor arrays. The proposed methodology allows for control of the processor array workload and the workload of each processing element. Managing processor word size allows for control of system latency, area, and consumed energy. The ASIC experimental results indicate that the proposed processor structure reduces area and energy consumption by factors reaching up to 97.7% and 99.2%, respectively. Full article