Search Results (398)

Remaining useful life (RUL) prediction of power semiconductor devices plays a crucial role in reliability design and predictive maintenance of power control system. This article introduces a data-driven methodology on predicting the RUL of the gate oxide layer in silicon carbide (SiC) MOSFETs. Firstly, a power cycling platform is established to collect the time-varying curves of threshold voltage and construct an aging dataset. Then, the successive variational mode decomposition (SVMD) algorithm is employed to adaptively decompose the signal of gate threshold voltage, helping suppress measurement noise and fluctuations caused by operating conditions while retaining degradation features. Subsequently, a Temporal Convolutional Network (TCN) is adopted to capture temporal dependencies in the degradation sequence, thereby improving the characterization of gate oxide health status assessment. Finally, the extended Kalman particle filter (EKPF) is employed to estimate the degradation state and quantify the associated uncertainty by recursively fusing model predictions with real-time measurements. The proposed method integrates the adaptive signal decomposition capability of SVMD, the temporal feature extraction capability of TCN, and the uncertainty quantification capability of EKPF. Their complementary integration improves prediction accuracy and robustness in gate oxide degradation evaluation for SiC MOSFET. Full article

Single-event burnout (SEB) remains a persistent threat to SiC power MOSFETs in space, yet rapid evaluation of SEB susceptibility without costly heavy-ion campaigns is challenging. This work demonstrates that femtosecond laser two-photon absorption (TPA) can fill that role for a commercial 1200 V SiC MOSFET—provided the laser energy is correctly mapped to heavy-ion linear energy transfer (LET). We derive an equivalent LET model that incorporates the thermal spike effect, giving LET_eq = Γ₁E₀² + Γ₂E₀⁴, which corrects the classical square law at high excitation intensities where it fails. Three ionization-driven failure signatures emerge: drain-to-gate and drain-to-source single-event leakage current (SELC), and SEB. The SEB threshold saturates near 500 V once LET exceeds 25 MeV·cm²/mg—roughly 42% of the device’s 1200 V rating. From these thresholds, we define a safe operating area: below 200 V is safe, 200–600 V risks SELC degradation, and above 600 V carries high SEB risk. Benchmarking against published heavy-ion data shows SEB threshold agreement within 15%, and within 5% at high LET. We stress that the TPA method captures ionization-driven effects only; it does not replicate displacement damage. These results support rapid, laser-based screening of SiC power devices for radiation hardness. Full article

High-output-current boron-doped diamond (B-diamond) metal–oxide–semiconductor field-effect transistors (MOSFETs) with a modulated boron-doped epitaxial layer were fabricated. An intrinsic diamond epitaxial layer was deposited on the single-crystal diamond substrate as a buffer layer, and plasma-enhanced chemical vapor deposition (PECVD) SiO₂ was employed as both the gate dielectric and passivation layer. The boron-doped epitaxial layer has a thickness of approximately 500 nm and a boron concentration in the range of 10¹⁷–10¹⁸ cm⁻³. The B-diamond MOSFETs showed clear p-channel operation, with a maximum output current of −0.18 mA/mm at room temperature. When the temperature was increased to 150 °C, the maximum output current increased to −1.05 mA/mm, while the on-resistance decreased from 413.91 to 12.13 kΩ·mm. The on/off ratio remains approximately 10⁵ over the measured temperature range. In addition, the device exhibited a breakdown voltage of −347 V at a gate-to-drain spacing of 12.5 μm, and the simulation results showed that the peak electric field was mainly concentrated near the drain-side gate edge of the passivation layer. These results indicated that, for the B-diamond MOSFETs, a balanced epitaxial layer thickness and boron concentration were essential for achieving sufficient channel conduction as well as effective gate control ability. Full article

The parameter degradation and failure mechanisms of 1200 V asymmetric trench-type (AT) silicon carbide (SiC) metal oxide semiconductor field-effect transistors (MOSFETs) under various single and repetitive surge currents, with various gate bias voltages (V_GS) of 0 V, −5 V, and −10 V, are systematically investigated in this work. It is indicated that V_GS has no impact on the single surge reliability, with the same maximum single surge current (SSC_max) under different V_GS. However, during repetitive surge stress (90% and 60% SSC_max), the maximum surge cycles have increased as V_GS increases from −10 V to 0 V. It may be caused by the enhancement of channel-assisted leakage conduction, allowing more surge current to flow through the channel. It is concluded from gate capacitance (Cg-Vg) and low-frequency noise (LFN) characterizations that lower V_GS increases SiC/SiO₂ interface defect density, accelerating parameter degradation during single and repetitive surge stress. Both chip and package failures are observed for single and repetitive surge stress. For single surge stress, the device failure has resulted from the melted source Al as the metal erodes and penetrates through the interlayer dielectric and the ohmic contact layer between the source metal and the SiC-doped region, respectively, leading to a three-terminal short circuit. For repetitive surge stress, the device failure has been caused by the penetration of Al metal into the interlayer dielectric, leading to a gate-source short circuit. This comprehensive research provides valuable guidance for enhancing the surge reliability of SiC MOSFETs. Full article

This paper proposes an Active Gate Driver (AGD) for a DC–DC boost converter based on Silicon Carbide (SiC) power devices, in which surge voltage and ringing arise from their fast-switching characteristics. In this work, a practical and simple 4-bit logic AGD was proposed to adjust the gate resistance during the Miller interval of the SiC MOSFET. This helps suppress these effects and lowers the surge voltage and ringing stress on the power device. Experimental results demonstrate that the voltage overshoot decreases from 52 V to 22 V, corresponding to a reduction from 52% to 22% under a 100 V output condition, while the peak drain–source voltage decreases from 152 V to 122 V. The turn-off energy increases from 60.2 µJ to 76.9 µJ due to the slightly reduced switching speed. This trade-off represents the improvement in the comparison between transient suppression and switching loss. In addition, the voltage ringing is significantly attenuated. Although the modified switching strategy slightly increases switching loss, it effectively improves waveform quality and reduces voltage stress. These results confirm that the proposed AGD provides a simple and effective solution for improving the switching robustness and reliability of SiC-based DC–DC boost converters. Full article

In high-step-up ratio converters for portable battery-powered devices, MOSFET switching loss limits efficiency and thermal design. This paper evaluates a multi-stage adaptive gate driver (MS-AGD) after transfer from a 900 V SiC MOSFET high-step-up converter to a 25 V Si MOSFET transformer-based boost circuit. The MS-AGD detects the Miller plateau by differential sensing and controls gate current in four stages through cascode current mirrors. The target-platform comparison combines measured switching waveforms with a temperature-based $\zeta$ coefficient and an apparent $R_{on-effective}$ indicator under a fixed device, load, fixture, pulse sequence, and thermal path. Total switching energy is not determined directly. Tests at 15 frequency points from 23.26 to 125 kHz show that drain-source voltage reaches its valley in about 500 ns with MS-AGD rather than about 1300–1450 ns with fixed-resistor drive and that the MOSFET package-temperature rise is reduced at all tested points by about 25% on average. The fitted apparent thermal-electrical indicator is also lower. These mutually consistent waveform and thermal results indirectly support a reduced turn-on switching-loss contribution while avoiding interpretation of $\zeta$ or apparent $R_{on-effective}$ as direct measurements of total switching loss or instantaneous channel resistance. Full article

Surge reliability is a crucial aspect of silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET) reliability. This study investigates the degradation behavior and mechanisms of switching characteristics in 1.2 kV planar-gate SiC MOSFETs under repetitive surge current. A surge current test platform is established to conduct surge tests on the device, while monitoring the evolution of its switching characteristics. The results indicate that after 4000 surge current cycles, the device’s turn-on delay time (t_d(on)), rise time (t_r), and turn-on loss (E_ON) show no significant changes. In contrast, the turn-off delay time (t_d(off)), fall time (t_f), and turn-off loss (E_OFF) increase by 9%, 7.5%, and 8.3%, respectively. Switching characteristics variations are closely linked to the reduction in threshold voltage (V_TH) and the increase in gate-source capacitance (C_GS) and gate-drain capacitance (C_GD). The degradation of these parameters stems from the accumulation of positive trapped charge in the gate oxide layer above the channel and junction field-effect transistor (JFET) region. The increase in charges results from the combined effects of negative gate bias and cyclic high temperature induced by repetitive surge current. This study provides a theoretical basis for the comprehensive understanding of the impact of surge current on SiC MOSFET performance. Full article

The accelerated global transition toward eco-friendly mobility has necessitated robust decarbonization measures across the maritime sector, with battery-powered electric propulsion ships emerging as a promising alternative. Accordingly, the applicability of silicon carbide (SiC)-based technology to propulsion inverters, a key component of such vessels, is currently under investigation. Although life cycle assessment (LCA) studies comparing conventional silicon (Si)-based and SiC-based inverters have been conducted previously, these analyses neglect realistic operating profiles and load fluctuations, limiting their applicability. Furthermore, life cycle cost assessment (LCCA) integrating real-world operating conditions has rarely been addressed. To address these gaps, this study conducted a comparative LCA and LCCA of Si IGBT and SiC MOSFET inverters for marine electric propulsion systems across three vessel types: a cruise ship, a passenger and car ship, and a recreational boat, incorporating real-world load profiles to evaluate global warming potential (GWP), fossil depletion (FD), and cumulative energy demand (CED). The static LCA results showed negligible differences between inverter types, contributing less than 1% to total impacts. The dynamic LCA demonstrated that SiC MOSFET inverters reduced environmental impacts by approximately 57%, 52%, and 34% for cruise ships, passenger and car ships, and recreational boats, respectively. Despite a 40% higher initial investment cost, SiC inverters achieved payback periods well within vessel lifetimes across all vessel types. These findings support SiC inverters as a sustainable and economically viable solution for ship electrification. Full article

The increasing adoption of electric vehicles (EVs) demands highly efficient bidirectional DC–DC converters capable of seamless energy transfer between the grid and vehicle batteries. This paper introduces a Fixed-Frequency Dual-Active-Bridge (DAB) resonant converter featuring four degrees of freedom, achieved through a combination of triple phase-shift (TPS) modulation and a current-controlled variable inductor (VI). The proposed control strategy aims to minimize conduction and switching losses by simultaneously managing reactive power, RMS current, and soft-switching conditions across wide variations in voltage and power. Unlike conventional phase-shift or variable-frequency modulations, the fixed-frequency operation maintains full zero-voltage switching (ZVS) for the two bridges, and zero-current switching (ZCS) in the bridge that is receiving energy, enhancing overall system reliability and control simplicity. The proposed converter is validated through simulations and experimental results from a SiC MOSFET-based 14 kW prototype operating at 122 kHz, demonstrating peak efficiencies above 97% under both charging and discharging modes. The experimental results confirm that the proposed DAB topology and modulation scheme significantly improve efficiency and controllability, making it a promising solution for next-generation on-board chargers and vehicle-to-grid (V2G) applications. Full article

This paper addresses the challenge of optimally controlling silicon carbide (SiC) metal-oxide-semiconductor field-effect transistors (MOSFETs) to minimize switching losses while simultaneously reducing overshoots and voltage slew rates. A digitally controlled gate current source is used to drive the transistors, and its output waveform is defined by a set of parameters that must be optimized. To this end, a sequential lowest segment extraction (SLSE) method is proposed to identify parameter sets that generate trade-off curves that closely approximate the Pareto frontiers. These curves represent the lowest simultaneously achievable values of either switching loss and current/voltage overshoot, or switching loss and maximum voltage slew rate. The resulting boundary curves demonstrate a total switching loss reduction of up to 60% while maintaining nearly the same overshoot and slew rate values compared to a classical gate driver. The paper concludes with an analysis of the results and a summary of the key findings. Full article

SiC MOSFETs suffer from severe EMI issues due to their high dv/dt and di/dt values as well as the reduced coupling length resulting from their compact design. Conventional magnetic shielding suffers from three major limitations: susceptibility to magnetic saturation, restrictions at high frequencies, and extra parasitic inductance introduced by the shielding material itself. This paper proposes a method that uses eddy currents to mitigate the near-field magnetic radiation. By wrapping the system in an external copper layer without affecting system layout or wiring, external radiation is reduced by 10 times, removing the possibility of magnetic saturation, and reducing parasitic inductance by 10 percent. Compared to traditional magnetic shielding, this solution is cost-effective, and offers enhanced reliability and performance. Full article

This work contains the results of the research carried out on the framework of the design of the resonant power module of DAB. The peculiarity of this device is that it is supposed to be used as part of the basic element of a scalable power storage system, the load of which is an industrial three-phase network. The paper proposes a method of designing such devices based on preliminary analytical calculations and the development of numerical models. This method includes three stages. In the first iteration, the parameters of the resonant CLLC converter. In the second iteration, in the course of performing more accurate calculations and development of numerical models, the output parameters and the adjustment characteristic of the converter are determined, taking into account the specifics of the load. At the third stage, a numerical model of a high-frequency transformer is developed to determine the number of losses in the core and estimate the values of magnetic induction. Full article

To address the turn-off overvoltage challenge arising from the rapid interruption of Low Voltage DC Solid-State Circuit Breakers (SSCBs), this paper proposes a high-precision behavioral modeling method for domestic SiC MOSFETs. The model is constructed based on the physical structure of the device, integrating a modified EKV-based static current model and a voltage-dependent nonlinear parasitic capacitance model described by piecewise functions. Model parameters are efficiently extracted from datasheets and measurement data using a composite optimization strategy combining the Genetic Algorithm and the Levenberg–Marquardt algorithm. The model is implemented in LTspice, and its accuracy in both static and dynamic characteristics is validated by comparing the simulation waveforms with experimental results. Based on the validated model, the turn-off process is subdivided into four distinct stages, with an equivalent circuit established for each. A systematic analysis reveals the intrinsic physical mechanism of the voltage spike and oscillation, which results from interaction among the drive circuit parameters, system parameters, and the nonlinear capacitances of the device. The research outcomes provide effective theoretical guidance and a design tool for simulation modeling, turn-off stress assessment, and snubber circuit optimization for SSCBs utilizing SiC MOSFETs. Full article

This work presents the design of a $\beta$-Ga₂O₃ MOSFET incorporating a P-type Ga₂O₃ buffer layer on a high-thermal-conductivity AlN/SiC composite substrate. The electrical characteristics of the device were simulated using Sentaurus TCAD. Results demonstrate that the integration of the composite substrate effectively mitigates self-heating effects, reducing the peak temperature ($T_{\mathit{max}}$) from 776.5 K to 570.9 K at 300 K, while simultaneously increasing the threshold voltage ($V_{\mathit{th}}$) from −0.35 V to 1.52 V. Through systematic optimization of the P-Ga₂O₃ buffer layer thickness and doping concentration, the device achieves a breakdown voltage ($V_{\mathit{br}}$) of 4781 V, a power figure of merit (PFOM) of 2.18 GW/cm², an $I_{DS}$, on/off ratio of 9.20 × 10⁹, and cut-off/maximum oscillation frequencies ($f_{\mathit{t}}$/$f_{\mathit{max}}$) of 1.29 GHz and 1.40 GHz, respectively. These findings provide a theoretical foundation for developing $\beta$-Ga₂O₃-based power devices with high breakdown voltage, improved thermal conductivity, and low specific on-resistance ($R_{\mathit{on},\mathit{sp}}$). Full article

Bias temperature instability (BTI) degradation is commonly described using empirical power-law kinetics; however, extraction of the time exponent and projection of lifetime remain highly sensitive to baseline definition and data representation. In conventional approaches, the threshold voltage shift is referenced to an initial value that cannot be measured simultaneously with stress, introducing uncertainty that can produce apparent curvature and variability in the extracted exponent. In this work, a baseline-independent linearization method is applied to representative published datasets spanning advanced silicon, SiC MOSFETs, and GaN power devices. By analyzing the measured degradation trajectories directly in a transformed time coordinate, the method removes curvature associated with baseline ambiguity and enables consistent extraction of the effective power-law exponent. Across all material systems examined, the extracted exponent exhibits systematic dependence on applied stress once baseline effects are reduced. This behavior challenges the commonly assumed constant-exponent formulation used in conventional lifetime projections and shows that even modest variations in the exponent can produce large differences in projected time-to-failure. A transformed lifetime representation based on ${\mathrm{T}\mathrm{T}\mathrm{F}}^n$ is introduced, in which the influence of exponent variation is separated from the intrinsic voltage and temperature acceleration of the degradation rate. In this representation, the extracted acceleration parameters become more stable and physically interpretable. This formulation is consistent with standard reliability frameworks, including JEDEC JEP122G, in which the time exponent enters directly into the lifetime expression. These results demonstrate that baseline-independent analysis provides a unified framework for interpreting BTI degradation across disparate semiconductor technologies and suggest that explicit treatment of stress-dependent exponents is required for physically consistent lifetime modeling. Full article