Optimization of Gate Current Profiles for SiC Power MOSFETs with Respect to Switching Loss, Overshoot, and Slew Rate

Abstract

This paper addresses the challenge of optimally controlling silicon carbide (SiC) metal-oxide-semiconductor field-effect transistors (MOSFETs) to minimize switching losses while simultaneously reducing overshoots and voltage slew rates. A digitally controlled gate current source is used to drive the transistors, and its output waveform is defined by a set of parameters that must be optimized. To this end, a sequential lowest segment extraction (SLSE) method is proposed to identify parameter sets that generate trade-off curves that closely approximate the Pareto frontiers. These curves represent the lowest simultaneously achievable values of either switching loss and current/voltage overshoot, or switching loss and maximum voltage slew rate. The resulting boundary curves demonstrate a total switching loss reduction of up to 60% while maintaining nearly the same overshoot and slew rate values compared to a classical gate driver. The paper concludes with an analysis of the results and a summary of the key findings.

1. Introduction

Power semiconductor devices are essential in modern power electronics. They typically operate as switches to efficiently control and transfer large amounts of power, with minimal energy loss. However, like all practical components, they have inherent limitations, such as finite power-handling capabilities, restricted switching speeds, and nonzero on-state and off-state resistances, which lead to power losses, known as conduction losses during the on and off states, and switching losses during state transitions [1].

To mitigate these limitations, various control techniques have been developed to regulate the switching behavior of semiconductor devices. These techniques are usually implemented in gate drivers, which are electronic circuits that receive logic-level signals from the control system and deliver the necessary voltage or current to the control electrode of the switch, ensuring immediate turn-on or turn-off, while safely maintaining the desired state [2]. For example, when insulated-gate bipolar transistors (IGBTs) are considered, three control techniques can be distinguished: passive, open-loop, and closed-loop [3].

Passive control, in its simplest form, relies on two different gate resistors: one is active during turn-on and the other during turn-off [4]. To achieve fast switching transients and thereby minimize switching losses, low-ohmic gate resistors are used. However, this increases electromagnetic interference (EMI) and imposes higher current and voltage stresses on the switches due to the increased slew rates of the transients. Conversely, high-ohmic gate resistors reduce EMI and stress at the cost of slower switching and increased energy loss. Therefore, a compromise is required to meet the circuit performance criteria, which remain limited because of the restricted controllability of the switching waveforms in passive control.

Open-loop control methods utilize switchable gate resistors [5,6,7,8], gate voltages [9,10], or gate current sources [11,12,13,14], each operating at discrete levels of resistance, voltage, or current. The main concept involves dividing the switching transients into smaller time intervals and assigning a specific gate resistor, voltage, or current to each interval. This allows interval-specific control based on a fixed profile [5,6,11,12], an operating point-dependent action [8,15,16], or event-triggered feedback from the switching process [7,10,14,15]. However, despite these strategies, open-loop approaches offer limited adaptability to a wide range of operating conditions.

Closed-loop techniques employ negative feedback to compensate for various nonlinearities as well as dependencies on the operating point and temperature. Both analog [3,17,18,19] and digital [20,21,22,23] approaches are used to exploit one or more feedback signals, such as the collector-emitter voltage, collector current, or their derivatives. Analog control offers the advantage of a higher bandwidth, as it avoids delays introduced by analog-to-digital and digital-to-analog conversions. However, it may suffer from crosstalk issues caused by reverse transfer capacitance and feedback circuits [24]. Digital control, on the other hand, enables finer tuning at the expense of increased delays in the signal paths, limiting its applicability to slower switching transients in real-time systems.

The aforementioned control concepts can be applied to drive silicon carbide (SiC) metal-oxide-semiconductor field-effect transistors (MOSFETs), which are increasingly replacing IGBTs in a wide range of power conversion applications owing to their low switching losses, high breakdown voltages, high switching frequencies, and superior thermal performance [25]. However, high switching speeds can lead to excessive voltage and current overshoots as well as oscillations, which constrain the maximum operating range and degrade the EMI performance of power converters. Consequently, extensive research has been conducted to model the switching dynamics of SiC MOSFETs to develop efficient control strategies [26,27,28,29,30,31]. More recently, programmable multistage gate drivers and variable gate voltage strategies have demonstrated improved switching performance by dynamically adjusting the gate excitation during different switching intervals, thereby reducing oscillations and overshoots without substantially increasing switching losses [32,33]. Likewise, active gate driving and waveform shaping techniques based on variable current control or charge sharing concepts have been proposed to optimize the trade-off between switching energy and transient stresses while maintaining fast switching capability [34,35,36,37].

One approach for achieving the target switching behavior, characterized by reduced switching losses and limited drain-source voltage and drain current overshoots and slew rates, is to determine the optimal gate current profile for driving the switch. These profiles should be identified across a wide range of operating conditions and applied dynamically, depending on the varying system parameters, to ensure compliance with design constraints. Digital control is well suited for this task, as it enables predefined profiles to be stored in a lookup table and generated in response to the input control signals. This approach was utilized in [21,22], where an initial (precalculated) gate current waveform corresponding to the identified operating point was adjusted in real time using an adaptive algorithm to optimize the switching behavior. A similar iterative gate current shaping strategy was employed in [20] to compensate for feedback delays. In [29], a lookup table provided expressions for the timing durations of the switching stages during which gate currents of fixed magnitudes were applied to the device. Depending on the load current, this method achieved up to 46% reduction in switching losses compared to conventional gate drivers (CGDs). Similar savings, up to 49%, are reported in [38], where a 6-bit programmable gate current source with automatic timing control is used to generate three successive pulses of large-small-large amplitudes for both turn-on and turn-off operations. Nevertheless, most existing approaches optimize only selected switching metrics or rely on predefined switching stages and fixed profile structures, whereas a unified optimization of gate current/voltage profiles with simultaneous consideration of switching loss, overshoot, and slew-rate constraints across varying operating conditions remains insufficiently explored in the literature.

This study explores the extent to which two conflicting factors, switching losses and current/voltage overshoots or switching losses and voltage slew rates, can be simultaneously minimized across their full range through digital control using programmable gate current profiles. To the best of our knowledge, such a study relying on simulations of an electrical circuit with a defined SiC MOSFET model has not yet been reported in the literature. Therefore, these findings may offer valuable insights into potential performance improvements over CGDs. As will be shown, these boundaries can be identified by systematically varying two of the multiple parameters that define the gate current profile, demonstrating switching loss reductions of up to 60% while maintaining equivalent overshoot or slew rate compared to a CGD. Because the discrete points forming the boundaries correspond to the optimal gate current profiles, the proposed method also yields parameter sets that can be stored in a lookup table and later used to generate an appropriate gate current waveform depending on the operating conditions.

The remainder of this paper is organized as follows. Section 2 defines the problem. Section 3 and Section 4 detail the methods used to optimize the gate current waveforms for the turn-on and turn-off phases, respectively. Section 5 compares the obtained results with those of the CGD. The final section summarizes the findings and presents the conclusions.

2. Problem Definition

Double-pulse testing (DPT) is a standard method for evaluating the dynamic behavior of power switching devices, such as MOSFETs and IGBTs [39]. In addition to switching characterization, DPT enables the assessment of the body-diode recovery behavior [40].

The DPT circuit shown in Figure 1 was used for the simulations with a PMJX06S 1200V SiC power MOSFET model, which is a custom, physics-based SPICE model provided by an undisclosed manufacturer. The model includes nonlinear $C_{gd}$, package inductances, temperature dependence (with temperature applied via an external node of the model block), and reverse-recovery/body-diode effects. A programmable gate current source $i_p\left(t\right)$ is connected in parallel to two diodes, $D_1$ and $D_2$, which are placed in series with voltage sources $V_{-}$ and $V_{+}$, respectively. This biased parallel clippers configuration ensures that the gate-source voltage of the active transistor (the lower device in Figure 1) remains close within $V_{-}$ to $V_{+}$.

The DC-link capacitor is modeled as an ideal voltage source $V_{DC}$, with the assumption of a sufficiently large capacitance to maintain a constant voltage during switching transients. Its non-ideal behavior is captured through the equivalent series inductance (ESL) and equivalent series resistance (ESR). The parameter values of these elements, along with those of the other circuit components, are summarized in

Table 1. Circuit Elements Used in the DPT Simulations.

Element	Value
Positive voltage source ($V_{+}$)	$18\mathrm{V}$
Negative voltage source ($V_{-}$)	$-5\mathrm{V}$
Passive switch gate resistance (${\widehat{R}}_g$)	$1\Omega$
Active switch gate resistance ($R_g$)	$1\Omega$
Gate-side parasitic inductance ($L_g$)	$15\mathrm{nH}$
Drain-side parasitic inductance ($L_d$)	$2.5\mathrm{nH}$
Source-side parasitic inductance ($L_s$)	$2.5\mathrm{nH}$
Common source parasitic inductance ($L_{cs}$)	$0.2\mathrm{nH}$
Load current loop parasitic inductance ($L_{ac}$)	$35\mathrm{nH}$
DC bus parasitic inductance ($L_{dc}$)	$5\mathrm{nH}$
DC-link capacitor ESL ($L_{ESL}$)	$4\mathrm{nH}$
DC-link capacitor ESR ($R_{ESR}$)	$1\mathrm{m}\Omega$

.

The objective is to determine the optimal gate current source waveform $i_p\left(t\right)$ that minimizes switching losses (denoted as energy losses $E_l$) while simultaneously limiting either the drain current overshoot $I_o$ during turn-on or the drain-source voltage overshoot $V_o$ during turn-off. Optimal waveforms must be identified across a range of operating conditions defined by the DC-link voltage $V_{DC}$, the load current $I_L$, and the MOSFET’s junction temperature T.

The switching losses are calculated according to the IEC definition [41] as

$$E_l={\int }_{{\tilde{t}}_1}^{{\tilde{t}}_2}{v}_{ds}\left(t\right)i_d\left(t\right)dt,$$

(1)

where, in the turn-on case, ${\tilde{t}}_1$ denotes the instant at which the drain current $i_d\left(t\right)$ exceeds 10% of the load current $I_L$, and ${\tilde{t}}_2$ denotes the instant at which the drain-source voltage $v_{ds}\left(t\right)$ falls below 10% of the DC-link voltage $V_{DC}$. In the turn-off case, ${\tilde{t}}_1$ denotes the instant at which $v_{ds}\left(t\right)$ exceeds 10% of $V_{DC}$, whereas ${\tilde{t}}_2$ denotes the instant at which $i_d\left(t\right)$ falls below 10% of $I_L$ (the total switching loss is the sum of the turn-on and turn-off switching losses). To avoid the situations in which ${\tilde{t}}_2$ is detected too early due to parasitic oscillations during switching transients, a threshold of 1% (instead of 10%) is used in this study to detect both ${\tilde{t}}_1$ and ${\tilde{t}}_2$.

Following the idea of using three pulses in [38], the gate current source waveform is defined as

$$i_p\left(t\right)={\displaystyle \sum _{\kappa =1}^5}{I}_{\kappa }\left(u(t-t_{\kappa -1})-u(t-t_{\kappa })\right),$$

(2)

where $I_{\kappa }$ denotes the amplitude of each pulse, which is composed of two Heaviside step functions $u(t-t_{\kappa -1})$ and $u(t-t_{\kappa })$, and the sequence $t_0<t_1<t_2<t_3<t_4<t_5$ determines the timing of the pulses, as illustrated in Figure 2. The first three pulses, defined by $(I_{\kappa },{\Theta }_{\kappa })$, $\kappa =1,2,3$, regulate the turn-on transients of the MOSFET, whereas the last two pulses, defined by $(I_4,{\Theta }_4)$ and $(I_5,{\Theta }_5)$, control the turn-off transients. In contrast to the turn-on phase, the third pulse was omitted during turn-off, as the simulations later showed that it offered no performance improvement.

An 8-bit programmable gate current source is used for the digital driver. Consequently, for the turn-on phase, the gate current amplitudes are defined as $I_{\kappa }=n_{\kappa }{\Delta }_I$, and for the turn-off phase, as $I_{\kappa }=-n_{\kappa }{\Delta }_I$, where $n_{\kappa }\in [0,255]$ are integers, and ${\Delta }_I=2.5/255$ A.

Similarly, the pulse durations are defined as ${\Theta }_{\kappa }=m_{\kappa }{\Delta }_{{\Theta }_{\kappa }}$, where $m_1\in [0,1020]$, $m_2\in [0,256]$, $m_4\in [0,2040]$, and $m_5\in [0,510]$ are integers, with corresponding time steps ${\Delta }_{{\Theta }_1}=0.98$ ns, ${\Delta }_{{\Theta }_2}=1.56$ ns, and ${\Delta }_{{\Theta }_4}={\Delta }_{{\Theta }_5}=0.98$ ns. Parameter $m_3$ is not included in the optimization process because the duration ${\Theta }_3$ of the third pulse is fixed to be sufficiently long for the transients to reach a steady state after the transistor is turned on.

As a result, there are nearly $4^{21}$ and $4^{16}$ unique combinations of the parameters $(n_1,m_1,n_2,m_2,n_3)$ and $(n_4,m_4,n_5,m_5)$ for the turn-on and turn-off cases, respectively. Simulating all of these combinations to obtain $E_l$, $I_o$, and $V_o$ is computationally infeasible. Therefore, strategic considerations must be made to reduce the parameter search space.

3. Turn-On Phase

3.1. Constraining the Search Space

The first step is to examine how the energy loss $E_l$ and drain current overshoot $I_o$ vary with $n_1$, under the condition that $n_2=n_3=n_1$, and with $m_1$ and $m_2$ set to their maximum values. The resulting curves, shown in Figure 3, indicate that the minimum energy loss occurs at the maximum gate current of $n_1=255$. Therefore, $n_1=255$ should be selected if the focus is on reducing $E_l$.

The second step is to evaluate how the duration of the first pulse, ${\Theta }_1=m_1{\Delta }_{{\Theta }_1}$, influences $E_l$ and $I_o$, under the conditions $n_1=255$, $n_2=0$, and a fixed maximum value for the second pulse duration ${\Theta }_2=256{\Delta }_{{\Theta }_2}$. The resulting curves for two different values of $n_3$ are shown in Figure 4. A minimum overshoot is observed at a specific $m_1=m_{1\min }$, which also corresponds to a near-maximum value of $E_l$. When $m_1$ is smaller than $m_{1\min }$ (e.g., $m_1=20$ and 35 in Figure 5), the opening of the transistor is mainly determined by the third pulse, as the duration of the first pulse is too short. Conversely, once $m_1$ exceeds $m_{1\min }$ (e.g., $m_1=43$ and 65 in Figure 5), the influence of the first pulse increases. Beyond a certain upper threshold $m_{1\max }$, both $E_l$ and $I_o$ stabilize at nearly constant values. Further increases in $m_1$ have a negligible impact on $E_l$ and $I_o$, regardless of the second pulse parameters $(n_2,m_2)$, as the first pulse alone is sufficient to turn on the transistor.

After finding $m_{1\min }$ and $m_{1\max }$, the search space for the gate current profile parameters $(n_1,m_1,n_2,m_2,n_3)$ is constrained as follows: $n_1=255$, $m_1\in [m_{1\min }-\Delta m_{1\min },m_{1\max }]$, $n_2\in [0,255]$, $m_2\in [0,m_{2\max }]$, and $n_3=n_1=255$. The term $\Delta m_{1\min }$ ($m_{1\min }>\Delta m_{1\min }>0$) is introduced to explore the cases in which $m_1$ is too small (${\Theta }_1$ is too short) for the transistor to turn on, thereby requiring either the second or third pulse to trigger the switching event. The upper limit $m_{2\max }$ is imposed to prevent an excessive increase in $m_2$, as the simulation results show that beyond this point, a further increase leads to a higher $E_l$ without contributing to a reduction in $I_o$.

3.2. Simulation Results

In our case, the parameters are selected as follows: $n_1=255$, $m_1=[15,16,\dots ,90]$, $n_2=[0,1,\dots ,20]\cup [22,24,\dots ,30]\cup [35,40,\dots ,60]\cup [70,80,\dots ,200]\cup [215,230,245]\cup \left[255\right]$, where step sizes of 1, 2, 5, 10, and 15 are applied to subsequent intervals to reduce the search space at higher $I_2$ values; $m_2=[1,2,\dots ,40]$, and $n_3=255$. These ranges yield a total of 152,000 possible $(n_1,m_1,n_2,m_2,n_3)$ combinations, the simulation results of which are shown as gray points in Figure 6, indicating that simultaneously minimizing both $E_l$ and $I_o$ is not feasible. Instead, the optimal trade-off between these two conflicting objectives is represented by the set of points that form the red boundary in Figure 6. These points should be identified to enable the selection of the most suitable solution based on the specific application requirements.

3.3. Finding the Optimal Trade-Off Curve

Given the distribution of the points in Figure 6, it is possible to extract the lower edge of the cloud, as indicated by the red descending line. This line represents the Pareto frontier (or Pareto curve in the case of two objectives) [42], which contains Pareto-optimal solutions, those for which no improvement in one objective (e.g., energy loss $E_l$) can be made without worsening the other (e.g., current overshoot $I_o$). Therefore, the focus should be on identifying solutions along the Pareto frontier as they offer the best trade-offs without requiring an a priori preference between conflicting objectives.

However, extracting this curve requires running numerous computationally expensive simulations. For instance, given that each simulation takes 1 s, evaluating all 152,000 combinations requires approximately 42 h. Consequently, alternative approaches should be considered to reduce computational effort while still identifying near-optimal solutions.

3.3.1. Hooke–Jeeves Method

The Hooke–Jeeves method explores the search space by evaluating small step variations in each coordinate direction [42]. In our case, if we select either $f=E_l$ or $f=I_o$ as the objective function and fix $n_1=n_3=255$, then the optimal parameter set ${(m_1,n_2,m_2)}_{opt}$ must be identified such that f is minimized.

Starting from an initial guess ${(m_1,n_2,m_2)}_0$ and defining the step sizes $\Delta m_1\in [-1,0,1]$, $\Delta n_2\in [-1,0,1]$, and $\Delta m_2\in [-1,0,1]$, the function f is found at all neighboring points of the form ${(m_1,n_2,m_2)}_0+\alpha (\Delta m_1,\Delta n_2,\Delta m_2)$, where $\alpha =1$ is an integer step multiplier. The next candidate, ${(m_1,n_2,m_2)}_1$ is chosen as the point providing the lowest f value.

This process is iterated until no further decrease in f is observed. At this point, the step size $\alpha$ can be increased to escape potential local minima. If no further improvement follows, the algorithm terminates.

The results of this optimization approach are illustrated in Figure 7, starting from the initial parameter set ${(m_1,n_2,m_2)}_0=(35,40,20)$. As the iterations progress, the identified points converge toward lower values of either $E_l$ or $I_o$.

After 33 and 30 iterations, involving 574 and 554 unique simulations of the circuit, respectively, the optimal sets ${(m_1,n_2,m_2)}_{33}=(46,255,3)$ and ${(m_1,n_2,m_2)}_{30}=(38,16,40)$ are found, yielding the lowest $E_l=1.93$ mJ and $I_o=20.96$ A, respectively.

To identify multiple points on the Pareto curve, the weighted sum method [42] can be employed to transform the bi-objective optimization problem into a single-objective problem. This is achieved by using the expression $f=w{\widehat{E}}_l+(1-w){\widehat{I}}_o$, where $0\le w\le 1$ is a weighting factor, and ${\widehat{E}}_l=E_l/\min \left(E_l\right)$, ${\widehat{I}}_o=I_o/\min \left(I_o\right)$ are the normalized forms of $E_l$ and $I_o$, respectively, to ensure that both terms are comparable.

Starting from the initial point ${(m_1,n_2,m_2)}_0=(35,40,20)$, the optimal parameter sets corresponding to the lowest values of f are computed for increasing weights $w=0,0.05,\dots ,1$. The results are shown in Figure 8. Although the method succeeds in locating solutions along the edge of the point cloud, the distribution is sparse in the middle region. This occurs despite the use of many weight values and a total of 379 iterations, involving 2298 circuit simulations. Therefore, the weighted sum approach is inefficient.

To increase the density of Pareto-optimal solutions and reduce the number of required simulations, an alternative method is proposed in the following subsection.

3.3.2. Proposed SLSE Method

From the point cloud, it was observed that setting constant values of $n_1=255$ and $n_2=0$, while decreasing $m_1=90,89,\dots$, produces distinct traces of points moving from left to right for different fixed values of $m_2$, as illustrated in Figure 9. For each trace (i.e., each $m_2$), a specific value $m_{1\min }$ exists that yields minimum overshoot $I_o$. Decreasing $m_1$ beyond this point causes an increase in $I_o$, as demonstrated in Figure 4, for the case $m_2=256$.

Figure 9 also demonstrates that adjacent traces corresponding to sequentially increasing $m_2$ values define some lower edge points of the cloud within specific energy intervals. For example, the green curve represents the lowest line in the energy range from $E_{m_2=2}$ to $E_{m_2=3}$, whereas the magenta curve is the lowest from $E_{m_2=3}$ to $E_{m_2=4}$. Therefore, we are interested in finding not all traces, but rather a few key points from sections where these traces are the lowest compared to the others. Based on this observation and considering that the points in the $E_l$ versus $I_o$ plane ($\mathit{eo}$-plane) are closely located to each other for the gate current profiles $(n_1,m_1,n_2,m_2,n_3)$ and $(n_1,m_1\pm 1,n_2,m_2\pm 1,n_3)$, the following SLSE (sequential lowest segment extraction) algorithm for finding the Pareto frontier is proposed.

1.

The parameters $(n_1,m_1,n_2,m_2,n_3)$ are set to their maximum values: ($n_{\max }$, 1020, $n_{\max }$, 256, $n_{\max }$), $n_{\max }=255$, and the simulation is run to determine the energy loss and drain current overshoot, denoted as $E_{l\min }$ and $I_{o\max }$, respectively, as the selected gate current profile yields the smallest $E_l$ and the largest $I_o$.

2.

Keep $n_1=n_3=n_{\max }$; set $n_2=0$, $m_2=1$, and run the simulations by increasing $m_1=1,2,\dots$ until the difference $I_{o\max }-I_o$ is less than a certain threshold (e.g., 100 mA). Record the final $m_1$ value, denoted as $m_{1\max }$, and define a pair $({\acute{m}}_1,{\acute{m}}_2)$ as $(m_{1\max },1)$.

3.

Keep $n_1=n_3=n_{\max }$, $n_2=0$; set $(m_1,m_2)$ to $({\acute{m}}_1+1,{\acute{m}}_2)$, $({\acute{m}}_1,{\acute{m}}_2)$, $({\acute{m}}_1+1,{\acute{m}}_2+1)$, $({\acute{m}}_1,{\acute{m}}_2+1)$, and run the simulations to find the points $A_1$, $A_2$, $B_1$, $B_2$, respectively, which represent $E_l$ and $I_o$ values in the $\mathit{eo}$-plane, as illustrated in Figure 10, where x, $dx$, y, $dy$ conform to ${\acute{m}}_1+1$, $-1$, ${\acute{m}}_2$, 1, respectively. Subsequently, compare the obtained segments $\overline{A_1{A}_2}$ and $\overline{B_1{B}_2}$ (as detailed in the next subsection), and update the values of $({\acute{m}}_1,{\acute{m}}_2)$ accordingly: decrease ${\acute{m}}_1$ by 1 or increase ${\acute{m}}_2$ by 1 based on the comparison result.

4.

Repeat Step 3 until $I_o$ reduces no more.

After applying the algorithm, a set of gate current profiles $\left\{{(n_1,m_1,n_2,m_2,n_3)}_k\right\}$, where $k=1,2,\dots$, is obtained. The elements ${(n_1,m_1,n_2,m_2,n_3)}_k$ are used during the execution of the algorithm to identify the segments $\overline{A_1{A}_2}$ and $\overline{B_1{B}_2}$ of adjacent traces, ensuring that those closest to the Pareto frontier are selected. All profiles share the same parameters: $n_{1k}=n_{\max }$, $n_{2k}=0$, and $n_{3k}=n_{\max }$, whereas $m_{1k}$ decreases and $m_{2k}$ increases with increasing k, following the values of ${\acute{m}}_1$ and ${\acute{m}}_2$, respectively. The corresponding ${(E_l,I_o)}_k$ values are shown in Figure 11, where the dashed line connects the points in the order they were obtained. The algorithm required 52 simulations of the electrical circuit, including those for finding $(E_{l\min },I_{o\max })$ and the initial $({\acute{m}}_1,{\acute{m}}_2)$. Since the points ${(E_l,I_o)}_k$ do not form a decreasing curve in the $\mathit{eo}$-plane, a filtering operator $\mathcal{F}$ is applied to remove the points located above the curve, resulting in 21 optimal points and their corresponding gate current profiles.

For clarity, the application of the algorithm will be denoted by $f_{\mathrm{SLSE}}$$(x$, $dx$, y, $dy$, $plane)$, where x and y are the parameters varied during the execution of the algorithm, and $dx$ and $dy$ are their corresponding step sizes. The term $plane$ denotes the coordinate plane in which the optimal curve is determined (in our case, either $eo$ or $e{\dot{v}}_{\max }$-plane). Accordingly, the application of the algorithm described in this subsection can be expressed as $f_{\mathrm{SLSE}}(m_1,-1,m_2,1,eo)$.

3.3.3. Comparison of the Segments of the Traces

Given two segments $\overline{A_1{A}_2}$ and $\overline{B_1{B}_2}$ in the energy loss (e) versus overshoot (o) plane, they are compared according to the overlap of their projections on the e and o axes:

(a)

Only the horizontal (e) projections overlap (Figure 10a). In this case, if ${\widehat{o}}_{12}<o_{12}$, then y is updated by $dy$: $y=y+dy$, whereas x remains unchanged. Otherwise, x is updated by $dx$: $x=x+dx$, whereas y remains the same. Here, ${\widehat{o}}_{12}$ and $o_{12}$ are the ordinates of points $B_{12}$ and $A_{12}$, respectively, which lie on segments $\overline{B_1{B}_2}$ and $\overline{A_1{A}_2}$. These points share equal abscissas $e_{12}$ conforming to the midpoint of the overlapping segment on the e-axis.

(b)

Only vertical projections (o) overlap (Figure 10b). In this case, if ${\widehat{e}}_{12}<e_{12}$, then only y is updated as: $y=y+dy$. Otherwise, only x is updated to $x=x+dx$. Here, ${\widehat{e}}_{12}$ and $e_{12}$ are the abscissas of points $B_{12}$ and $A_{12}$, respectively, which lie on segments $\overline{B_1{B}_2}$ and $\overline{A_1{A}_2}$, and whose equal ordinates $o_{12}$ correspond to the midpoint of the overlapping segment on the o-axis.

(c)

Both the horizontal (e) and vertical (o) projections overlap (Figure 10c). In this scenario, if $\overline{A_1{A}_2}$ and $\overline{B_1{B}_2}$ do not intersect and ${\widehat{o}}_{12}<o_{12}$, then only y is updated to $y=y+dy$. Otherwise, only x is updated to $x=x+dx$. Here, ${\widehat{o}}_{12}$ and $o_{12}$ are the ordinates of $B_{12}$ and $A_{12}$, respectively, which lie on segments $\overline{B_1{B}_2}$ and $\overline{A_1{A}_2}$ and share equal abscissas $e_{12}$ conforming to the midpoint of the overlapping segment on the e-axis.

(d)

No overlaps occur (Figure 10d). In this last scenario, two points, $A_{12}$ and $B_{12}$, are found, which lie either on $\overline{A_1{A}_2}$ and $\overline{B_1{B}_2}$, respectively, or on their extensions and share the same abscissa $e_{12}=({\widehat{e}}_1+{\widehat{e}}_2+e_1+e_2)/4$. If their ordinates satisfy ${\widehat{o}}_{12}<o_{12}$, only y is updated as $y=y+dy$, otherwise, only x is updated as $x=x+dx$.

3.3.4. Increasing the Amplitude of the Second Pulse

From Figure 11, it can be observed that the identified blue points are less dense than the gray points along the boundary of the point cloud. Moreover, in the lower $E_l$ region, the blue points are positioned above the lower edge of the cloud. This arises from the fact that $n_2=0$ is kept constant for all profiles. If $n_2$ is increased for the same set of identified optimal profiles, additional points ${(E_l,I_o)}_{\widehat{k}}$ with a denser distribution can be obtained.

For example, by selecting $n_2=[2,4,\dots ,20]\cup [24,28,\dots ,40]\cup [50,60,\dots ,120]\cup [150,200]\cup \left[255\right]$, the newly obtained points are shown as green circles in Figure 12. The increase from $n_2=2$ to $n_2=255$ is applied only to those profiles whose corresponding $(E_l,I_o)$ points, when connected to the leftmost upper point, form the lowest boundary lines. Furthermore, each increase in $n_2$ can be terminated early once the generated profiles begin to yield higher $E_l$ values for the same $I_o$ compared to already identified optimal profiles.

In this manner, by performing 94 additional circuit simulations and applying the filtering operator to the union of the two sets $\left\{{(E_l,I_o)}_k\right\}\cup \left\{{(E_l,I_o)}_{\widehat{k}}\right\}$, 70 additional optimal profiles are found. As a result, a total of 146 circuit simulations yield 91 optimal gate current profiles, which is significantly more efficient than the weighted sum approach.

3.3.5. Decreasing the Amplitude of the Third Pulse

Figure 12 presents the results for $n_1=n_3=255$. To investigate the effect of reducing $n_3$ while keeping $n_1=255$, the algorithm was run for smaller values of $n_3=120$, 90, 50, and 30. As shown in Figure 13, the resulting trade-off curves shift to the right, with the shift becoming more pronounced as $n_3$ decreases. This behavior can be attributed to the reduction in $m_1$ along the descending lines, which shortens the duration of the first pulse and increases the impact of the third pulse on the opening of the transistor. As $n_3$ decreases, smaller values of $I_o$ can be achieved. This is also demonstrated by the lower teal Pareto curve, obtained from the gray points representing the simulation results for $n_3=[10,20,\dots ,240]\cup \left[255\right]$. The red Pareto curve (also shown in Figure 6) corresponds to the single case $n_3=255$.

Conversely, increasing $n_3$ from smaller to larger values leads to a reduction in $E_l$. However, this improvement diminishes as $n_3$ approaches its maximum value of 255. Therefore, selecting $n_3=255$ yields the lowest $E_l$ values, provided that $I_o$ values larger than 30 A are acceptable.

3.3.6. Decreasing the Amplitude of the First Pulse

High-speed switching transients produce EMI, which can lead to performance degradation of electrical equipment. Therefore, attention must also be paid to ${\dot{v}}_{\max }=\max (d{v}_{ds}/dt)$ values of the drain-source voltages $v_{ds}\left(t\right)$, which in our application should not exceed 20 V/ns.

By representing the results from Figure 13 in the $e{\dot{v}}_{\max }$-plane (Figure 14), it becomes evident that the leftmost blue dashed curve, which is optimal in the $eo$-plane and corresponds to $n_1=n_3=255$, is also nearly optimal in the $e{\dot{v}}_{\max }$-plane for $E_l<3$ mJ. A similar observation applies to the $eo$-Pareto curves, indicating a correlation between $I_o$ and ${\dot{v}}_{\max }$, as both the drain current overshoot $I_o$ and ${\dot{v}}_{\max }$ are determined by the rate of change of the drain current $d{i}_d/dt$ [28]. Furthermore, the gray points show that ${\dot{v}}_{\max }$ does not fall below 40 V/ns for both $n_3=n_1$ and $n_3<n_1$ cases.

To achieve lower values, the amplitude of the first pulse must be reduced to limit the rate of increase of the drain current. To demonstrate this effect, the SLSE algorithm was executed multiple times with $n_1=n_3$ set to 120, 90, 70, 50, 40, and 30. The resulting curves, obtained by applying $\mathcal{F}$ to the SLSE points in the $e{\dot{v}}_{\max }$-plane, progressively shift toward the lower-right corner as $n_1$ decreases, as indicated by the dashed lines in Figure 15.

Additionally, the empty red circles connected by a solid red line represent the $(E_l$, ${\dot{v}}_{\max })$ values obtained when, instead of (2), the gate current profiles are composed of a single Heaviside step function $i_p\left(t\right)=I_{1}u(t-t_0)$, where $I_1=n_1{\Delta }_I$, and $n_1$ decreases from 255 to 26, resulting in a descending sequence of points from left to right. As observed, the starting points (large empty circles) of the trade-off curves lie close to the solid red line, confirming the consistency of the results, because the initial gate current profiles with $n_1=n_3$ and $m_2=1$ approximate scaled Heaviside step functions with amplitude $I_1$.

3.3.7. Extended SLSE Method

By comparing the first two curves ($n_1=n_3=255$ and $n_1=n_3=120$) with the teal Pareto curve in Figure 15, it follows that lower values of ${\dot{v}}_{\max }$ for the same $E_l$ can be achieved by reducing $n_3$ below $n_1$. Consequently, for each value of $n_1$, multiple cases with $n_3\le n_1$ must be considered. This requires executing the SLSE algorithm for different combinations of $(n_1,n_3)$, thereby increasing the computational cost.

To reduce the number of circuit simulations, the following two observations are considered:

• Since consecutive curves for $n_1=n_3$ shift downward and to the right as $n_1$ decreases (Figure 15), it is more efficient to focus only on determining the lower segments of each curve, where ${\dot{v}}_{\max }$ values are smaller. This can be justified by noting that the final points of adjacent trade-off curves correspond to the gate current profiles, which have $n_1$ and $m_1$ yielding almost identical products $n_1{m}_1$. This indicates that the amount of electric charge transferred to the transistor gate remains approximately constant.
• After determining the $eo$-optimal curve for the case $n_1=n_3$ (as described in Section 3.3.2), its final gate current profile yielding the lowest $I_o$ can be used to identify the optimal profiles for reduced values $n_3<n_1$. For this purpose, the SLSE algorithm is applied as $f_{\mathrm{SLSE}}(n_3,-d{n}_3,n_2,-1,e{\dot{v}}_{\max })$, resulting in profiles corresponding to lower ${\dot{v}}_{\max }$ values. Accordingly, instead of varying $m_1$ and $m_2$, the parameters $n_2$ and $n_3$ are decreased.

Based on these two observations, an extended SLSE (ESLSE) procedure consisting of 2 phases is proposed to determine the trade-off curve spanning both the high- and low-${\dot{v}}_{\max }$ regions.

Phase 1 (considers the first observation):

(1a)

Choose some integer values ${\gamma }_1>{\gamma }_2>\dots >{\gamma }_L>0$, where ${\gamma }_1=255$, and initialize $l=1$.

(1b)

Set $n_{\max }={\gamma }_l$ and run the SLSE algorithm as described in Section 3.3.2.

(1c)

After completion, apply $\mathcal{F}$ to the obtained $(E_l,I_o)$ points and record the gate current profile ${({\widehat{n}}_1,{\widehat{m}}_1,{\widehat{n}}_2,{\widehat{m}}_2,{\widehat{n}}_3)}_l$ corresponding to the lowest $I_o$ value. Calculate the new parameter ${\acute{m}}_1=\lfloor {\gamma }_l{\widehat{m}}_{1l}/{\gamma }_{l+1}\rfloor$.

(1d)

Increase $l=l+1$; set $n_1=n_3={\gamma }_l$, keep $n_2=0$, set $m_2=1$, and run the simulations for increasing $m_1={\acute{m}}_1,{\acute{m}}_1+1,\dots$ until $I_o$ begins to rise; record the final $m_1$ value as $m_{1\min }$, and define a pair $({\acute{m}}_1,{\acute{m}}_2)$ as $(m_{1\min },1)$.

(1e)

Restart the SLSE algorithm from Step 3, by keeping $n_1=n_3={\gamma }_l$.

(1f)

Repeat Steps (1c)–(1e) until the final ${\gamma }_L$ has been processed.

Phase 2 (considers the second observation):

(2a)

Set $l=0$.

(2b)

Increase $l=l+1$ and select the profile ${({\widehat{n}}_1,{\widehat{m}}_1,{\widehat{n}}_2,{\widehat{m}}_2,{\widehat{n}}_3)}_l$.

(2c)

Run simulations for increasing and decreasing values of $m_1={\widehat{m}}_{1l}\pm 1,{\widehat{m}}_{1l}\pm 2,\dots$ until the profile yielding the lowest ${\dot{v}}_{\max }$ is identified; record the corresponding value of $m_1$ as ${\widehat{m}}_{1\min }$.

(2d)

Keep $n_1={\widehat{n}}_{1l}$, $m_1={\widehat{m}}_{1\min }$, $m_2={\widehat{m}}_{2l}$, and define a pair $({\acute{n}}_2,{\acute{n}}_3)$ as $(20,{\widehat{n}}_{3l}-d{\acute{n}}_3)$, where the step size $d{\acute{n}}_3=\lfloor {\widehat{n}}_{3l}/10+1\rfloor$ is chosen to adapt to the ${\widehat{n}}_{3l}$ values to reduce the number of simulations while increasing the density of points as ${\widehat{n}}_{3l}$ decreases.

(2e)

Set $(n_2,n_3)$ to $({\acute{n}}_2,{\acute{n}}_3+d{\acute{n}}_3)$, $({\acute{n}}_2,{\acute{n}}_3)$, $({\acute{n}}_2-1,{\acute{n}}_3+d{\acute{n}}_3)$, $({\acute{n}}_2-1,{\acute{n}}_3)$, and run the simulations to find the points $A_1$, $A_2$, $B_1$, $B_2$, respectively, which represent $E_l$ and ${\dot{v}}_{\max }$ values in the $\mathit{e}{\dot{\mathit{v}}}_{\max }$-plane. Then, compare the obtained segments $\overline{A_1{A}_2}$ and $\overline{B_1{B}_2}$, and update the values of $({\acute{n}}_2,{\acute{n}}_3)$ accordingly: decrease ${\acute{n}}_2$ by 1 or decrease ${\acute{n}}_3$ by $d{\acute{n}}_3=\lfloor {\acute{n}}_3/10+1\rfloor$ based on the comparison result.

(2f)

Repeat Step (2e) until ${\dot{v}}_{\max }$ reduces no more.

(2g)

Repeat Steps (2b)–(2f) until l exceeds L.

Phase 1 begins with the identification of the complete trade-off curve for $n_1=n_3=255$, followed by determination of the lower segments of subsequent curves with $n_1=n_3<255$. In Step (1d), the parameter $m_1$ is increased because its initial value $m_1={\acute{m}}_1$ is too low for the SLSE algorithm to proceed from Step 3. Since this initial value corresponds to the lowest points of the trade-off curve associated with the updated $n_1$, it must be increased to enable the SLSE algorithm to track the lower segments starting from higher ${\dot{v}}_{\max }$ values. Furthermore, $m_1$ is increased until $I_o$ begins to rise, i.e., beyond the point $m_{1\min }$, as illustrated in Figure 4.

Phase 2 enables identification of the optimal low-${\dot{v}}_{\max }$ gate current profiles for each $n_1=n_3={\gamma }_l$ curve and follows a procedure nearly identical to the SLSE algorithm, with $n_2$ and $n_3$ as the varying parameters. In Step (2d), the value of ${\acute{n}}_2$ is initialized to 20, as simulations indicate that low-${\dot{v}}_{\max }$ region corresponds to $n_2<20$.

In our example, with $L=7$, ${\gamma }_1=255$, ${\gamma }_2=120$, ${\gamma }_3=90$, ${\gamma }_4=70$, ${\gamma }_5=50$, ${\gamma }_6=40$, and ${\gamma }_7=30$, the ESLSE required 800 circuit simulations (333 and 467 for Phases 1 and 2, respectively) to determine the $(E_l,{\dot{v}}_{\max })$ points, as illustrated in Figure 16. Applying the operator $\mathcal{F}$ to these points yields 152 optimal points, indicated by large magenta circles.

When Phase 2 is executed in the $eo$-plane, $eo$-optimal trade-off curve spanning both the high- and low-$I_o$ regions is obtained. However, this curve is not optimal in the $e{\dot{v}}_{\max }$-plane. Conversely, the $e{\dot{v}}_{\max }$-optimal trade-off curve is not optimal in the $eo$-plane. This distinction is illustrated in Figure 17, where the optimal curves are shown as solid lines, while their representations in the other plane are shown as dotted lines.

The last two figures for the turn-on case (Figure 18 and Figure 19) illustrate the parameters of the gate current profiles corresponding to the $eo$- and $e{\dot{v}}_{\max }$-optimal trade-off curves. The vertical dashed lines on the left and right indicate the end of Phase 1 and Phase 2, respectively, for the case $n_1=255,n_3\le 255$. As observed, the parameters for both the $eo$- and $e{\dot{v}}_{\max }$-optimal curves are similar during Phase 1, which corresponds to low $E_l$ and high $I_o$ and ${\dot{v}}_{\max }$ values. In contrast, after Phase 1, the parameters begin to differ significantly in order to achieve lower values of either $I_o$ or ${\dot{v}}_{\max }$.

For the $eo$-optimal curve, the first case with $n_1=255,n_3\le 255$ provides optimal profiles for $E_l$ up to 9 mJ. It can be observed that during Phase 1, when $n_1=n_3$, the parameter $m_1$ gradually decreases, whereas $m_2$ increases, which aligns with the behavior targeted by the SLSE algorithm. In addition, the amplitude of the second pulse, $n_2$, increases multiple times from 0 to higher values to obtain a denser sampling of the trade-off curve, as described in Section 3.3.4. In Phase 2, the amplitudes $n_2$ and $n_3$ decrease to achieve a further reduction in $I_o$.

For the $e{\dot{v}}_{\max }$-optimal curve, the first case with $n_1=255,n_3\le 255$ is optimal only for $E_l$ up to 4.2 mJ, and further reductions in ${\dot{v}}_{\max }$ require decreasing $n_1$.

4. Turn-Off Phase

4.1. Constraining the Search Space

The gate current parameters for the turn-off phase are $(n_4,m_4)$, $(n_5,m_5)$. Similar to the turn-on case, the first step is to investigate how the energy loss $E_l$ and drain-source voltage overshoot $V_o=v_{ds\max }-V_{DC}$ vary with $n_4=n_5$, while setting $m_4$ and $m_5$ to their maximum values. The resulting curves, shown in Figure 20 for the $V_{DC}$ value of 850 V, reveal that the smallest energy losses occur when $n_4=n_5=255$. Therefore, to achieve lower $E_l$ values, $n_4$ should be set to $n_4=255$.

The second step is to determine the effect of an increase in $m_4$ on $E_l$ and $V_o$, given that $n_4=255$ and $m_5=0$, ensuring that the second negative pulse is discarded. The obtained curves are illustrated in Figure 21, which shows that at a specific $m_4=m_{4\min }$, the energy loss $E_l$ reaches its maximum value, whereas $V_o$ approaches zero. If $m_4\le m_{4\min }$, the transistor fails to reach the turn-off state (Figure 22, $m_4=50$, 65, and 69) with its drain current $i_D\left(t\right)$ keeping $I_L$ value. Conversely, if $m_4$ exceeds $m_{4\min }$ and continues to increase, the transistor progressively closes until it fully turns off at $m_{4\max }$ (Figure 22, $m_4=70$, 75, and 95). Beyond this point, further increase in $m_4$ is unnecessary, as $E_l$ and $V_o$ remain nearly constant regardless of the different combinations of $(n_5,m_5)$, as the transistor is already turned off after the first pulse.

Given $m_{4\min }$ and $m_{4\max }$, the search space for the parameters $(n_4,m_4,n_5,m_5)$ is restricted to $n_4=255$, $m_4\in [m_{4\min }-\Delta m_{4\min },m_{4\max }]$, $n_5\in [0,255]$, and $m_5=510$. The term $\Delta m_{4\min }$ ($m_{4\min }>\Delta m_{4\min }>0$) is introduced to explore scenarios in which $m_4$ is too small to significantly impact the switching behavior of the transistor, making the second negative pulse the primary influencing factor. Consequently, smaller $m_5$ values are unnecessary, because the main role of the second pulse is to ensure complete transistor turn-off.

4.2. Simulation Results

The parameters are selected as follows, $n_4=255$, $m_4=[0,1,\dots ,100]$, $n_5=[0,1,\dots ,255]$, and $m_5=510$, resulting in 25,856 unique combinations of $(n_4,m_4,n_5,m_5)$. After running the simulations and discarding cases where the transistor failed to turn off (i.e., $i_d\left(t\right)$ did not fall below 0.1 A), the remaining 24,253 results are plotted as gray points in Figure 23. The red Pareto curve highlights the optimal trade-off between $E_l$ and $V_o$.

To demonstrate the effect of decreasing $m_5$, 25,856 simulations were conducted for each of $m_5=350$, $m_5=50$, and $m_5=25$. After filtering out cases in which the transistor did not turn off, 23,540, 11,200, and 7286 valid results remained, respectively. The corresponding Pareto curves shown in Figure 23 reveal that the length of the curves decreases as $m_5$ decreases. This occurs because for the transistor to turn off at lower $m_5$ values, the parameter $m_4$, which controls the duration of the first negative pulse, must be larger. A longer first pulse results in faster transients, leading to a lower energy loss $E_l$ but a higher $V_o$. Therefore, to ensure that both high and low $V_o$ regions are covered, $m_5$ is set to its maximum value of 510.

4.3. Finding the Optimal Trade-Off Curve

Extraction of the Pareto curve from the gray points in Figure 23 is possible if a large number of simulations are performed, which is time consuming. Although the Hooke–Jeeves method can also be applied, it yields only a small number of optimal solutions relative to the number of simulations. Therefore, the SLSE algorithm for the turn-off case is proposed, as described in the next subsection.

4.3.1. SLSE Method for the Turn-Off Case

From the point cloud in Figure 23, the following observations were made. When $n_4=255$ and $m_5=510$ are held constant, decreasing $n_5$ from 255 to 0 generates distinct traces of points moving from left to right for different $m_4$ values, as shown in Figure 24. For each trace (corresponding to a specific $m_4$), there is a section that aligns with the Pareto curve. Therefore, instead of identifying all traces, only key sections conforming to the optimal trade-off line should be extracted.

By closely examining Figure 25, which shows four adjacent traces corresponding to sequentially decreasing $m_4$ values, and comparing it to Figure 9, it is evident that the SLSE algorithm can be applied in this case. However, instead of adjusting the parameters $m_1$ and $m_2$, the parameters $m_4$ and $n_5$ are modified. The algorithm $f_{\mathrm{SLSE}}(n_5,-1,m_4,-1,eo)$ is written as follows.

1.

The parameters $(n_4,m_4,n_5,m_5)$ are set to their maximum values: (255, 2040, 255, 510), and the simulation is run to find the energy loss and the drain-source voltage overshoot, denoted as $E_{l\min }$ and $V_{o\max }$.

2.

Keep $n_4=255$, $m_5=510$; set $m_4=1$, $n_5=0$, and run the simulations by increasing $m_4=1,2,\dots$ until the difference $V_{o\max }-V_o$ is less than a certain threshold (e.g., 1 V), record the final $m_4$ value, denoted as $m_{4\max }$, and define a pair $({\acute{m}}_4,{\acute{n}}_5)$ as $(m_{4\max },254)$.

3.

Keep $n_4=255$, $m_5=510$; set $(m_4,n_5)$ to $({\acute{m}}_4,{\acute{n}}_5+1)$, $({\acute{m}}_4,{\acute{n}}_5)$, $({\acute{m}}_4-1,{\acute{n}}_5+1)$, $({\acute{m}}_4-1,{\acute{n}}_5)$, and run the simulations to find points $A_1$, $A_2$, $B_1$, $B_2$, respectively, which represent $E_l$ and $V_o$ values in the $\mathit{eo}$-plane, as illustrated in Figure 10, where x, $dx$, y, $dy$ conform to ${\acute{n}}_5+1$, $-1$, ${\acute{m}}_4$, $-1$, respectively. Subsequently, compare the obtained segments $\overline{A_1{A}_2}$ and $\overline{B_1{B}_2}$ (as detailed in Section 3.3.3) and update the values of $({\acute{m}}_4,{\acute{n}}_5)$ accordingly: decrease either ${\acute{m}}_4$ or ${\acute{n}}_5$ by 1 based on the comparison result.

4.

Repeat Step 3 until the transistor fails to turn off.

In our example, after the algorithm is completed, a set of the gate current profiles $\left\{{(n_4,m_4,n_5,m_5)}_k\right\}$, where $k=1,2,\dots ,871$, is obtained. The corresponding ${(E_l,V_o)}_k$ values are represented by red dots in Figure 26. Because the density of these points increases with increasing $n_5$, an adaptive value of $-\lfloor {\acute{n}}_5/50+1\rfloor$ can be used in Step 3 of the algorithm instead of a fixed $dx=-1$. This adjustment reduces the number of required simulations from 871 to 372 while maintaining a sufficient point density (represented by the green triangles in Figure 26) along the optimal trade-off line, which is obtained by first applying the filtering operator $\mathcal{F}$ to the green triangles and then connecting the remaining 169 optimal points.

4.3.2. Decreasing the Amplitude of the First Negative Pulse

After determining the optimal solutions in the $eo$-plane, the next step is to analyze these results in the $e{\dot{v}}_{\max }$-plane, as illustrated in Figure 27. The figure shows that all $eo$-optimal profiles yield the same value of ${\dot{v}}_{\max }=80$ V/ns, which lie significantly above the $e{\dot{v}}_{\max }$-Pareto curve.

To reduce the ${\dot{v}}_{\max }$ values of the $eo$-optimal profiles, the amplitude of the first negative pulse can be decreased. This effect is demonstrated by executing the SLSE algorithm for multiple values of $n_4=\xi$, where $\xi =90$, 50, and 30, with the following adjustments in the algorithm. Set $n_4=n_5=\xi$ in Step 1. Keep $n_4=\xi$, find $m_{4\max }$, and then define $({\acute{m}}_4,{\acute{n}}_5)$ as $(m_{4\max },\xi -1)$ in Step 2. Finally, keep $n_4=\xi$ in Step 3.

The results obtained in both planes are shown in Figure 28 and Figure 29. The additional empty red circles connected by a solid red line represent $(E_l,V_o)$ and $(E_l,{\dot{v}}_{max})$ values, respectively, obtained when the gate current profiles are composed of a single Heaviside step function, $i_p\left(t\right)=I_{4}u(t-t_4)$, where $I_4=-n_4{\Delta }_I$, and $n_4$ decreases from 255 to 19, resulting in a descending sequence of points from left to right.

As shown in Figure 28, the trade-off curve for $n_4=255$ yields the lowest energy loss values across the entire $V_o$ range, eliminating the need to further decrease $n_4$. However, this is not the case in the $e{\dot{v}}_{\max }$-plane (Figure 29), where the curves have constant ${\dot{v}}_{\max }$ values, which decrease as $n_4$ decreases, yet remain above the $e{\dot{v}}_{\max }$-Pareto curve. This Pareto curve coincides with the red line corresponding to profiles defined by a single Heaviside step function.

To explain this behavior, Figure 30 presents multiple traces of $(E_l,{\dot{v}}_{max})$ points for different combinations of $(m_4,n_5)$, where one parameter is varied while the other is held constant, with the remaining parameters fixed at $n_4=255$ and $m_5=510$. The traces corresponding to $m_4=70$, 63, and 55 show that for $m_4>70$, ${\dot{v}}_{\max }$ remains constant at 80 V/ns. This indicates that when the duration of the first negative pulse exceeds a certain threshold, ${\dot{v}}_{\max }$ reaches its maximum value and remains unchanged with further increases in $m_4$.

In contrast, for $m_4<55$, the values of ${\dot{v}}_{\max }$ follow the $e{\dot{v}}_{\max }$-Pareto curve from left to right as $n_5$ decreases below 255. This behavior arises because the first pulse is too short to discharge the parasitic capacitances of the transistor and therefore has negligible influence on the turn-off transients, which are instead governed by the second pulse. In this case, the response is effectively equivalent to that obtained with a single Heaviside step function of decreasing amplitude, as the first pulse can be neglected.

The observed constant values of ${\dot{v}}_{\max }$ for the $eo$-optimal curves corresponding to different $n_4$ can be explained by the excessively long duration of the first pulse. In this regime, only the amplitude of the first pulse influences the resulting ${\dot{v}}_{\max }$ values, while both $m_4$ and $n_5$ determine the voltage overshoot $V_o$. This is confirmed by the parameters of the $eo$-optimal gate current profiles shown in Figure 31 for the case $n_4=255$. As observed, $m_4$ does not fall below the threshold value of 70, resulting in constant ${\dot{v}}_{\max }$ values of 80 V/ns for all profiles.

Similar to the turn-on case, two trade-off curves are identified in the turn-off case. The first, $eo$-optimal, is derived using the SLSE method as described in Section 4.3.1. The second, $e{\dot{v}}_{\max }$-optimal, is obtained by applying a single Heaviside step function with decreasing amplitude. Both curves and their representations in the other plane are illustrated in Figure 32, revealing a more pronounced difference than that observed in the turn-on case (Figure 17).

5. Comparison of the Results with the Classical Gate Driver

The identified optimal trade-off curves can be compared with the classical driving case, where a voltage source is applied to the transistor gate through gate resistance $R_g$ instead of a digital current source. The voltage source generates a single pulse with either a positive (turn-on) or negative (turn-off) amplitude. Depending on the selected $R_g$ value, the energy loss, overshoot, and voltage derivative vary similarly to the advanced driving case, where different gate current profiles are used.

In our case, after simulating the same MOSFET circuit driven by the voltage source, the resulting $(E_l,I_o)$ and $(E_l,{\dot{v}}_{\max })$ values form descending lines as $R_g$ increases, as indicated by the solid lines in Figure 33.

The dotted lines, which conform to the $e{\dot{v}}_{\max }$-optimal trade-off curve and its representation in the $eo$-plane for the advanced gate driver (AGD), demonstrate reduced values of both $I_o$ and ${\dot{v}}_{\max }$ for the same $E_l$ (i.e., for the same gate current profile). The following formulas are used to evaluate these reductions:

$${\iota }_{ϵ}=\left(1-{\displaystyle \frac{I_o^{\mathrm{a}}{|}_{E_l=ϵ}}{I_o^{\mathrm{c}}{|}_{E_l=ϵ}}}\right)100\%,$$

(3)

$${\nu }_{ϵ}=\left(1-{\displaystyle \frac{{\dot{v}}_{\max }^{\mathrm{a}}{|}_{E_l=ϵ}}{{\dot{v}}_{\max }^{\mathrm{c}}{|}_{E_l=ϵ}}}\right)100\%,$$

(4)

where $I_o^{\mathrm{a}}{|}_{E_l=ϵ}$, ${\dot{v}}_{\max }^{\mathrm{a}}{|}_{E_l=ϵ}$, and $I_o^{\mathrm{c}}{|}_{E_l=ϵ}$, ${\dot{v}}_{\max }^{\mathrm{c}}{|}_{E_l=ϵ}$ denote the values of $I_o$, ${\dot{v}}_{\max }$ for the advanced and classical gate drivers, respectively, at $E_l=ϵ$. The resulting ${\iota }_{ϵ}$ and ${\nu }_{ϵ}$ values as functions of $ϵ$ are shown as solid lines in Figure 34, while the dotted lines represent the corresponding values obtained when the $eo$-optimal curve is used instead of the $e{\dot{v}}_{\max }$-optimal curve.

Similarly, by choosing a certain value for either $I_o=\zeta$ (for $eo$-optimal curve) or ${\dot{v}}_{\max }=\vartheta$ (for $e{\dot{v}}_{\max }$-optimal curve), energy loss reductions ${\epsilon }_{\zeta }$ and ${\epsilon }_{\vartheta }$ as functions of $\zeta$ and $\vartheta$ can be calculated as follows:

$${\epsilon }_{\zeta }=\left(1-{\displaystyle \frac{E_l^{\mathrm{a}}{|}_{I_o=\zeta }}{E_l^{\mathrm{c}}{|}_{I_o=\zeta }}}\right)100\%$$

(5)

and

$${\epsilon }_{\vartheta }=\left(1-{\displaystyle \frac{E_l^{\mathrm{a}}{|}_{{\dot{v}}_{\max }=\vartheta }}{E_l^{\mathrm{c}}{|}_{{\dot{v}}_{\max }=\vartheta }}}\right)100\%,$$

(6)

where $E_l^{\mathrm{a}}{|}_{I_o=\zeta }$, $E_l^{\mathrm{a}}{|}_{{\dot{v}}_{\max }=\vartheta }$, and $E_l^{\mathrm{c}}{|}_{I_o=\zeta }$, $E_l^{\mathrm{c}}{|}_{{\dot{v}}_{\max }=\vartheta }$ denote the values of $E_l$ for AGD and CGD, respectively, at either $I_o=\zeta$ or ${\dot{v}}_{\max }=\vartheta$.

For the $eo$- and $e{\dot{v}}_{\max }$-optimal curves, the obtained ${\epsilon }_{\zeta }$ and ${\epsilon }_{\vartheta }$ values are shown in Figure 35 and Figure 36, respectively, where the corresponding ${\dot{v}}_{\max }$ and $I_o$ values are also compared between AGD and CGD. For both curves, AGD achieves significantly lower $E_l$ as $I_o$ and ${\dot{v}}_{\max }$ decrease. While the $eo$-optimal curve provides ${\epsilon }_{\zeta }$ values exceeding 70% in the low-$I_o$ region, the corresponding ${\dot{v}}_{\max }$ curve for AGD lies noticeably above that of CGD. In contrast, the $e{\dot{v}}_{\max }$-optimal curve yields very similar $I_o$ values for both AGD and CGD while achieving ${\epsilon }_{\vartheta }$ values exceeding 60%.

Figure 37, Figure 38, Figure 39, Figure 40 and Figure 41 illustrate the results obtained for the turn-off phase. In contrast to the turn-on phase, the difference between $eo$-optimal and $e{\dot{v}}_{\max }$-optimal curves is more pronounced during turn-off. As shown in Figure 37 and Figure 38, employing the $eo$-optimal curve results in greater reductions in $V_o$ for the same increase in energy loss. However, the corresponding ${\dot{v}}_{\max }$ values (80 V/ns) remain significantly higher than those of CGD. In contrast, Figure 39 shows that the $e{\dot{v}}_{\max }$-optimal curve enables a simultaneous reduction in both $V_o$ and ${\dot{v}}_{\max }$ for energy losses exceeding 6 mJ, although the extent of these reductions is smaller than in the turn-on case.

As shown in Figure 40, for the $eo$-optimal curve, the reduction in energy loss increases with decreasing $V_o$, reaching up to 65%, while ${\dot{v}}_{\max }$ remains constant and is significantly higher than that of CGD. For the $e{\dot{v}}_{\max }$-optimal curve, Figure 41 shows that the energy loss reduction does not exceed 11%, while the $V_o$ values remain similar for both AGD and CGD at ${\dot{v}}_{\max }$ values below 20 V/ns. Therefore, considering this advantage and the similar performance of the $eo$- and $e{\dot{v}}_{\max }$-optimal curves in the turn-on phase, the $e{\dot{v}}_{\max }$-optimal curves are used for further comparisons in both the turn-on and turn-off phases.

Different combinations of the circuit parameters $V_{DC}$, $I_L$, and T yield different $e{\dot{v}}_{\max }$-optimal curves. Several examples are shown in Figure 42, where $V_{DC}\in [650,850]$ V, $I_L\in [30,180]$ A, and $T\in [-25,175]$ °C, indicating that temperature has a negligible influence on the turn-off curves.

By selecting $\vartheta =20$ V/ns, the resulting ${\epsilon }_{\vartheta }$ values for various combinations of $V_{DC}$ and $I_L$ in the turn-on case are as shown on the top-left side of Figure 43. The actual ${\dot{v}}_{\max }$ values, displayed on the top-middle of Figure 43, are as close as possible to 20 V/ns, constrained by the resolution (i.e., the number of $(E_l,{\dot{v}}_{\max })$ points) of the AGD trade-off curves.

The corresponding $(n_1,m_1,n_2,m_2,n_3)$ parameters defining the gate current profiles are shown on the bottom side of Figure 43. The first parameter $n_1$ takes values from the set $[30,40,50,60,70,80,100,130,170,255]$, as these values were selected for ${\gamma }_l$ in the ESLSE algorithm. The top-right side of Figure 43 presents the gate resistances $R_g$ for the CGD under the assumption that $R_g$ can be adjusted according to $V_{DC}$ and $I_L$ to match the target ${\dot{v}}_{\max }$ values. However, if such an adjustment is not possible and a single resistance value of $R_g=68.4$ Ω is selected based on the worst-case scenario to ensure that ${\dot{v}}_{\max }$ does not exceed 20 V/ns for any $V_{DC}$ and $I_L$ combination, then the resulting ${\epsilon }_{\vartheta }$ values for the CGD are shown on the left side of Figure 44, while the corresponding $\vartheta$ values are shown on the right.

The obtained values of ${\epsilon }_{\vartheta }$ for the same combinations of $V_{DC}$ and $I_L$ in the turn-off case are shown on the top-left side of Figure 45. The corresponding ${\dot{v}}_{\max }$, $(n_4,m_4)$, and $R_g$ values are shown on the top-right, bottom-left, and bottom-right sides of Figure 45, respectively. If the CGD uses a fixed $R_g=21.9$ $\Omega$ to keep ${\dot{v}}_{\max }$ below 20 V/ns for all $V_{DC}$ and $I_L$ values, then the ${\epsilon }_{\vartheta }$ values shown on the left side of Figure 46 are obtained. The corresponding ${\dot{v}}_{\max }$ values for CGD are shown on the right.

The ${\epsilon }_{\vartheta }$ values of the total switching losses, obtained by summing the corresponding turn-on and turn-off losses, are presented in Figure 47. The left side assumes a CGD with adjustable gate resistance, whereas the right side corresponds to a fixed-resistance CGD configuration.

The results in Figure 43 show that, in the turn-on case, ${\epsilon }_{\vartheta }$ varies from 27.70% to 68.09%. This indicates a significant reduction in $E_l$, even when the classical driver is allowed to use optimal $R_g$ values for different $V_{DC}$ and $I_L$. However, if this adjustment is not permitted, the minimum ${\epsilon }_{\vartheta }$ value increases to 41.90%, as shown in Figure 44.

The results in Figure 45 indicate that in the turn-off case, the reduction in $E_l$ is minimal, or even negative, when the CGD utilizes optimally tuned $R_g$ values. However, if CGD uses a fixed $R_g$ across all conditions, the advantage of AGD becomes significant, as shown in Figure 46.

6. Conclusions

The main findings of this study can be summarized as follows. First, the proposed SLSE-based optimization approach successfully identified gate current profiles that approximate the Pareto-optimal trade-off boundaries between switching losses, overshoot, and voltage slew rate for SiC MOSFET switching transients. Second, the optimized digitally controlled gate current profiles achieved total switching loss reductions of up to 60% compared to classical gate drivers while maintaining comparable overshoot and slew rate values under different operating conditions. Third, the obtained optimal gate current profiles revealed recurring pulse-shaping tendencies for both turn-on and turn-off transitions, providing practical insight into the design of programmable gate current waveforms. Finally, the identified parameter sets may be directly utilized in lookup-table-based digital gate driver implementations for adaptive switching control.

In the turn-on phase, the identified optimal gate current profiles, consisting of three successive pulses with the first and third amplitudes, $n_1$ and $n_3$, significantly larger than $n_2$, are consistent with the stop-and-go driving strategy defined in [43]. Depending on the pulse amplitudes and durations $m_1$ and $m_2$, as determined by the ESLSE algorithm, the switching losses $E_l$ are reduced by more than 70% and 60% for the $eo$- and $e{\dot{v}}_{\max }$-optimal curves, respectively, compared to the CGD. Furthermore, the use of $e{\dot{v}}_{\max }$-optimal profiles may be preferable, as they provide nearly the same values of $I_o$ and ${\dot{v}}_{\max }$ as the CGD. By selecting the threshold value of ${\dot{v}}_{\max }=20$ V/ns and comparing $E_l$ between AGD and CGD for different combinations of the circuit parameters $V_{DC}$ and $I_L$, reductions in $E_l$ of up to 68% and 71% are obtained relative to CGD with adjustable and fixed gate resistances, respectively.

In the turn-off phase, only two successive pulses are required, as the inclusion of a third pulse does not improve the trade-off curves. Furthermore, two pulses are needed only to obtain the $eo$-optimal curves, whereas a single pulse is sufficient for determining the $e{\dot{v}}_{\max }$-optimal curves. The reduction in switching losses also differs, reaching more than 60% and 10% for the $eo$- and $e{\dot{v}}_{\max }$-optimal curves, respectively. A limitation of the $eo$-optimal curves is that the resulting ${\dot{v}}_{\max }$ values become excessively high compared to CGD. Therefore, despite providing smaller reductions in $E_l$, the $e{\dot{v}}_{\max }$-optimal curves may be preferable. By selecting the threshold value of ${\dot{v}}_{\max }=20$ V/ns and comparing $E_l$ between AGD and CGD for different combinations of $V_{DC}$ and $I_L$, reductions in $E_l$ of up to 6% and 66% are obtained relative to CGD with adjustable and fixed gate resistances, respectively.

The total switching losses, calculated as the sum of the corresponding turn-on and turn-off $E_l$ values for the same $V_{DC}$, $I_L$, and T values, are reduced by up to 52% and 60% compared to CGD with adjustable and fixed gate resistances, respectively.

Turn-on and turn-off times were not measured in this study because the focus was on optimizing $E_l$, $I_o$, $V_o$, and ${\dot{v}}_{\max }$. Nevertheless, $E_l$ can be regarded as an indicative measure of switching duration, since higher switching losses generally correspond to longer switching times.

Furthermore, although experimental validation is beyond the scope of the present work, as the experimental gate driver platform is currently under development, the proposed methodology was comprehensively evaluated through simulation studies under different operating conditions. Future work should include validation of the proposed SLSE method in a real hardware system, taking into account the Safe Operating Area of the MOSFETs. Since both the turn-on and turn-off cases indicate that lower overshoot and slew rate values are achieved with smaller first pulse amplitudes, the search for optimal trade-off curves should begin with low initial values of $n_1$ and $n_4$.