Investigation on Degradation of Switching Characteristics in SiC MOSFETs Under Repetitive Surge Current

Abstract

Surge reliability is a crucial aspect of silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET) reliability. This study investigates the degradation behavior and mechanisms of switching characteristics in 1.2 kV planar-gate SiC MOSFETs under repetitive surge current. A surge current test platform is established to conduct surge tests on the device, while monitoring the evolution of its switching characteristics. The results indicate that after 4000 surge current cycles, the device’s turn-on delay time (t_d(on)), rise time (t_r), and turn-on loss (E_ON) show no significant changes. In contrast, the turn-off delay time (t_d(off)), fall time (t_f), and turn-off loss (E_OFF) increase by 9%, 7.5%, and 8.3%, respectively. Switching characteristics variations are closely linked to the reduction in threshold voltage (V_TH) and the increase in gate-source capacitance (C_GS) and gate-drain capacitance (C_GD). The degradation of these parameters stems from the accumulation of positive trapped charge in the gate oxide layer above the channel and junction field-effect transistor (JFET) region. The increase in charges results from the combined effects of negative gate bias and cyclic high temperature induced by repetitive surge current. This study provides a theoretical basis for the comprehensive understanding of the impact of surge current on SiC MOSFET performance.

1. Introduction

Compared with traditional silicon-based devices, silicon carbide (SiC) metal-oxide-semiconductor field-effect transistors (MOSFETs) have been widely adopted in fields such as electric vehicles, renewable energy, and industrial drives [1,2], owing to their advantages of high switching speed, low loss, and high-temperature tolerance [3,4]. For long-term applications, the reliability evaluation of SiC MOSFETs is particularly critical. Among various tests, power cycling testing is one of the most important reliability experiments for assessing a device’s long-term operational capability [5,6]. This test primarily simulates actual normal operating conditions and can effectively evaluate the device’s lifetime. However, the device’s performance under extreme conditions, such as surge current, is equally important. Surge current refers to an instantaneous overload current significantly exceeding the steady-state operating current of the circuit, typically triggered by converter faults [7,8,9] or transient charging of capacitive loads during system startup [10,11]. In power converter design, to achieve higher power density and lower costs, the high-performance parasitic body diode of SiC MOSFETs is often leveraged to directly replace the external anti-parallel diode [12,13]. This results in the body diode becoming the primary conduction path for surge current. During service, SiC MOSFETs may endure repetitive surge current impacts, subjecting the devices to cyclic high-temperature and high-current stress. Such conditions can induce performance degradation in the devices, thereby affecting overall system efficiency. Consequently, conducting repetitive surge tests on SiC MOSFETs and investigating the degradation behavior and physical mechanisms hold significant academic value and engineering significance.

Existing studies have investigated this issue. Ma et al. [14] conducted repetitive surge tests on SiC MOSFETs under negative gate bias, observing negative drift in threshold voltage (V_TH), increased gate leakage current (I_GSS), elevated on-resistance (R_DS(ON)), and increased body diode forward voltage drop (V_SD). The degradation primarily originates from bond wire aging and gate oxide damage. Zhu et al. [15] performed tests under gate-source short-circuit condition and noted no significant V_TH drift, but observed increases in V_SD and R_DS(ON), with bipolar degradation being the dominant mechanism. Jiang et al. [16] investigated the effects of surge current magnitude, gate turn-off voltage, and stress cycles on devices, finding significant drift in static parameters such as V_TH, R_DS(ON), V_SD, and drain leakage current (I_DSS). Wang et al. [17] conducted repetitive surge tests on asymmetric trench SiC MOSFETs under different gate voltages and ambient temperatures, similarly observing negative V_TH shift and increases in V_SD and R_DS(ON). Zhan et al. [18] evaluated surge reliability in a series of planar-gate SiC MOSFETs with different P-well designs under gate-source voltage (V_GS) of −10 V, noting varying degrees of degradation in static characteristics. These studies uncover the performance degradation and underlying mechanisms in SiC MOSFETs under repetitive surge current, yet all focus on static characteristics and pay insufficient attention to the degradation of dynamic characteristics (switching characteristics). As switching devices, the dynamic characteristics of SiC MOSFETs are equally critical.

To address this gap, this paper conducts repetitive surge tests on SiC MOSFETs, focusing on the degradation behavior and mechanisms of their switching characteristics. After subjecting the devices to repetitive surge current stress, the turn-on process exhibits minimal changes, while the turn-off process is significantly affected. These alterations are considered closely related to the degradation of V_TH, gate-source capacitance (C_GS), and gate-drain capacitance (C_GD). The observed parametric shifts are attributed to an increase in positive trapped charge density within the oxide layer overlying the channel and junction field-effect transistor (JFET) regions.

2. Materials and Methods

A surge current generator is used to produce a half-sinusoidal surge current with a peak of 110 A, corresponding to about three times the rated current (36 A) and 60% of the maximum surge withstand capability (about 190 A). This level is selected to induce observable cumulative degradation while avoiding premature failure. The pulse duration is set to 10 ms to simulate the surge waveform typical of a 50 Hz AC grid fault. A 20 s interval between consecutive surge pulses is implemented to allow sufficient heat dissipation, ensuring that the device fully cools down before each surge stress application. This guarantees that every stress cycle starts from an identical thermodynamic initial state. Consequently, the observed performance degradation can be attributed solely to the cumulative damage from repeated electrical-thermal stress, thereby eliminating any interference from thermal accumulation in the analysis of the degradation mechanism. During testing, the device under test (DUT) is biased at a gate-source voltage of −5 V by a DC power supply. This setup ensured that during surge events, the current is confined to the body diode. The corresponding source-drain current (I_SD) and voltage (V_SD) waveforms are measured using a Hall-effect current sensor and a passive voltage probe, respectively, as shown in Figure 1b.

The electrical characterization of the DUT is conducted at every 1000-cycle interval, during which the surge current test is temporarily paused. This procedure is repeated until a gate-source short-circuit failure occurs after 4200 cycles. To characterize switching characteristics, the double-pulse test circuit shown in Figure 1c is utilized. The upper arm employs a device identical to the DUT, with its V_GS set to −5 V to ensure current flow through its body diode during freewheeling. For the DUT, the turn-off gate voltage (V_Goff) is set to −5 V, the turn-on gate voltage (V_Gon) to 20 V, and the DC bus voltage (V_DC) to 800 V. The load inductance (L) is 500 μH, and the load current (I_Load) is set to 20 A. To amplify the degradation of switching characteristics, the external gate resistance (R_G) is set to 160 Ω. Figure 1d shows the printed circuit board (PCB) used for the double-pulse test. During testing, the DUT’s drain-source voltage (V_DS) is measured using a differential voltage probe, the drain-source current (I_DS) via a coaxial cable, and V_GS using an optically isolated probe. To analyze the causes of switching characteristics degradation, the transfer characteristics and parasitic capacitances of the DUT are measured before and after repetitive surge current using an Agilent B1500A Semiconductor Analyzer (Keysight Technologies, Santa Rosa, CA, USA). For transfer characteristics, the gate and drain are shorted (V_G = V_D), and V_TH is extracted at I_DS = 10 mA. For parasitic capacitance characterization, the gate and source are shorted (V_G = V_S) with a small-signal frequency f = 1 MHz and AC amplitude V_AC = 25 mV. Additionally, to assess the degradation of the oxide layer, the capacitance-voltage (C-V) characteristics are measured using an Agilent E4990A Impedance Analyzer (Keysight Technologies, Santa Rosa, CA, USA) before and after repetitive surge current, with the drain and source shorted (V_D = V_S), f = 1 MHz, and V_AC = 25 mV. The high measurement frequency of 1 MHz minimizes the contribution of interface states to the capacitance, thereby facilitating the analysis of the polarity and distribution of oxide trap charges [19]. All tests are conducted at room temperature (25 °C). To ensure the reproducibility and reliability of the results, three DUTs are employed in the experiments.

3. Results

3.1. Degradation of Switching Characteristics

Figure 2a and Figure 2b, respectively, illustrate the evolution of the device’s turn-on and turn-off waveforms with increasing surge current cycles. It can be observed that the turn-on waveforms remain essentially unchanged, while the turn-off waveforms exhibit a significant delay.

To quantitatively characterize the degradation of the switching characteristics, the switching times and switching losses are extracted. The switching times include the turn-on time (t_on) and turn-off time (t_off), where t_on comprises the turn-on delay time (t_d(on)) and rise time (t_r), while t_off comprises the turn-off delay time (t_d(off)) and fall time (t_f). Switching losses include the turn-on loss (E_ON) and turn-off loss (E_OFF). The sum of the two is the total loss (E_SW). The extraction of all these parameters strictly adheres to the IEC 60747-8 standard [20].

Figure 3a,b presents the variations of switching times with increasing surge current cycles, respectively. It can be observed that as the cycle count increases, t_d(on) and t_r remain essentially unchanged, resulting in nearly constant t_on. In contrast, t_d(off) and t_f progressively increase, leading to prolonged t_off. After 4000 surge current cycles, the DUT exhibits a 23.7 ns extension in t_d(off) (a 9% increase) and a 7.7 ns extension in t_f (a 7.5% increase). To investigate the primary causes of these switching time variations, the following expressions may be analyzed [21,22]:

$$t_{\mathrm{d}(\mathrm{on})}=R_{\mathrm{G}}(C_{\mathrm{GS}}+C_{\mathrm{GD}})\ln ({\displaystyle \frac{V_{\mathrm{Gon}}-V_{\mathrm{Goff}}}{V_{\mathrm{Gon}}-V_{\mathrm{GP}}}}),$$

(1)

$$t_{\mathrm{r}}={\displaystyle \frac{C_{\mathrm{GD}}{R}_{\mathrm{G}}}{V_{\mathrm{Gon}}-V_{\mathrm{GP}}}}{V}_{\mathrm{DC}},$$

(2)

$$t_{\mathrm{d}(\mathrm{off})}=R_{\mathrm{G}}(C_{\mathrm{GS}}+C_{\mathrm{GD}})\ln ({\displaystyle \frac{V_{\mathrm{Gon}}}{V_{\mathrm{GP}}}}),$$

(3)

$$t_{\mathrm{f}}={\displaystyle \frac{C_{\mathrm{GD}}{R}_{\mathrm{G}}}{V_{\mathrm{GP}}-V_{\mathrm{Goff}}}}{V}_{\mathrm{DC}}.$$

(4)

Here, V_GP denotes the Miller plateau voltage. C_GS, C_GD, and V_GP are susceptible to variations induced by gate bias and surge current, while other parameters such as R_G, V_Gon, V_Goff, and V_DC remain unaffected and essentially constant. Therefore, according to Equation (1), the change in t_d(on) is primarily dominated by C_GS, C_GD, and V_GP. It should be noted that during the t_d(on) phase, the DUT is subjected to a V_DC of approximately 800 V. At this point, C_GD is at its minimum value C_GD,min. Consequently, (C_GS + C_GD) is predominantly determined by C_GS, because C_GD,min is negligible compared to C_GS [23]. Additionally, combining with the expression [24]

$$V_{\mathrm{GP}}=V_{\mathrm{TH}}+\sqrt{{\displaystyle \frac{J_{\mathrm{on}}{W}_{\mathrm{cell}}{L}_{\mathrm{ch}}}{2{\mu }_{\mathrm{ni}}{C}_{\mathrm{ox}}}}},$$

(5)

V_GP is determined by V_TH. Therefore, the variation in t_d(on) is primarily influenced by changes in C_GS and V_TH. Based on the above analysis and combining Equations (2) and (4), the variations in t_r and t_f are mainly affected by C_GD and V_TH. During these two phases, V_DS undergoes significant changes. Since C_GD is strongly modulated by V_DS, its value also experiences substantial variations. Thus, more accurately, C_GD here should be represented by its average value, C_GD,av. Similarly, t_d(off) is affected by C_GS, C_GD, and V_TH, as shown in Equation (3). However, during this phase, the V_DS of the DUT is relatively small (approximately equal to the on-state voltage), and V_GS > V_TH. Consequently, (C_GS + C_GD) approximates the gate oxide capacitance C_OX. This capacitance is less susceptible to gate bias and surge current influences, so the variation in t_d(off) is primarily determined by V_TH.

Figure 4a shows the variations of E_SW, E_ON, and E_OFF with increasing surge current cycles. It can be observed that as the number of cycles increases, E_ON remains essentially unchanged, while E_OFF continuously rises, leading to a corresponding increase in E_SW. After 4000 cycles, E_OFF increases by 81.8 μJ, representing an 8.3% increase. The changes in switching losses can be explained by variations in their corresponding integration times [25]. Integration time refers to the time window over which the product of V_DS and I_DS is integrated to extract the switching loss, including the turn-on integration time (t_turn-on) and the turn-off integration time (t_turn-off). Furthermore, t_turn-on can be expressed as the sum of the current rise time (t_ir) and the voltage fall time (t_vf), while t_turn-off can be expressed as the sum of the voltage rise time (t_vr) and the current fall time (t_if). The definitions of these time intervals are shown in Figure 5 [25]. Switching loss, which stems from the overlap of I_DS and V_DS, is directly proportional to the integration time: a longer time increases the loss, while a shorter time reduces it. Figure 4b,c, respectively, shows the trends of t_turn-on and t_turn-off with increasing surge current cycles. It can be seen that t_turn-on shows almost no change; hence, E_ON remains essentially stable. Conversely, t_turn-off gradually lengthens with increasing cycles, causing E_OFF to increase accordingly. It can also be observed that the stability of t_turn-on stems from the offsetting effects of a shortened t_ir and a lengthened t_vf: after 4000 cycles, t_ir shortens by 2.1 ns (a decrease of approximately 1.7%), while t_vf lengthens by 3.3 ns (an increase of approximately 2.8%). On the other hand, the increase in t_turn-off is caused by the simultaneous lengthening of both t_vr and t_if. After the same 4000 cycles, t_vr lengthens by 8 ns (an increase of about 8%), and t_if lengthens by 5.1 ns (an increase of about 10.4%). The main reasons for the changes in integration time can be analyzed through the following equations [26]:

$$t_{\mathrm{ir}}=R_{\mathrm{G}}{(C}_{\mathrm{GS}}+C_{\mathrm{GD}})\ln ({\displaystyle \frac{V_{\mathrm{Gon}}-V_{\mathrm{TH}}}{V_{\mathrm{Gon}}-V_{\mathrm{GP}}}}),$$

(6)

$$t_{\mathrm{vf}}={\displaystyle \frac{R_{\mathrm{G}}{Q}_{\mathrm{GD}}}{V_{\mathrm{Gon}}-V_{\mathrm{GP}}}},$$

(7)

$$t_{\mathrm{vr}}={\displaystyle \frac{R_{\mathrm{G}}{Q}_{\mathrm{GD}}}{V_{\mathrm{GP}}-V_{\mathrm{Goff}}}},$$

(8)

$$t_{\mathrm{if}}=R_{\mathrm{G}}(C_{\mathrm{GS}}+C_{\mathrm{GD}})\ln ({\displaystyle \frac{V_{\mathrm{GP}}}{V_{\mathrm{TH}}-V_{\mathrm{Goff}}}}).$$

(9)

Among them, Q_GD represents the gate-drain charge. According to Equation (6), the variation in t_ir is primarily influenced by C_GS, C_GD, and V_TH. However, during this stage, the DUT satisfies V_GS > V_TH, and the channel is in a strong inversion state. At this point, C_GS can be regarded as the oxide layer capacitance, which is less susceptible to gate bias and surge current influences. Simultaneously, since V_DS ≈ V_DC, C_GD is at its minimum value C_GD,min, which is negligible compared to C_GS. Therefore, the variation in t_ir is actually dominated solely by V_TH. Based on Equations (7) and (8), t_vf and t_vr are mainly affected by Q_GD and V_GP (i.e., V_TH). The magnitude of Q_GD is proportional to C_GD,av. Similarly, according to Equation (9), t_if is also influenced by C_GS, C_GD, and V_TH. Based on the same mechanism as t_ir, its variation is ultimately determined solely by V_TH.

Figure 4. Variations in switching losses and integration times with increasing surge current cycles. (a) Total loss (E_SW), turn-on loss (E_ON), and turn-off loss (E_OFF); (b) turn-on integration time (t_turn-on), current rise time (t_ir), and voltage fall time (t_vf); (c) turn-off integration time (t_turn-off), voltage rise time (t_vr), and current fall time (t_if).

Figure 4. Variations in switching losses and integration times with increasing surge current cycles. (a) Total loss (E_SW), turn-on loss (E_ON), and turn-off loss (E_OFF); (b) turn-on integration time (t_turn-on), current rise time (t_ir), and voltage fall time (t_vf); (c) turn-off integration time (t_turn-off), voltage rise time (t_vr), and current fall time (t_if).

Figure 5. The schematic diagram of integration time definition.

Figure 5. The schematic diagram of integration time definition.

3.2. Degradation Mechanism Analysis

In light of the preceding analysis, V_TH, C_GS, and C_GD emerge as the key parameters governing the device’s switching times and losses (integration times). Therefore, this paper monitors these key parameters. Figure 6a, b, and c shows the variations in the transfer characteristics curve, C_GS-V_DS curve, and C_GD-V_DS curve with increasing cycle numbers, respectively. A negative V_TH shift of approximately 0.12 V is observed after 4000 surge current cycles. C_GS increases across the entire V_DS range with increasing cycles. In contrast, C_GD increases only within the low V_DS range and remains largely unchanged at high voltage. Consequently, C_GD,av gradually increases with the number of cycles.

Based on the trends of the key parameters described above, the drift mechanisms of switching times and integration times can be reasonably explained. Regarding switching times, the stability of t_d(on) is attributed to the counteracting effects of decreased V_TH and increased C_GS: Equation (1) indicates that a reduction in V_TH shortens t_d(on), while an increase in C_GS lengthens it, resulting in minimal overall change. Similarly, the stability of t_r arises from the combined influence of decreased V_TH and increased C_GD,av: according to Equation (2), lower V_TH reduces t_r, while higher C_GD,av extends it, leading to overall stability. The lengthening of t_d(off) primarily stems from reduced V_TH, as shown in Equation (3), while the extension of t_f is jointly caused by decreased V_TH and increased C_GD,av, as specified in Equation (4). Regarding integration times, based on Equations (6) and (9), both the shortening of t_ir and lengthening of t_if originate from reduced V_TH. The extension of t_vf is predominantly driven by increased C_GD,av, as described in Equation (7). The lengthening of t_vr arises from the synergistic effects of reduced V_TH and increased C_GD,av, as established in Equation (8).

The observed decrease in V_TH results from a higher positive trapped charge density (Q_pos) in the oxide. The expression for V_TH is given by [27]

$$V_{\mathrm{TH}}={\displaystyle \frac{\sqrt{4{\epsilon }_{\mathrm{S}}kT{N}_{\mathrm{B}}\ln \left(N_{\mathrm{B}}/n_{\mathrm{i}}\right)}}{C_{\mathrm{OX}}}}+{\displaystyle \frac{2kT}{q}}\ln \left({\displaystyle \frac{N_{\mathrm{B}}}{n_{\mathrm{i}}}}\right)+{\Phi }_{\mathrm{ms}}-{\displaystyle \frac{Q_{\mathrm{pos}}}{C_{\mathrm{OX}}}}+{\displaystyle \frac{Q_{\mathrm{neg}}}{C_{\mathrm{OX}}}},$$

(10)

where ε_S is the absolute permittivity of SiC, Φ_ms represents the work function difference between the gate material (poly-Si) and SiC, C_OX denotes the oxide capacitance, k is Boltzmann’s constant, T is absolute temperature, N_B is the doping concentration, n_i is the intrinsic carrier concentration, and q is the electron charge. All of these parameters remain constant under stress conditions. Only Q_pos and Q_neg, representing the density of positive and negative trapped charge, respectively, are susceptible to gate bias and surge current influences. Consequently, the negative shift in V_TH is attributed to an increase in Q_pos. These charges create an assisting electric field that lowers V_TH by promoting inversion layer formation.

The increase in C_GS and C_GD can be attributed to the accumulation of Q_pos in the gate oxide overlying the channel and JFET regions, respectively. Under gate-source short-circuit conditions, this Q_pos buildup in the channel oxide generates an electric field that reduces the P-well depletion width. Because capacitance is inversely proportional to depletion width, the narrowing directly raises C_GS. Similarly, Q_pos accumulation in the oxide above the JFET region attracts more electrons, narrowing the depletion layer in that area. This results in an increase in C_GD at low V_DS. However, at high V_DS, the depletion layer expands significantly. This expansion diminishes the modulating effect of Q_pos on the depletion layer, rendering C_GD nearly unchanged under high V_DS.

Therefore, the observed drift in V_TH, C_GS, and C_GD is primarily due to the accumulation of Q_pos in the gate oxide overlying the channel and JFET regions. To verify this conclusion, C-V characterization is performed on the device pre- and post-repetitive surge current stress, with the results presented in Figure 7. According to the interface damage theory, the C-V curve is typically divided into five regions [19]. The results reveal that as the surge cycles increase, the curves in Region II and Region IV both exhibit a negative shift. This shift is a characteristic signature of increased Q_pos in the gate oxide. The shift in Region II indicates degradation of the JFET region’s gate oxide, while the shift in Region IV corresponds to degradation above the channel region. These results directly confirm that Q_pos accumulation occurs in the gate oxide overlying the channel and JFET regions after repetitive surge current.

The generation of Q_pos in the gate oxide is closely linked to the synergistic interaction between negative gate bias voltage and cyclic high temperature induced by repetitive surge current. Figure 8 shows the energy band diagrams of the gate stack, corresponding to the channel and JFET regions, as well as the process of hole trapping by oxide traps during surge current stress. Under V_GS= −5 V, a high density of holes accumulates beneath the oxide layer in the channel and JFET regions. In the energy band diagram, this is manifested by the valence band edge moving closer to the Fermi level, which creates conditions favorable for hole injection into the oxide layer. The surge current can generate a very high instantaneous current density and power density in the active area of the chip, thereby producing a significant amount of Joule heat within the chip. Due to the effects of device thermal resistance and heat capacity, this heat cannot dissipate immediately, leading to a rapid rise in the chip’s junction temperature. At the cell level, under V_GS= −5 V, the regions with the highest temperature are primarily the source metal, the gate region, and the body diode. Driven by the gate electric field and the high temperature, holes located at the bottom of the oxide layer can enter the oxide via a tunneling mechanism and become trapped by pre-existing hole traps within the oxide, rendering the traps positively charged. These hole traps belong to near-interfacial oxide defects associated with oxygen vacancies, known as E’-type defects. Structurally, an E’-type defect is characterized by a silicon dangling bond, where a silicon atom bonded to three oxygen atoms hosts an unpaired electron. The high temperature generated by the surge not only promotes hole injection, but also provides activation energy, causing the breaking of certain weak Si-Si bonds (precursors to E’-type defects) within the oxide. These bonds can also be broken during the hole trapping process. This leads to an increase in E’-type defects, which can, in turn, trap more holes [28,29,30]. Finally, under repetitive surge current cycles, the aforementioned process occurs continuously. This results in the continuous generation of new defects, enabling the trapping of an increasing number of holes, and ultimately leading to the continuous accumulation of Q_pos. This subsequently drives the degradation of V_TH, C_GS, and C_GD, ultimately causing drift in the device’s switching times and switching losses.

4. Conclusions

This study investigates the degradation behavior and physical mechanisms of switching characteristics in planar-gate SiC MOSFETs under repetitive surge current. Experimental results demonstrate that after 4000 surge current cycles, the turn-on process remains largely unchanged, with no significant variations in t_d(on), t_r, or E_ON. Conversely, the turn-off process exhibits significant delays, with t_d(off), t_f, and E_OFF increasing by 9%, 7.5%, and 8.3%, respectively. The primary factors driving these changes in switching characteristics are the reduction in V_TH and the increase in C_GS and C_GD. The decrease in V_TH and increase in C_GS result from the accumulation of Q_pos within the gate oxide overlying the channel region. Similarly, the increase in C_GD stems from Q_pos accumulation in the gate oxide overlying the JFET region. These conclusions are experimentally validated by the leftward shift of C-V characteristic curves with increasing cycle counts. The accumulation of Q_pos in the gate oxide arises from the combined effects of negative gate bias and cyclic high temperature induced by repetitive surge current. The negative gate bias induces hole accumulation beneath the oxide layer. Assisted by the gate electric field and the elevated junction temperature, these holes enter the oxide via a tunneling mechanism and become trapped by hole traps, specifically E’-type defects. Simultaneously, the high temperature and the hole trapping process can activate more of such defects, thereby enabling the oxide layer to capture more holes. As the number of cycles increases, the oxide layer is continuously subjected to the influence of the gate electric field and high temperature, causing the processes of hole trapping and trap generation to proceed continuously and leading to the accumulation of Q_pos. This process triggers the degradation of V_TH, C_GS, and C_GD, and ultimately results in nearly unchanged turn-on time and turn-on loss, but increased turn-off time and turn-off loss of the device. This study not only deepens the understanding of the impact of surge current on devices, but also lays a preliminary foundation for lifetime assessment under repetitive surge current stress. In the future, testing will be conducted at multiple stress levels (e.g., varying surge current magnitudes and temperatures) to gather sufficient data for establishing a more accurate lifetime model.