Search Results (244)

Hand-drawn circuit diagrams remain common in education, maintenance, and early-stage design and are often photographed for storage, sharing, and reuse. Recovering electrically meaningful structure from such camera-acquired images is difficult because irregular strokes, wire discontinuities, crossings, symbol–text interference, and imaging artifacts can disrupt valid circuit topology. We therefore formulate the task as topology recovery with semantic completion rather than symbol recognition alone. To solve it, we propose a topology-consistent structural parsing framework that integrates multi-source visual perception, wire connected-component-guided connectivity reasoning, and explicit endpoint semantic recovery for direction-sensitive and multi-terminal components. On an independent benchmark of 1317 hand-drawn circuit diagrams, the proposed method achieves a 95.14% strict image-level end-to-end success rate. The recovered structures are further exported as Simulation Program with Integrated Circuit Emphasis (SPICE)-compatible netlists for downstream simulation and verification. These results support a practical vision-based image acquisition and processing workflow for converting camera-acquired hand-drawn circuit images into machine-readable and simulation-ready circuit representations. Full article

This paper presents a rule-based LVS-driven methodology for parasitic RC extraction from CMOS layouts for post-layout SPICE simulation. The proposed approach operates directly within foundry-qualified rule environments, ensuring consistency with Process Design Kits (PDKs) and enabling seamless integration with existing design and verification flows without requiring field-solver execution during the production extraction flow. The methodology provides a generalized framework for deriving electrical parameters from layout geometries and is applicable to interconnects, contacts, vias, and gate structures in multilayer CMOS technologies. By decomposing conductive regions into directional components and applying geometric and Boolean operations, the method captures the impact of layout topology and process-dependent features on circuit-level behavior. In addition, a model-order reduction technique based on π-equivalent representations is introduced to simplify the resulting networks while preserving timing accuracy. This enables the scalable simulation of complex layouts with reduced computational overhead. The proposed framework supports layout optimization, variability-aware design, and process-technology co-design, particularly for mature and advanced planar nodes. The methodology is evaluated using register-file layout test cases and post-layout SPICE simulations. The results show that the proposed rule-based extraction and RC-merging flow preserve timing behavior while reducing netlist complexity. Full article

This paper presents a behavioral-level, pre-silicon analytical co-design framework for memristor read–write interfaces, intended to establish closed-form design rules that subsequently guide SPICE-level and silicon-level realizations. Memristor-based neural hardware requires interfaces that can program resistance states efficiently while suppressing read disturbance, yet existing designs typically rely on empirical tuning without closed-form analytical rules. We close this gap by deriving a single closed-form operating-window inequality $(v_{\mathrm{on}}<V_{\mathrm{rd}}<v_{\mathrm{off}},V_{\mathrm{wr}}\ge V_{\mathrm{wr}}^{min}\left(T_{\mathrm{wr}}\right))$ from the VTEAM state equation, embedding it in an Energy–Delay–Accuracy (EDA) cost function, and validating the resulting parameter set hierarchically up to MNIST-scale inference. The main finding is that this analytically derived parameter set simultaneously achieves a 96.08% set-cycle energy saving and 90.6% MNIST top-1 accuracy (1.2% below software baseline) under realistic D2D/C2C variability, with every measured number agreeing with its analytical prediction within 2%. The framework is instantiated with a two-phase over-threshold-write and sub-threshold-read timing strategy together with a mutually exclusive PMOS-NMOS path-isolation topology, evaluated through behavioral-level MATLAB simulation under linear-drift and VTEAM models. Behavioral simulation confirms each analytical bound within 2%: a 13.78× resistance window with $\le 0.008\%$ cycle-to-cycle drift, 5.01% read-current CV, and 30.94%/96.08% Reset/Set energy savings versus a no-separation baseline. Transistor-level non-idealities (slew rate, charge injection, RTN, retention aging, peripheral overhead) are bounded analytically; full SPICE/silicon validation is identified as immediate follow-up work. These results establish a reusable, analytically grounded reference design that bridges memristive device modeling, circuit-level interface implementation, and neural network-level usability. Full article

Two-transistor zero-capacitor (2T0C) DRAM has attracted attention as an alternative memory due to its high potential for monolithic 3D integration (M3D). However, conventional 2T0C DRAM consists of four terminals, requiring large contact and peripheral area in the array. Moreover, selective read-out in the array has not been sufficiently addressed, as half-selected cells are susceptible to unintended current. To address this, two types of three-terminal 2T0C DRAM, bit-line-shared (BLS) and word-line-shared (WLS), were implemented, together with an offset bias scheme that enables selective read by applying complementary biases to the read terminals. Both structures exhibited retention times exceeding 800 s, comparable to conventional 2T0C DRAM. Array-level read selectivity and sensing margin were evaluated through SPICE simulations under various parasitic capacitance and offset bias conditions. Under optimized conditions, read selectivity values of 1.63 × 10⁵ and 1.51 × 10⁵ were achieved for the BLS and WLS structures, respectively. Notably, the WLS structure exhibited a selected cell on-current of approximately 0.17 μA, one order of magnitude higher than that of the BLS structure. This on-current advantage is analytically attributed to the structural decoupling of write-induced V_SN drop and read-induced V_GS enhancement in the WLS configuration. These results establish the WLS three-terminal 2T0C DRAM with the offset bias scheme as a more favorable configuration for high-density array implementation. Full article

Passive components in integrated circuits occupy significant areas and increase production costs, driving the demand for compact alternatives. This study presents a generalized, electronically controllable positive/negative floating impedance multiplier implemented in TSMC 180 nm CMOS technology. To achieve a compact layout, the architecture utilizes custom-designed operational transconductance amplifiers (OTAs). The circuit operates on a lossless principle, scaling resistance, capacitance, and inductance values within a wide multiplication range of −100 to +100 using only a single base element. Comprehensive LTspice simulations including PVT, Monte Carlo, THD, and noise analyses verify the design’s stable operation, low distortion, and favorable noise characteristics across various filter configurations. Furthermore, practical feasibility is validated through SPICE simulations using commercial LM13700 OTA, confirming consistent behavior for real-world applications. The proposed active topology occupies a compact core area of only 5831 μm². By scaling down large passive components, this design decreases the overall system-level footprint, providing a versatile and area-efficient solution for tunable analog IC applications. It should be noted that the reported 5831 μm² corresponds to the active core only, while the effective system-level area benefit depends on the selected base impedance and the target application. Full article

Adaptive beamforming based on polarization-sensitive arrays enables joint spatial–polarization filtering for mainlobe interference suppression, but mainlobe distortion and performance degradation occur when the received data include the desired signal or multiple mainlobe interferences. Accordingly, this paper proposes a mainlobe interference suppression method based on Polarimetric Sparse Iterative Covariance-based Estimation (POL-SPICE) and covariance matrix reconstruction. This method utilizes the POL-SPICE algorithm to accurately estimate the direction of arrival (DOA), polarization, and power parameters. It reconstructs the covariance matrix by nulling the corresponding source power and constructs a feature projection matrix to preprocess the received signal. These eliminate the impact of the desired signal and mainlobe interference components on subsequent joint spatial–polarization domain beamforming, ultimately achieving interference suppression and mainlobe shape preservation. Simulation results illustrate that the proposed method is applicable to scenarios with the coexistence of the desired signal and multiple mainlobe interferences, and its superiority over existing methods is verified. Full article

This paper presents a novel extra-X second-generation current-controlled conveyor (EX-CCCII) with controllable current gain. Unlike the conventional EX-CCCII, the proposed EX-CCCII provides a controllable current gain between the $x$- and $z$-terminals. To demonstrate the advantages of the EX-CCCII with the controllable current gain, the proposed EX-CCCII is employed to realize a universal current-mode filter and a three-phase current-mode oscillator. The universal filter can realize five standard filtering responses (low-pass, high-pass, band-pass, band-stop, and all-pass) using the same topology. The current gains of these filters can be controlled through the current gain of the EX-CCCII, while the natural frequency of the universal filter can be electronically tuned via the intrinsic resistance at the x-terminal. When the proposed EX-CCCII is used to implement the three-phase oscillator, the condition of oscillation can be adjusted through the current gain of the EX-CCCII, whereas the oscillation frequency can be tuned using the parasitic resistance of the x-terminals. The proposed EX-CCCII and its applications were verified through SPICE simulations using the transistor model parameters NR100N (NPN) and PR100N (PNP) of the bipolar array ALA400-CBIC-R from AT&T to confirm the functionality and feasibility of the proposed topologies. Furthermore, experimental verification of the EX-CCCII and its integration into a three-phase oscillator further substantiates the proposed concept and demonstrates its practical viability. Full article

Mixed-signal simulation is indispensable for verifying modern integrated circuits that tightly couple analog and digital subsystems, yet the field lacks a unified framework for systematically comparing its diverse methodologies. This paper addresses that gap by proposing a novel three-axis taxonomy that classifies simulation methods along abstraction level, solver methodology, and analysis type, together with a comparative evaluation framework based on five quantitative metrics: accuracy, throughput, capacity, convergence reliability, and scalability. Applying this framework, we systematically compare thirteen classical method categories—spanning SPICE, FastSPICE, RF/periodic steady-state, behavioral modeling, co-simulation, and model order reduction—and eight AI/ML approaches including Gaussian process surrogates, graph neural networks, physics-informed neural networks, Bayesian optimization, and reinforcement learning. Our analysis reveals a clear maturity stratification: classical methods remain the only signoff-accurate approaches, Bayesian optimization represents the most industrially validated AI contribution with integration across all three major EDA platforms, while Neural ODE solvers and LLM-based design tools remain at the research stage. We identify a persistent academic-to-industry gap driven by foundry model complexity, limited benchmark diversity, and topology-specific overfitting. The proposed taxonomy and comparative framework provide practitioners with structured guidance for simulation method selection and highlight specific research directions needed to bridge the gap between AI promise and industrial deployment. Full article

Recent advances in energy storage systems and in increasingly efficient, safe, and energy-dense cell chemistries have driven the need for commercial Battery Management System (BMS) architectures with greater control, data acquisition, and communication capabilities, primarily oriented towards customization. This demand introduces a significant change in how electrical systems are modeled and simulated when they integrate active electrochemical elements such as lithium-ion cells. This work presents the development and modeling of a BMS for critical and high-efficiency applications, based on active balancing techniques and incorporating an additional safety stage to respond to failures when charging ${\mathrm{LiFePO}}_4$ cells. The electrochemical model was built using an equivalent RLC circuit and RC pairs to represent the Thevenin response of the cell. For the simulation of active balancers, LTspice was employed, while charging and discharging processes and their effects on state of charge (SOC) and state of health (SOH) were complemented through analysis in MATLAB R2024a.The proposed approach offers an efficient tool for evaluating cell dynamics and validating battery management strategies in demanding scenarios. While the current approach prioritizes the individual modeling of electrical conversion systems, our framework presents an innovative multisystem macromodel, where not only is the electrical behavior simulated but also the control, efficiency, and safety of the system are determined, prioritizing reproducibility through SPICE tools. Full article

This research presents an improved version of the Jiles–Atherton (J.-A.) ferromagnetic core model. The presented model eliminates the distortion of minor hysteresis loops and achieves better matching with measured data for minor loops—a well-known weak point of the unmodified J.-A. model. The proposed J.-A. model extension is backward compatible with the basic model version and requires two or four additional parameters. In addition to providing model equations, this paper considers the practical implementation of the improved J.-A. model using SPICE circuit simulation tools. The developed modular SPICE macromodel set is compatible with both open-source and proprietary circuit simulation software, and it allows for the construction of transformer schematics of any complexity. The proposed model shows a good match with measurement results for hysteresis loops and transient waveforms in transformer circuits. Full article

This paper proposes a corner analysis approach for CMOS circuits taking into the account radiation effects. The presented simulation approach is implemented using the open-source design automation (EDA) software QUCS-S 25.2.0 and Ngspice 45. It was developed a radiation-sensitive field-effect transistor (RADFET) SPICE macromodel representing threshold voltage shift versus radiation dose. The extraction procedure for this model is based on statistical measurements of pMOS transistors and process corner models (Slow, Typical, Fast) and involves percentile analysis. The article proposes an original design of the RADFET-based radiation sensor with RADFET device and CMOS readout circuit placed on the same die, which allows us to simplify the dosimeter schematic. The sensor output parameter dependency on process parameters, supply voltage, and temperature was investigated using the proposed simulation approach. Full article

The downscaling of VLSI technologies has exacerbated the susceptibility of integrated circuits (ICs) to radiation-induced Single-Event Transients (SETs). This work presents UPSET, a comprehensive and technology-independent EDA framework for probabilistic SET analysis using Static Timing Analysis (STA). Unlike traditional simulation-based methods that suffer from prohibitive runtimes, UPSET leverages graph-based propagation with advanced logical, electrical, and timing-window masking models to evaluate circuit sensitivity efficiently. Key contributions include a novel “Electrical Masking Window” (EMW) criterion that effectively filters non-full-rail pulses early in reconvergent logic and a TimeStamp-based propagation mode that accurately handles complex signal reconvergence with Boolean evaluation. The experimental results over some featured benchmarks demonstrate a speedup of more than 25,000× compared with SPICE while maintaining a tight 4.56% error bound in pulse width estimation. Moreover, experimental validation on 50 benchmarks across varying complexities showcases that EMW enhancement reduces the pessimism to circuit sensitivity by up to 25% on average, providing tighter upper bounds while maintaining scalability to million-gate designs. By integrating seamlessly with standard industrial formats (LEF, DEF, LIB, or SPEF), UPSET enables scalable, accurate soft SET sensitivity assessment for modern digital designs, establishing a robust foundation for automated radiation hardening flows. Full article

Firm requirements on electromagnetic compatibility (EMC) of electronic devices demand low electromagnetic emissions (EMI) of high-speed circuits, especially in the automotive industry. To be able to apply cost-effective anti-perturbative measures that reduce noise emission, critical signal integrity and power integrity (SI/PI) tools are needed for developing high-speed printed circuit board (PCB) designs. This paper presents an efficient method for modeling and analyzing the current drawn by digital ICs based on SPICE modeling data. The profile of the current drawn by the ICs from the power supply is composed of the static supply current and the dynamic supply current. This method enables power integrity engineers, in particular, PhD students and researchers who aim to develop an intuitive understanding of PI phenomena during the pre-layout phase, to see the hidden impact of the supply current on the power rail noise through time domain simulations, using a complex simulation model that integrates the Finite-Difference Time-Domain (FDTD) method of modeling the power and ground plane, with Voltage Regulator Modules (VRMs) and decoupling capacitors. A comparison of simulation results between the proposed models and SPICE IC models is also included to validate the proposed model. Full article

This paper reports the results of a system-level total ionizing dose (TID) effect simulation study on a SMIC 130 nm LEON2 processor. Firstly, the device-level simulations of the 130 nm NMOS transistors are performed using the Sentaurus TCAD software to analyze the effects of a bias condition, channel width, and irradiation dose on a TID-induced leakage current. Based on the TCAD simulation results, a Verilog-A-based compact model is developed for NMOS transistors to describe the TID-induced leakage current, and it is then embedded into target nodes of the SPICE netlist for the LEON2 processor, enabling system-level TID simulations. The simulation results reveal the processor’s failure threshold and corresponding failure mechanism; meanwhile, the increase in the power supply current with the irradiation dose is also observed. The research reported in this paper can provide beneficial guidance for radiation performance evaluation and radiation hardening by design (RHBD) in 130 nm bulk CMOS processors. Full article

This work presents a unified framework for multiobjective analog circuit optimization that combines surrogate modeling, uncertainty-aware evolutionary search, and adaptive high-fidelity verification. The approach integrates ensemble regressors and graph-based surrogate models with a closed-loop multi-fidelity controller that selectively invokes SPICE evaluations based on predictive uncertainty and diversity criteria. The framework includes reproducible caching, metadata tracking, and process- and Dask-based parallelism to reduce redundant simulations and improve throughput. The methodology is evaluated on four CMOS operational-amplifier topologies using NSGA-II, NSGA-III, SPEA2, and MOEA/D under a uniform configuration to ensure fair comparison. Surrogate-Guided Optimization (SGO) replaces approximately 96.5% of SPICE calls with fast model predictions, achieving about a 20× reduction in total simulation time while maintaining close agreement with ground-truth Pareto fronts. Multi-Fidelity Optimization (MFO) further improves robustness through adaptive verification, reducing SPICE usage by roughly 90%. The results show that the proposed workflow provides substantial computational savings with consistent Pareto-front quality across circuit families and algorithms. The framework is modular and extensible, enabling quantitative evaluation of analog circuits with significantly reduced simulation cost. Full article