Search Results (928)

The Network-on-Chip applications’ performance and efficiency depend on task allocation and message routing, which are complex problems. The existing solutions assign priorities to messages in order to regulate their transmission. Unfortunately, this message classification can lead to routings that block the best global solution. In this work, we propose to use the Hungarian algorithm to dynamically route messages with the minimal cost, i.e., minimizing the communication times while consuming the least energy possible. To meet the real-time constraints coming from requiring results at each flit transmission, we also suggest a hardware version of it, which reduces the processing time by an average of 42.5% with respect to its software implementation. Full article

In Network-on-Chip (NoC) research, the task mapping problem has attracted considerable attention as a core issue influencing system performance. As an NP-hard problem, it remains challenging, and existing algorithms exhibit limitations in both mapping quality and computational efficiency. To address this, a method named ET (Enhanced Coati Optimization Algorithm) is proposed, which leverages the nature-inspired Coati Optimization Algorithm (COA) for task mapping. An incremental hill-climbing strategy is integrated to improve local search capabilities, and a dynamic mechanism for adjusting the exploration–exploitation ratio is designed to better balance global and local searches. Additionally, an initial mapping strategy based on spectral clustering is introduced, which utilizes inter-task communication strength to cluster tasks, thereby improving the quality of the initial population. To evaluate the effectiveness of the proposed algorithm, the performance of the ET algorithm is compared and analyzed against various existing algorithms in terms of communication cost, energy consumption, and latency, using both real benchmark task maps and randomly generated task maps. Experimental results demonstrate that the ET algorithm consistently outperforms the compared algorithms across all performance metrics, thereby confirming its superiority in addressing the NoC task mapping problem. Full article

In resistive polymer humidity sensors, the quality of the resistor chips directly affects the performance. Detecting chip defects remains challenging due to the scarcity of defective samples, which limits traditional supervised-learning methods requiring abundant labeled data. While few-shot learning (FSL) shows promise for industrial defect detection, existing approaches struggle with mixed-scene conditions (e.g., daytime and night-version scenes). In this work, we propose a crossed wavelet convolution network (CWCN), including a dual-pipeline crossed wavelet convolution training framework (DPCWC) and a loss value calculation module named ProSL. Our method innovatively applies wavelet transform convolution and prototype learning to industrial defect detection, which effectively fuses feature information from multiple scenarios and improves the detection performance. Experiments across various few-shot tasks on chip datasets illustrate the better detection quality of CWCN, with an improvement in mAP ranging from 2.76% to 16.43% over other FSL methods. In addition, experiments on an open-source dataset NEU-DET further validate our proposed method. Full article

Background/Objectives: Circulating tumor cells (CTCs) are important biomarkers for predicting prognosis and evaluating treatment efficacy in cancer. We developed the “CTC-Chip” system based on microfluidics, enabling highly sensitive CTC detection and prognostic assessment in lung cancer and malignant pleural mesothelioma. However, the final identification and enumeration of CTCs require manual intervention, which is time-consuming, prone to human error, and necessitates the involvement of experienced medical professionals. Medical image recognition using machine learning can reduce workload and improve automation. However, CTCs are rare in clinical samples, limiting the training data available to construct a robust CTC image recognition system. In this study, we established a highly accurate artificial intelligence-based CTC recognition system by pre-training convolutional neural networks using images from lung cancer cell lines. Methods: We performed transfer learning of convolutional neural networks. Initially, the models were pre-trained using images obtained from lung cancer cell lines. The model’s accuracy was improved by training with a limited number of clinical CTC images. Results: Transfer learning significantly improved the CTC classification accuracy to an average of 99.51%, compared to 96.96% for a model trained solely on pre-trained cell lines (p < 0.05). This approach showed notable efficacy when clinical training images were limited, achieving statistically significant accuracy improvements with as few as 17 clinical CTC images (p < 0.05). Conclusions: Overall, our findings demonstrate that pre-training with cancer cell lines enables rapid and highly accurate automated CTC recognition even with limited clinical data, significantly enhancing clinical applicability and potential utility across diverse cancer diagnostic workflows. Full article

Stealthy chip-level tamper attacks, such as hardware Trojan insertions or security-critical circuit modifications, can threaten modern microelectronic systems’ security. While traditional inspection and side-channel methods offer potential for tamper detection, they may not reliably detect all forms of attacks and often face practical limitations in terms of scalability, accuracy, or applicability. This work introduces a non-invasive, contactless tamper detection method employing a complementary split-ring resonator (CSRR). CSRRs, which are typically deployed for non-destructive material characterization, can be placed on the surface of the chip’s package to detect subtle variations in the impedance of the chip’s power delivery network (PDN) caused by tampering. The changes in the PDN’s impedance profile perturb the local electric near field and consequently affect the sensor’s impedance. These changes manifest as measurable variations in the sensor’s scattering parameters. By monitoring these variations, our approach enables robust and cost-effective physical integrity verification requiring neither physical contact with the chips or printed circuit board (PCB) nor activation of the underlying malicious circuits. To validate our claims, we demonstrate the detection of various chip-level tamper events on an FPGA manufactured with 28 nm technology. Full article

For data-intensive applications like edge AI and image processing, we present a new reconfigurable 8T SRAM-based in-memory computing (IMC) macro designed for high-performance and energy-efficient operation. This architecture mitigates von Neumann limitations through numerous major breakthroughs. We built a new architecture with an adjustable capacitance array to substantially increase the multiply-and-accumulate (MAC) engine’s accuracy. It achieves 10–20 TOPS/W and >95% accuracy for 4–10-bit operations and is robust across PVT changes. By supporting binary and ternary neural networks (BNN/TNN) with XNOR-and-accumulate logic, a dual-mode inference engine further expands capabilities. With sub-5 ns mode switching, it can achieve up to 30 TOPS/W efficiency and >97% accuracy. In-memory Hamming error correction is implemented directly using integrated XOR circuitry. This technique eliminates off-chip ECC with >99% error correction and >98% MAC accuracy. Machine learning-aided co-optimization ensures sense amplifier dependability. To ensure CMOS compatibility, the macro may perform Boolean logic operations using normal 8T SRAM cells. Comparative circuit-level simulations show a 31.54% energy efficiency boost and a 74.81% delay reduction over other SRAM-based IMC solutions. These improvements make our macro ideal for real-time AI acceleration, cryptography, and next-generation edge computing, enabling advanced compute-in-memory systems. Full article

To tackle the low-accuracy problem with analyzing urine component concentrations in real time, a fully automated dipstick analysis device of urine dry chemistry was designed, and a prediction method combining an image acquisition system with a whale optimization algorithm (WOA) for BP neural network optimization was proposed. The image acquisition system, which comprised an ESP32S3 chip and a GC2145 camera, was used to collect the urine test strip images, and then color data were calibrated by image processing and color correction on the upper computer. The correlations between reflected light and concentrations were established following the Kubelka–Munk theory and the Beer–Lambert law. A mathematical model of urine colorimetric value and concentration was constructed based on the least squares method. The WOA algorithm was applied to optimize the weight and threshold of the BP neural network, and substantial data were utilized to train the neural network and perform comparative analysis. The experimental results show that the MAE, RMSE and R² of predicted versus actual urine protein values were, respectively, 3.1415, 4.328 and approximately 1. The WOA-BP neural network model exhibited high precision and accuracy in predicting the urine component concentrations. Full article

This paper presents a mathematical formalism for generative artificial intelligence (GAI). Our starting point is an observation that a “histories” approach to physical systems agrees with the compositional nature of deep neural networks. Mathematically, we define a GAI system as a family of sequential joint probabilities associated with input texts and temporal sequences of tokens (as physical event histories). From a physical perspective on modern chips, we then construct physical models realizing GAI systems as open quantum systems. Finally, as an illustration, we construct physical models realizing large language models based on a transformer architecture as open quantum systems in the Fock space over the Hilbert space of tokens. Our physical models underlie the transformer architecture for large language models. Full article

Leveraging the human brain as a paradigm of energy-efficient computation, considerable attention has been paid to photonic neurons and neural networks to achieve higher computing efficiency and lower energy consumption. This study experimentally demonstrates on-chip silicon photonic neurons and neural networks based on thermally tunable microring resonators (MRRs) implement weighting and nonlinear operations. The weight component consists of eight cascaded MRRs thermally tuned within wavelength division multiplexing (WDM) architecture. The nonlinear response depends on the MRR’s nonlinear transmission spectrum, which is analogous to the rectified linear unit (ReLU) function. The matrix multiplication and recognition task of digits 2, 3, and 5 represented by seven-segment digital tube are successfully completed by using the photonic neural networks constructed by the photonic neurons based on the on-chip thermally tunable MRR as the nonlinear units. The power consumption of the nonlinear unit was about 5.65 mW, with an extinction ratio of about 25 dB between different digits. The proposed photonic neural network is CMOS-compatible, which makes it easy to construct scalable and large-scale multilayer neural networks. These findings reveal that there is great potential for highly integrated and scalable neuromorphic photonic chips. Full article

Recent advances in technologies such as blockchain, the Internet of Things (IoT), Cyber–Physical Systems (CPSs), and the Industrial Internet of Things (IIoT) have driven the digitalization and intelligent transformation of modern industries. However, embedded control devices within power system communication infrastructures have become increasingly susceptible to cyber threats due to escalating software complexity and extensive network exposure. We have seen that symmetric conventional patching techniques—both static and dynamic—often fail to satisfy the stringent requirements of real-time responsiveness and computational efficiency in resource-constrained environments of all kinds of power grids. To address this limitation, we have proposed a hardware-assisted runtime patching framework tailored for embedded systems in critical power system networks. Our method has integrated binary-level vulnerability modeling, execution-trace-driven fault localization, and lightweight patch synthesis, enabling dynamic, in-place code redirection without disrupting ongoing operations. By constructing a system-level instruction flow model, the framework has leveraged on-chip debug registers to deploy patches at runtime, ensuring minimal operational impact. Experimental evaluations within a simulated substation communication architecture have revealed that the proposed approach has reduced patch latency by 92% over static techniques, which are symmetrical in a working way, while incurring less than 3% CPU overhead. This work has offered a scalable and real-time model-driven defense strategy that has enhanced the cyber–physical resilience of embedded systems in modern power systems, contributing new insights into the intersection of runtime security and grid infrastructure reliability. Full article

The development of artificial intelligence has resulted in significant challenges to conventional von Neumann architectures, including the separation of storage and computation, and power consumption bottlenecks. The new generation of brain-like devices is accelerating its evolution in the direction of high-density integration and integrated sensing, storage, and computing. The structural and information transmission similarity between memristors and biological synapses signifies their unique potential in sensing and memory. Therefore, memristors have become potential candidates for neural devices. In this paper, we have designed an optoelectronic memristor based on a ZnO/Cu₂O structure to achieve synaptic behavior through the modulation of electrical signals, demonstrating the recognition of a dataset by a neural network. Furthermore, the optical synaptic functions, such as short-term/long-term potentiation and learn-forget-relearn behavior, and advanced synaptic behavior of optoelectronic modulation, are successfully simulated. The mechanism of light-induced conductance enhancement is explained by the barrier change at the interface. This work explores a new pathway for constructing next-generation optoelectronic synaptic devices, which lays the foundation for future brain-like visual chips and intelligent perceptual devices. Full article

Weightlifting is a common fitness activity and can be practiced individually without supervision. However, performing regular weightlifting exercises without any form of feedback can lead to serious injuries. To counter this, this work proposes a different approach to automatic weightlifting supervision off-the-person. The proposed embedded system is coupled to the weights and evaluates if they follow the correct trajectory in real time. The system is based on a low-power embedded System-on-a-Chip to perform the classification of the correctness of physical exercises using a Convolutional Neural Network with data from the embedded IMU. It is a low-cost solution and can be adapted to the characteristics of specific exercises to fine-tune the performance of the athlete. Experimental results show real-time monitoring capability with an average accuracy close to 95%. To favor its use, the prototypes have been enclosed on a custom 3D case and validated in an operational environment. All research outputs, developments, and engineering models are publicly available. Full article

High-precision indoor positioning technology is increasingly prominent in its application value in emerging fields such as the Industrial Internet of Things, smart cities, and autonomous driving. 5G networks can transmit large-bandwidth signals and have the capability to transmit and receive signals with multiple antennas, enabling the simultaneous acquisition of angle and distance observation information, providing a solution for high-precision positioning. Differences in the types and quantities of observation information in complex environments lead to positioning scenarios having a multimodal nature; how to propose an effective observation model that covers multimodal scenarios for high-precision robust positioning is an urgent problem to be solved. This paper proposes a three-stage time–frequency synchronization method based on group peak time sequence tracing. Timing coarse synchronization is performed through a group peak accumulation timing coarse synchronization algorithm for multi-window joint estimation, frequency offset estimation is based on cyclic prefixes, and finally, fine timing synchronization based on the primary synchronization signal (PSS) sliding cross-correlation is used to synchronize 5G signals to chip-level accuracy. Then, a tracking loop is used to track the Positioning Reference Signal (PRS) to within-chip accuracy, obtaining accurate distance information. After obtaining distance and angle information, a high-precision positioning method for multimodal scenarios based on 5G heterogeneous measurement combination is proposed. Using high-precision angle observation values as intermediate variables, this algorithm can still solve a closed-form positioning solution under sparse observation conditions, enabling the positioning system to achieve good positioning performance even with limited redundant observation information. Full article

Touch is a crucial sense for advanced organisms, particularly humans, as it provides essential information about the shape, size, and texture of contacting objects. In robotics and automation, the integration of tactile sensors has become increasingly relevant, enabling devices to properly interact with their environment. This study aimed to develop a biomimetic, skin-inspired tactile sensor device capable of sensing applied force, characterizing it in three dimensions, and determining the point of application. The device was designed as a 4 × 4 matrix of tunneling magnetoresistive sensors, which provide a higher sensitivity in comparison to the ones based on the Hall effect, the current standard in tactile sensors. These detect magnetic field changes along a single axis, wire-bonded to a PCB and encapsulated in epoxy. This sensing array detects the magnetic field from an overlayed magnetorheological elastomer composed of Ecoflex and 5 µm neodymium–iron–boron ferromagnetic particles. Structural integrity tests showed that the device could withstand forces above 100 N, with an epoxy coverage of 0.12 mL per sensor chip. A 3D movement stage equipped with an indenting tip and force sensor was used to collect device data, which was then used to train neural network models to predict the contact location and 3D magnitude of the applied force. The magnitude-sensing model was trained on 31,260 data points, being able to accurately characterize force with a mean absolute error ranging between 0.07 and 0.17 N. The spatial sensitivity model was trained on 171,008 points and achieved a mean absolute error of 0.26 mm when predicting the location of applied force within a sensitive area of 25.5 mm × 25.5 mm using sensors spaced 4.5 mm apart. For points outside the testing range, the mean absolute error was 0.63 mm. Full article

This paper presents a 2-stage GaN Doherty power amplifier module (DPAM) on a compact $7\times 7$ quad flat no-lead (QFN) package, designed for the needs of 5G massive MIMO base transceiver systems. The interstage and input matching networks employ high-quality factor integrated passive devices (IPDs) to achieve a small form factor. This multi-chip module consists of three GaN-HEMT bare dies used for the driver stage, carrier amplifier, and peaking amplifier. Additionally, two IPD dies are included for the interstage and input matching networks. The external load network is developed using a printed circuit board (PCB). Utilizing a 5G NR signal of 100 MHz bandwidth and a 9.3 dB PAPR within the 3.4–3.8 GHz band, the developed DPAM demonstrated a power gain exceeding 26.8 dB and a power-added efficiency (PAE) greater than 37.8% at a 39 dBm average output power. Full article