Search Results (27)

Bipolar junction transistors (BJTs) are susceptible to total ionizing dose (TID) effects in radiation environments, leading to current gain degradation. Addressing the initial-value sensitivity issue in solving the two-dimensional implicit coupled equations within the BJT transceiver current analytical model based on symmetric double-gate MOSFET surface potential theory, this study proposes a machine learning-based BJT surface potential prediction method. This method integrates a classification model, a sample generation model, and a regression model to achieve accurate prediction of BJT surface potential under TID damage. For the sample generation model, a residual Transformer variational autoencoder is designed to enhance the efficiency of generating effective samples. For the regression model, a dynamic exponential weighted mean squared error function is adopted as the loss function for XGBoost to improve the model’s generalization capability. Simulation results demonstrate that at cumulative total doses of 50 and 100 krad(Si), the average relative error between predicted over-base currents and irradiation test results is as low as 0.1847 and 0.2619, respectively, confirming the accuracy of the proposed prediction method. Full article

Electromagnetic interference (EMI) rectification of grid-tied inverters is crucial for their practical application, and the variable frequency modulation (VFM) technique is a low-cost and simple way for EMI reduction. However, changes in loss and harmonic behaviors make it hard for parameter determination of VFM. In this paper, the parameters required for switching frequency (SF) function are determined for loss optimization of MOSFETs and inductors, while total harmonic distortion (THD) and temperature rise in MOSFETs and inductor core are constrained to guarantee the feasibility of the calculated parameters. Current transient is derived through multidimensional Fourier decomposition (MFD) and characteristics of Bessel function for loss estimation of MOSFET and inductor. Modified Steinmetz equation (MSE) is applied for core loss estimation and AC resistance is considered for copper loss estimation. With the constraints of THD and temperature, the loss optimization problem is solved by the augmented Lagrangian (AL) method. With the assistance of the proposed method, total loss optimization can be realized in feasible regions while the temperature rise in essential components can be restricted to the preset values. Full article

We present an analytic compact model for p-type cylindrical gate-all-around (GAA) MOSFETs in the quasi-ballistic/ballistic regime, incorporating drain-induced barrier lowering (DIBL). To describe the potential profile, an undetermined parameter is used to represent the channel potential, which is derived from the Laplace equation in the subthreshold region and from Gauss’s law combined with quantum statistics in the inversion region. A smoothing function is applied to this parameter to ensure a continuous source—drain current across all operating regions. The current model is based on the Landauer approach and captures both quasi-ballistic/ballistic transport and quantum-confinement effects. It is validated against non-equilibrium Green’s function (NEGF) simulation results and implemented in Verilog-A for SPICE circuit-level simulation of a CMOS inverter, demonstrating its applicability for nanoscale design. Full article

This study presents the development of a buck–boost converter for application in unmanned guided vehicles (UGVs). The converter was designed with its input connected to a lithium iron phosphate battery pack and its output connected to an inverter. This configuration enabled the inverter, which powered the drive motor, to receive a stable DC voltage, thereby mitigating the effects of battery voltage fluctuations and enhancing the overall system stability. A pulse-width modulation (PWM) controller was employed to regulate the developed buck–boost converter. During the transition from buck mode to buck–boost mode, both power MOSFETs were simultaneously turned on; however, the datasheet of the PWM controller did not provide operational details or characteristic curve analysis for this mode. Therefore, this study derived the relationship between voltage gain and duty cycle ratio for the transition mode. To analyze the input voltage versus duty cycle characteristics, the linear equation was employed. This analytical model was adjusted to meet different converter specifications developed for experimental validation. Furthermore, the external-connect test capacitor method was used to extract the equivalent parasitic inductance and capacitance present in the practical circuit of the buck–boost converter. Based on these parameters, a snubber circuit was designed and connected across the drain–source terminals of the power MOSFETs to suppress voltage spikes occurring at the junctions. Finally, the developed buck–boost converter prototype was installed on an unmanned guided vehicle to convert the power from the lithium battery pack into the input power required by two inverters. A computer host was used to control the motor speed. By measuring the output voltage and current of the buck–boost converter, its electrical functionality and performance specifications were verified. The dimensions of the developed UGV chassis prototype were 40 cm in length, 45 cm in width, and 18.3 cm in height. Full article

This paper proposes a cross-scale simulation approach for evaluating the steady-state electrothermal performance of power MOSFETs at the device–package–heatsink–board (DPHB) level. A co-simulation framework is designed by employing the iterative process of power loss and chip temperature to bridge the device and package–heatsink–board (PHB) level simulators. As a result, the cross-scale electrothermal coupling effect within multilevel settings is considered. Correspondingly, variation values in chip temperature and temperature-dependent drain current can be obtained at various voltage biases, level settings, and DPHB structural parameters, incorporating cross-level physical insights. The simulation results are compared with existing methods, and their features and limitations are discussed. Additionally, this paper also derives an empirical equation from the co-simulations to characterize the relationship between the drain current and the chip temperature under different operations exactly. A commercial MOSFET with TO-220F packaging is implemented in experiments to extract the chip temperature and drain current in electrothermal equilibrium. The method comparisons and fair agreement among simulations, equations, and measurements presents the proposed approach as generalized and powerful for describing variations in chip temperature and drain current considering from micrometer devices to millimeter packages–heatsinks–PCB boards, thus providing effective support for DPHB-level co-design. Full article

The reliability of power electronic switching components is of great concern for many researchers. For their usage in many mission profiles, it is crucial for them to perform for the duration of their intended lifetime; however, they can fail because of thermal stress. Thus, it is essential to analyze their thermal performance. Non-linear switching action, bifurcation and chaotic events may occur in DC-DC power converters. Consequently, they show different behaviors when their parameters change. However, this is an opportunity to study these bifurcation phenomena and the existence of chaos, e.g., in boost converters, on their performance as the effects of load variations (mission profiles) on the system’s behavior. These variations generate many non-linear phenomena such as periodic behavior, repeated period-doubling bifurcations and chaos in the MOSFET drain-source current. Thus, we propose, for the first time, an analysis of the influence of chaos on the junction temperature. First of all, this paper provides a step-by-step procedure to establish an electrothermal model of a C2M0080120D MOSFET with integrated power loss. Then, the junction temperature is estimated by computing the power losses and a thermal impedance model of the switch. Additionally, this model is used to investigate the bifurcation and chaotic behavior of the MOSFET junction temperature. The paper contributes by providing a mathematical model to calculate several coefficients based on experimental data and thermal oscillations. Estimation of the number of cycles to failure is given by the Coffin–Manson equation, while temperature cycles are counted using the rainflow counting algorithm. Further, the accumulated damage results are calculated using the Miner’s model. Finally, a comparison is made between the damage accumulated during different mission profiles: significant degradation of the MOSFET’s lifetime is pointed out for chaotic currents compared to periodic ones. Full article

This article presents a quasi-resonant converter (QRC) with multiple sources. A QRC has many benefits, such as high gain, constant current, and nominal voltage stress on MOSFET, with an up to 49% duty cycle with fewer switches. These features of the converter make it suitable for electrical vehicle (EV) off-board charging, which requires significant voltage gain. As the switch operates under soft switching condition, the converter has reduced power loss, improved efficiency, and increased reliability. To reduce grid dependency, the suggested QRC is housed with a grid and PV at the input ports. The proposed converter is modeled using mathematical equations and examined using the MATLAB platform under different operating conditions. In this work, analysis of the steady state, along with components design, estimation of the voltage and current stresses, are addressed. Further, the reliability of the QRC based on the probability of components failure is carried out using the Markov model. The hardware results are observed to validate the design, operation, efficiency, and suitability of the proposed QRC for EV off-board charging applications. A 400-watt test rig is designed to assess the performance of QRC. Full article

This research introduces a model-based approach for the analysis and control of an onboard charger (OBC) system for contemporary electrified vehicles. The primary objective is to integrate the modeling of SiC/GaN MOSFETs electrothermal behaviors into a unified simulation framework. The motivation behind this project stems from the fact that existing literature often relies on finite element method (FEM) software to examine thermal dynamics, necessitating the development of complex models through partial derivative equations. Such intricate models are computationally demanding, making it difficult to integrate them with circuit equations in the same virtual environment. As a result, lengthy wait periods and a lack of communication between the electrothermal models limit the thorough study that can be conducted during the design stage. The selected case study for examination is a modular 1$\varphi$ (single phase) onboard computer (OBC). This system comprises a dual active bridge (DAB) type DC/DC converter, which is positioned after a totem pole power factor correction (PFC) AC/DC converter. Specifically, the focus is directed toward a 7 kW onboard computer (OBC) utilizing high-voltage SiC/GaN MOSFETs to ensure optimal efficiency and performance. A systematic approach is presented for the assessment and selection of electronic components, employing circuit models for the totem pole power factor correction (PFC) and dual active bridge (DAB) converter. These models are employed in simulations closely mimicking real-world scenarios. Furthermore, rigorous testing of the generated models is conducted across a spectrum of real-world operating conditions to validate the stability of the implemented control algorithms. The validation process is bolstered by a comprehensive exploration of parametric variations relative to the nominal case. Notably, each simulation adheres to the recommended operational limits of the selected components and devices. Detailed data sheets encompassing electrothermal properties are provided for contextual reference. Full article

A non-isolated high gain DC–DC converter with magnetic coupling and a VM circuit is proposed in this study. By the use of the appropriate coupled inductor turn ratio, the output voltage of the recommended topology can be raised. The VM circuit is used to boost the voltage gain even further as well as to clamp the voltage spike across the switch, which results in a lower voltage on the switch. As a result, a MOSFET switch with a lower ON-state resistance (R_DS-ON) is used which, in turn, causes the conduction losses to be reduced and the entire system efficiency to be raised. Another advantage of the proposed structure is the ZCS of the diodes, which reduces the voltage drop losses caused by the regenerative diodes. The function modes analysis and the theoretical equations are accomplished. A comparison survey with other prior works is being developed to investigate the competency of the proposed converter. Based on this, the higher voltage gain and efficiency as well as the lower voltage stress on the semiconductors can be achieved by the proposed converter compared to the other converters. The effectiveness of the proposed converter is confirmed by the experimental results at a laboratory-scale operating under 150 V output voltage with a 96% efficiency at the 150 W full load and a 25 kHz switching frequency. Full article

In this paper, a new single-cell hybrid switched inductor DC-DC converter is proposed to demonstrate the verification of ultra-high voltage gain in renewable energy applications (REA). The modification involves adding a single cell of an inductor with a diode and double capacitor to increase voltage transfer gain. Additionally, this modification helps prevent the input current from becoming zero, pulsating at very low duty cycles. The single cell of the hybrid inductor is interleaved with the main switch to reduce current stress when the capacitor of the single-cell inductor charge becomes zero. Moreover, the addition of a modified hybrid switch inductor with a capacitor, operating in dual boosting mode with a single switch, allows the converter to achieve ultra-high voltage gain. The proposed converter offers several advantages, including ultra-high voltage gain, high efficiency, low voltage stress on power MOSFETs, diodes, inductors, and capacitors, as well as low switching and conduction losses. Furthermore, the proposed converter utilizes transformerless and non-coupled inductors. Mathematical equations have been derived for the discontinuous conduction mode (DCM) and continuous conduction mode (CCM) and implemented using Matlab Simulink software to validate the results. In addition, a dual PI controller is designed for the proposed converter to verify the fixed output voltage. Experimental results have also been obtained for a 200 W prototype, with the input voltage varying between 20 V and 40 V, and an output voltage of 200 V at an efficiency of 96.5%. Full article

This paper compares the cost and efficiency of two inverter topologies for a 5-kW grid-connected solar inverter application: the Conventional H-Bridge Inverter (CHB) and the Cascaded H-Bridge Multilevel Inverter (CHBMLI). Emphasis is put on power switches and passive elements with a detailed study of the losses. Both designs respect the same constraints (cost, efficiency, and junction temperature of the transistors) to ensure a fair comparison between both topologies. The work highlights the important parameters when choosing the components (MOSFETs, capacitors, and magnetic cores for the inductors). The DC-link voltage ripple and the output AC current ripple are the key parameters for the design of the passive elements (capacitors and inductors). On top of that, the transistors MOSFETs are chosen, in both topologies, to limit the conduction losses (by selecting the $R_{d{s}_{on}}$) and the switching losses (by selecting the $Q_{rr}$ and $dv/dt$). Real components are picked in order to make the comparison as complete as possible. Numerical simulations are performed using the MATLAB platform. All equations and parameters are provided. A CHBMLI prototype was built with eight independent H-Bridges to validate the proposed design with thermal and efficiency measurements. Full article

The continued scaling-down of nanoscale semiconductor devices has made it very challenging to obtain analytic surface potential solutions from complex equations in physics, which is the fundamental purpose of the MOSFET compact model. In this work, we proposed a general framework to automatically derive analytical solutions for surface potential in MOSFET, by leveraging the universal approximation power of deep neural networks. Our framework incorporated a physical-relation-neural-network (PRNN) to learn side-by-side from a general-purpose numerical simulator in handling complex equations of mathematical physics, and then instilled the “knowledge’’ from the simulation data into the neural network, so as to generate an accurate closed-form mapping between device parameters and surface potential. Inherently, the surface potential was able to reflect the numerical solution of a two-dimensional (2D) Poisson equation, surpassing the limits of traditional 1D Poisson equation solutions, thus better illustrating the physical characteristics of scaling devices. We obtained promising results in inferring the analytic surface potential of MOSFET, and in applying the derived potential function to the building of 130 nm MOSFET compact models and circuit simulation. Such an efficient framework with accurate prediction of device performances demonstrates its potential in device optimization and circuit design. Full article

With the rapid miniaturization of integrated chips in recent decades, aggressive geometric scaling of transistor dimensions to nanometric scales has become imperative. Recent works have reported the usefulness of 2D transition metal dichalcogenides (TMDs) like MoS₂ in MOSFET fabrication due to their enhanced active surface area, thin body, and non-zero bandgap. However, a systematic study on the effects of geometric scaling down to sub-10-nm nodes on the performance of MoS₂ MOSFETs is lacking. Here, the authors present an extensive study on the performance of MoS₂ FETs when geometrically scaled down to the sub-10 nm range. Transport properties are modelled using drift-diffusion equations in the classical regime and self-consistent Schrödinger-Poisson solution using NEGF formulation in the quantum regime. By employing the device modeling tool COMSOL for the classical regime, drain current vs. gate voltage (I_D vs. V_GS) plots were simulated. On the other hand, NEGF formulation for quantum regions is performed using MATLAB, and transfer characteristics are obtained. The effects of scaling device dimensions, such as channel length and contact length, are evaluated based on transfer characteristics by computing performance metrics like drain-induced barrier lowering (DIBL), on-off currents, subthreshold swing, and threshold voltage. Full article

In this work, three-dimensional modeling of the surface potential along the cylindrical surrounding double-gate (CSDG) MOSFET is proposed. The derived surface potential is used to predict the values of electron mobility along the length of the device, thereby deriving the drain current equation at the end of the device. The expressions are used for modeling the symmetric doped and undoped channel CSDG MOSFET device. This model uses Pao-Sah’s double integral to derive the current equation for the concentric cylindrical structure of the CSDG MOSFET. The three-dimensional surface potential estimation is performed analytically for doped and undoped device parameters. The maximum oxidant concentration of the oxide layer is observed to be 4.37 × 10¹⁶ cm⁻³ of the thickness of 0.82 nm for (100) and 3.90 × 10¹⁶ cm⁻³ of the thickness of 0.96 nm for (111) for dry oxidation, and 2.56 × 10¹⁹ cm⁻³ of thickness 0.33 nm for (100) and 2.11 × 10¹⁹ cm⁻³ of thickness 0.49 nm for (111) for wet oxidation environment conditions. Being an extensive analytical approach, the drain current serves the purpose of electron concentration explicitly inside the concentric cylindrical structures. The behavior of the device is analyzed for various threshold conditions of the gate voltage and other parameters. Full article

High conversion gain is often required for the grid integration of renewable energy resources such as PV, fuel cells, and wind. It is desired that the stress across switches is lower when higher voltage gain is attained. Similarly, it is also preferred that the converter can achieve high voltage gain without operating at higher duty cycle values. This article presents a novel high-gain CUK converter (HGCC) that uses voltage-multiplier units. The HGCC is a combination of a modified CUK converter and voltage-multiplier units (VMUs). The converter utilizes a boost converter as an input to the modified CUK converter, resulting in an increase in the gain value. The voltage gain of HGCC is increased further by placing VMUs. Based on its overall design, the HGCC inherits various advantages of the CUK converter, such as continuous input and output current, resulting in low input and output current ripples. A mathematical model is developed for the HGCC, which helps calculate its voltage gain at different stages. The model is developed considering ideal elements without conduction and switching losses. Generalized equations for output voltage and gain are derived for $n$ level converter. A simulation study was performed in MATLAB/Simulink that further highlights the advantages of the HGCC. Voltage stresses across different components and the switching of MOSFET and diodes are studied in simulations. An experimental setup is established for hardware prototyping of the converter and validation with the simulation and Mathematical models. Full article