A New Single-Cell Hybrid Inductor-Capacitor DC-DC Converter for Ultra-High Voltage Gain in Renewable Energy Applications

Abstract

In this paper, a new single-cell hybrid switched inductor DC-DC converter is proposed to demonstrate the verification of ultra-high voltage gain in renewable energy applications (REA). The modification involves adding a single cell of an inductor with a diode and double capacitor to increase voltage transfer gain. Additionally, this modification helps prevent the input current from becoming zero, pulsating at very low duty cycles. The single cell of the hybrid inductor is interleaved with the main switch to reduce current stress when the capacitor of the single-cell inductor charge becomes zero. Moreover, the addition of a modified hybrid switch inductor with a capacitor, operating in dual boosting mode with a single switch, allows the converter to achieve ultra-high voltage gain. The proposed converter offers several advantages, including ultra-high voltage gain, high efficiency, low voltage stress on power MOSFETs, diodes, inductors, and capacitors, as well as low switching and conduction losses. Furthermore, the proposed converter utilizes transformerless and non-coupled inductors. Mathematical equations have been derived for the discontinuous conduction mode (DCM) and continuous conduction mode (CCM) and implemented using Matlab Simulink software to validate the results. In addition, a dual PI controller is designed for the proposed converter to verify the fixed output voltage. Experimental results have also been obtained for a 200 W prototype, with the input voltage varying between 20 V and 40 V, and an output voltage of 200 V at an efficiency of 96.5%.

1. Introduction

The world is increasingly interested in utilizing various types of renewable energy sources to generate electrical power, driven by concerns regarding energy security and the environmental impact resulting from carbon dioxide emissions [1,2]. Solar and wind energy, in particular, have gained widespread adoption worldwide [3,4]. For instance, photovoltaic solar panels produce variable low-voltage outputs ranging from 12–40 V, which are unsuitable for applications requiring high DC supply voltage or household appliances [5,6]. Therefore, DC-DC converters are employed to step up very low input voltage to high output DC voltage for various applications such as streetlights, motor drives, microgrid systems, uninterruptible power supplies, fuel cells, and medical equipment [2,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35]. Different converter topologies, including buck-boost, boost, and Ćuk DC-DC converters, have been introduced to achieve high voltage gain. The choice of converter depends on the specific application requirements. However, these converters encounter challenges when targeting ultra-high voltage gain. Key issues include a lower count of inductors and capacitors, reduced efficiency at high voltage gain with extremely high duty ratios, high voltage stress on power switches and diodes (equivalent to the output voltage), and increased current stress on power devices as the load current rises. In this context, current stress refers to the magnitude of current flowing through the switch during the on state and is influenced by the paths traversed by the current through the MOSFET. Moreover, these converters suffer from elevated switching and conduction losses when the duty cycle exceeds 0.9, as well as low power density [20]. Although boost converter topologies can achieve voltage step-up with high voltage gains of up to 10, their efficiency diminishes at high duty cycles [10,36]. Several researchers have proposed new technologies for DC-DC converters to attain high voltage gain in renewable energy systems (RESs).

A modified DC-DC converter, interleaved with a boost converter based on soft switching between the main and auxiliary power MOSFETs, has been proposed to achieve high voltage gain and solve the inrush current problem [1]. Another modification to the boost converter using a hybrid inductor capacitor has been proposed in [8], and another with a switch capacitor (SC), switch inductor (SL), and voltage multiplier (VM) in [31]. A cascaded conventional SEPIC with a boost converter has been proposed in [24,26], and a modified SEPIC based on an interleaved buck-boost converter in [11]. A modified converter with multi-input has been proposed in [9,25]. These converters, as mentioned, are modified to achieve high voltage gain with high power density. However, they have low voltage gain and a high number of inductors and capacitors. Additionally, they require a high number of power diodes and power MOSFETs to step up the low input to a high output voltage. Furthermore, the power MOSFETs and diodes in these converters experience high voltage stress. Complex control was also required in [8] to achieve high voltage gain. Moreover, these converters achieve high voltage gain with an extremely high duty cycle, resulting in high switching and conduction losses, as well as low performance and efficiency. Other topologies have been proposed, such as a modified DC-DC converter with coupled inductors and a voltage multiplier network (VMN) [3], and a conventional SEPIC with a coupled inductor and VM [23]. These converters have demonstrated high voltage gain, but they feature a high number of passive and active elements, as well as diodes. The large number of components leads to a high parasitic resistance of inductors and capacitors, resulting in reduced efficiency. Additionally, these converters operate at a low switching frequency, which necessitates the use of large values of inductors and capacitors. Moreover, the internal resistance of the power MOSFET (Ron) is high, further diminishing the voltage gain of the system. Furthermore, a major issue with coupled inductor converters is the occurrence of high spike voltages in the off state of the power switch due to the inductance with parasitic capacitance of the power MOSFET switch [36]. To address this problem, a clamped circuit can be added to the power switch to prevent the occurrence of high spike voltages due to the coupled inductor [2,37]. However, adding more components to the circuit increases costs and reduces efficiency due to parasitism. In addition, the system will be heavy and large. Another problem is the pulsating input current at a low duty cycle, which makes these converters unsuitable for RES applications.

Other researchers have developed DC-DC converters to achieve high voltage gain using non-isolated coupled inductors. In [12], a double power switch converter with double switch inductor (SL) was utilized. Additionally, in [13], a modified converter incorporating a hybrid capacitor and inductor, and in [14], a DC-DC converter employing the voltage lift technique, are proposed. Furthermore, in [15,16], a DC-DC converter based on SC with zero voltage switching, and in [10,17], a modified buck-boost converter featuring a single switch and pulsating input current, are described. However, these converters require an extremely high duty ratio to achieve a high voltage gain ratio. This implies high switching and conduction losses, low efficiency, low power density, and high voltage stress on the power switches, diodes, inductors, and capacitors. Additionally, these converters exhibit a high inductor count with low switching frequencies, which results in high parasitic resistance, diminished performance, and efficiency. A modified boost converter with dual power switch was proposed in [18], a modified boost converter with a single switch, multiplier capacitor, and SL in [19,22], and a multi-input converter with multiple capacitors as hybrid energy storage in [21], with the goal of attaining high voltage gain for RESs. A buck-boost converter with SC SL was developed in [27], a pair of cascaded conventional boost converters with dual switches in [28] and with a single switch in [30], and a modified buck interleaved with SEPIC based on (SC) (SL) with two input sources in [29]. These converters achieve high voltage gain; however, they have a large number of power switches and diodes, which has a high impact on system efficiency and performance. In addition, the voltage and current stress on the power switch is high. Furthermore, the gate control circuit is large and complex to implement.

In this paper, a new single-cell hybrid switched inductor-capacitor DC-DC converter is proposed to demonstrate the verification of ultra-high voltage gain in renewable energy applications (REA). The proposed modification involves incorporating a single cell of a hybrid inductor, along with a diode and double capacitors, interleaved with the main switch. This integration enables the proposed converter to attain a high voltage gain while ensuring that the input current does not experience zero pulsations at very low duty cycles. Additionally, the current stress on the main switch will reduce as the duty ratio increases, as shown in Figure 11f when the single-cell capacitor C₁ charge becomes zero. Furthermore, the converter employs a modified hybrid switch inductor in dual boosting mode, working with a single switch. This arrangement allows for the realization of an ultra-high voltage gain. Moreover, one of the passive components, L₂, will be open circuit, and D₁ is working at zero current switching, which means a reduction in the total power loss of the converter.

2. Structure and Operation of the Proposed DC–DC Converter

The DC-DC converter is modified to achieve a high voltage gain by stepping up a low input voltage range of 20–40 V to an output voltage of 200 V. The proposed converter is based on a modified hybrid switched inductor-capacitor configuration to verify high voltage gain. Figure 1a shows the basic connection of a switched inductor, while Figure 1b illustrates the hybrid connection of a switched inductor and a capacitor. Consequently, the proposed converter is designed for Renewable Energy Sources (RES). In Figure 1c, the connection of the proposed converter with PV Panels and Battery is shown for Energy Saving Mode Applications. The structure of the proposed converter includes four inductors, four capacitors, three diodes, and two power switches, as depicted in Figure 1d. The main advantages of the proposed converter are that it utilizes non-coupled inductors and is transformerless. It employs a high switching frequency to reduce the sizes of inductors and capacitors, thereby increasing its efficiency. The proposed converter has a simple structure with a straightforward control circuit. The new single cell of an inductor and capacitor, which is interleaved with the main switch, helps avoid pulsating input current at low duty cycles and minimizes voltage stress on the power switches, diodes, and inductors. Additionally, the current stress on the main switch is reduced when the duty cycle increases. Furthermore, the proposed converter achieves an ultra-high voltage gain compared to previous DC-DC converters. In terms of the power switch PWM generator, it uses a simple design where both MOSFETs turn on and off simultaneously. The proposed converter can operate in DCM under two cases. Firstly, it can function in DCM Case 1 (DCMC1) at a low duty cycle and maximum input voltage, with a duty ratio below 50%. Secondly, the proposed converter can operate in DCM Case 2 (DCMC2) when the input voltage decreases during the day at a high load current, with a duty ratio above 50%. Additionally, the converter can also operate in CCM when the load current increases and the duty ratio exceeds 70%. These scenarios are illustrated in Figure 4a,b, which demonstrates the dynamic performance of the proposed converter.

2.1. Proposed Converter Operation DCMC1

The proposed converter can operate in DCMC1 in four states of operation during one cycle when the input voltage is at its maximum, with a low duty cycle, and at light load. The waveform of this mode of operation is shown in Figure 2a. The four states of this operational mode are listed below:

State 1: [0–t₀]: In this mode, the two power MOSFETs (Sw₁ and Sw₂) are in the on state, and a PWM generator provides a high source-to-gate voltage to turn both MOSFETs on and keep diodes D₂ and D₃ off. During this mode, L₁ charges with energy from the input source, which is connected in series with it. L₂ begins to charge from C₁, and C₁ discharges the energy stored in L₂ through Sw₁. D₁ is on during this mode, and C₂ stores a significant amount of energy, which is used to charge L₃ through Sw₂. At the same time, L₄ starts charging from C₃. C₄ supplies power to the load and forms the current path for this mode, as shown in Figure 2b.

The voltage equations of this mode for inductors, capacitors, diodes, and MOSFETs are as follows:

$$\left.\begin{array}{l}V{L}_1=Vs\\ V{L}_2=V{c}_1\\ V{L}_3=V{c}_2\\ V{L}_4=V{c}_2-V{c}_3\\ V{c}_4=Vo\end{array}\right\}$$

(1)

The current equations of this mode for inductors, capacitors, diodes, and MOSFETs are as follows:

$$i{L}_1+i{L}_2=IS{W}_1$$

(2)

$$IS{W}_2=I{c}_2=i{L}_3+i{L}_4$$

(3)

$$I{D}_1=i{L}_2=I{C}_1$$

(4)

$$I{C}_4=Io$$

(5)

$$\left.\begin{array}{l}i{L}_1=\frac{Vs}{L_1}\\ i{L}_2=\frac{V{c}_1}{L_2}\\ i{L}_3=\frac{V{c}_2}{L_3}\\ Io=\frac{Vo}{RL}\end{array}\right\}$$

(6)

where VL represents the voltage across the inductor, Vc denotes the voltage across the capacitor, Isw represents the current through the power MOSFET switch during the on state, Vo signifies the output voltage, iL represents the current through the inductor, Io represents the output current, RL represents the resistive load, ID is the current through the power diode, and Ic denotes the current through the capacitor.

State 2: [t₀–t₁]: In this mode, the two power MOSFETs are in the off state, and both diodes D₂ and D₃ in the on state. L₁ discharges energy to C₁ and charges C₂. L₂ starts discharging its energy to C₂ through D₁ and remains in the on state. C₂ stores a large amount of energy from L₁ and L₂. L₃ and L₄ start discharging their energy to C₄, which supplies high power to the load and forms the current path of this mode, as shown in Figure 3c.

The voltage equations of this mode for inductors, capacitors, diodes, and MOSFETs are as follows:

$$\left.\begin{array}{l}V{L}_1=Vs-V{c}_1-V{c}_2\\ V{L}_2=-V{c}_2\\ V{L}_3=V{c}_3+V{L}_4\\ V{L}_4=-V{c}_4\\ V{c}_4=V_o\end{array}\right\}$$

(7)

The current equations of this mode for inductors, capacitors, diodes, and MOSFETs are as follows:

$$\left.\begin{array}{l}i{L}_1=\frac{VS}{L_1}-\frac{Vc1}{L_1}-\frac{Vc2}{L_1}\\ i{L}_2=\frac{-V{c}_2}{L_2}\\ i{L}_3=\frac{V{c}_3 + V{L}_4}{L_3}\\ Io=\frac{Vo}{RL}\end{array}\right\}$$

(8)

$$i{L}_1+i{L}_2=I{D}_2$$

(9)

$$i{L}_3+i{L}_4=I{D}_3$$

(10)

$$I{D}_1=i{L}_2$$

(11)

$$I{c}_4=Io=i{L}_3+i{L}_4$$

(12)

$$i{L}_1=I{c}_1=Ii$$

(13)

where Ii is the input current, which is equal to iL₁.

State 3: [t₁–t₂]: In this mode, the two power MOSFETs are still in the off state, and both diodes D₂ and D₃ are still in the on state. L₁ continues discharging energy to C₁ and charges C₂. L₂ reaches zero charge and iL₂ and ID₁ are zero. C₂ continues receiving energy from only L₁, and D₁ is now in the off state in this mode. L₃ and L₄ continue discharging their energy to C₄, which supplies high power to the load and forms the current path of this mode, as shown in Figure 3d.

The current equations of this mode are as follows:

$$i{L}_1=I{D}_2$$

(14)

$$I{D}_1=i{L}_2=0$$

(15)

$$I{c}_2=i{L}_1$$

(16)

State 4: [t₂–t₃]: In this mode, the two power MOSFETs are still off, the PWM generator gives zero gate-to-source voltage to keep them in the off state, and only D₂ is still on. D₃ is now changed to the off state in this mode. L₁ continues discharging energy to charge C₁ and C₂. C₂ stores a large amount of energy for the next pulse to supply it to the load. L₂ has zero charge and iL₂ and ID₁ are zero, and D₁ is still off in this mode. L₃ and L₄ will have the same current values but in opposite directions: iL₃ = −iL₄. C₄ supplies high power to the load and forms the current path of this mode, as shown in Figure 3e.

Figure 4a,b illustrate the dynamic performance of the proposed converter when operating in DCM and CCM, respectively. It is evident from the figures that the proposed converter operates in DCM for duty cycles below 70%. However, for duty cycles above 70%, the converter can operate in CCM based on the boundary condition specified in Equation (33).

2.2. Proposed Converter Operation in DCMC2

The proposed converter can operate in DCMC2 when the input voltage is reduced to the minimum value during the day, while the load current is high. In this mode, the input current is still in CCM, and L₂ will be in resonant mode with C₁, while L₃ and L₄ will continue to operate in DCM. Therefore, this mode has four states of operation, as shown in Figure 2b: the proposed converter waveforms at DCMC2.

State 1: [0–t₀]: In this mode, the two MOSFETs Sw₁ and Sw₂ are in the on state, and both diodes D₂ and D₃ in their off states. L₁ starts charging energy from the input source, which is connected in series with it in CCM and never reaches zero. Inductor L₂ starts charging from C₁, and C₁ will discharge energy to L₂ through Sw₁ until (D − β₂), the charge across C₁ will be zero, and the current through Sw₁ will come only from IL₁ after this time, as shown in Figure 11f. D₁ is on in this mode, and C₂ stores a large amount of energy, which charges L₃ through Sw₂, and L₄ starts charging from C₃. C₄ supplies power to the load and forms the current path of this mode, as shown in Figure 3b. The current and voltage equations of this mode are the same as for State 1 of DCM Case 1. Only the current through Sw₁ is shown below:

$$\left.\begin{array}{l}Is{w}_1=(i{L}_1+I{c}_1) \mathrm{from} 0<\mathrm{t}<(\mathrm{D}-{\beta }_2)\\ Is{w}_1=i{L}_1 \mathrm{only} \mathrm{from} (\mathrm{D}-{\beta }_2)<\mathrm{t}<\mathrm{D}\end{array}\right\}$$

(17)

$$i{L}_2=\frac{V{c}_1}{L_2}(D-{\beta }_2)$$

(18)

State 2: [t₀–t₁]: In this mode, the two power Mosfets are still in the on state. The PWM generator continues to provide a high gate-to-source voltage to keep them in the on state, and both diodes D₂ and D₃ remain off. Meanwhile, L₁ continues to charge energy from the input source, while L₂ reaches zero charge due to the charge across C₁ being zero. The current through Sw₁ comes solely from IL₁, reducing the current stress through Sw1. D₁ operates with zero current switching during this mode, meaning that L₂ will be open circuit during the time period ((D − β₂) < t < D). L₃ and L₄ continue to charge from C₂ and C₃, respectively. C4 continues to supply power to the load, and the current path of this mode is shown in Figure 3f. The current equations remain the same as in the previous state 1.

State 3: [t₁–t₂]: in this mode, the two power MOSFETs are off, and both diodes D₂ and D₃ are now on. L₁ now starts discharging energy to C₁ and charges C₂. L₂ does not charge, and iL₂ and ID₁ are zero. L₂ is open circuit during this mode. C₂ receives a large amount of energy from L₁. L₃ and L₄ also start discharging their energy to C₄, which supplies high power to the load and forms the current path of this mode, as shown in Figure 3d.

State 4: [t₂–t₃]: In this mode, the two power MOSFETs are still off, and only D₂ is still on. D₃ is changed to the off state in this mode. L₁ continues discharging energy to charge C_2, and C₂ will have a large amount of energy for the next pulse to supply it to the load. L₂ remains open circuit in this mode. C₂ will continue receiving energy only from L₁. L₃ and L₄ will have the same current but in opposite directions: iL₃ = −iL₄. C₄ will supply high power to the load and forms the current path of this mode, as shown in Figure 3e.

When the proposed converter operates in DCMC2, the capacitor C₁ is discharged to zero at (D − β₂), reducing the current stress across Sw₁. In this case, the current through Sw₁ flows only from L₁. Additionally, the voltage stress across Sw₁ and the power diodes is significantly reduced. Furthermore, the conduction loss of Sw₁ is significantly reduced when the stress current is reduced. In this mode, L₂ will be in an open circuit state, and D₁ will have very low voltage stress. Additionally, as mentioned above, C₁ is discharged to zero. This implies that the components of the proposed converter are reduced during this mode, leading to improved performance and efficiency.

2.3. Proposed Converter Operation in CCM

This operation mode occurs when the load current increases to a duty cycle of 70%, as depicted in Figure 4. The input current still operates in CCM, and L₂ enters a resonant mode with C₁, while L₃ and L₄ continue to operate in CCM. Additionally, the voltage gain in this mode will be increased. Thus, this mode consists of three states of operation, as illustrated in Figure 2c, which shows the proposed converter waveforms in CCM.

State 1: [0–t₀]: in this mode, same as state 1 DCMC2.

State 2: [t₀–t₁]: in this mode, same as state 2 DCMC2.

State 3: [t₁–t₂]: In this mode, the two power MOSFETs are off, and both diodes D₂ and D₃ are now on. L₁ will start discharging energy to C₁ and charge C_2, and iL₂ and ID₁ are zero. C₂ receives a large amount of energy from L₁. L₃ and L₄ will also start discharging their energy to C₄, and L₃ and L₄ will have the same current in CCM but in opposite directions: iL₃ = −iL₄. C₄ will supply high power to the load and forms the current path of this mode, as shown in Figure 3d.

3. Voltage Gain Calculations of the Proposed Converter

In this section, the voltage gain of the proposed converter is calculated when it operates in DCM and CCM.

3.1. Voltage Gain of the Proposed Converter in DCMC1

In this section, we analyze the voltage gain of the proposed converter while it operates in DCMC1. This particular mode is encountered when the input voltage reaches its maximum value during light load applications, with a duty cycle below 50%. Hence, the equations that describe the voltage gain under the DCMC1 operation of the proposed converter are presented below:

$$\frac{1}{Ts}({\displaystyle {\int }_0^{DTs}(Vs+V{c}_1)dt}+{\displaystyle {\int }_D^{Ts}(Vs-V{c}_1-V{c}_2)}dt+{\displaystyle {\int }_{DTs}^{{\beta }_{1}Ts}(-V{c}_2})dt)=0$$

(19)

$$\frac{1}{Ts}({\displaystyle {\int }_0^{DTs}(V{c}_2)dt}+{\displaystyle {\int }_D^{D1Ts}(V{c}_2-V{c}_3)}dt=0$$

(20)

$$V{c}_2=\frac{Vs}{(1+{\beta }_1-D)}$$

(21)

$${\beta }_1=(\frac{Vs}{V{c}_2}+D-1)$$

(22)

$$D1=\frac{DV{c}_2}{Vo}$$

(23)

From Equations (1) and (7), applying volt-second balance to L₁ and L₂ results in Equation (19). Solving it results in Equation (21). Applying volt-second balance to L₃ and L₄ from Equations (1) and (7) yields Equation (20). After solving Equation (20), by applying the fact that the average voltage across C₃ is almost zero during the steady state, Equation (23) can be obtained (D1) is the discharging time of L₃ and L₄, and (β₁) represents the discharging time of L₂, which can be found from Equation (22) and is a function of $(D,Vs,V{c}_2)$.

$$\left.\begin{array}{l}<I2>=\frac{V{c}_1}{2L_2}DTs(D+\beta 1)\\ <I3>=\frac{V{c}_2}{2L_3}DTs(D+D1)+I\\ <I4>=\frac{V{c}_2}{2L_4}DTs(D+D1)-I\end{array}\right\}$$

(24)

$$\left.\begin{array}{l}i{L}_2{}_{peak}=\frac{VsDTs}{2(1-D)L_2}\\ i{L}_3{}_{peak}=\frac{VsDTs}{(1-D)L_3}\\ i{L}_4{}_{peak}=\frac{VsDTs}{(1-D)L_4}\end{array}\right\}$$

(25)

$$I3+I4=Io$$

(26)

$$Io=\frac{VsDTsD1}{2Le(1+{\beta }_1-D)}$$

(27)

To find the average current through L₂, L₃, and L₄, we can use Equation (24) to determine their respective averages. By adding the average currents I₃ and I₄ in Equation (24), we can calculate the average output current using Equation (27). The peak current of the inductors L₂, L₃, and L₄ can be found using Equation (25).

$$V{c}_2=\sqrt{\frac{2LeV{o}^2}{RL{D}^{2}Ts}}$$

(28)

$$Le=\frac{L_3{L}_4}{L_3+L_4}$$

(29)

$$Gv(DCMC1)=\frac{Vs{D}^{2}TsRL}{2LeVo{(1+{\beta }_1-D)}^2}$$

(30)

$$Gv(DCMC1)=\frac{D}{(1+{\beta }_1-D)\sqrt{K}}$$

(31)

$$k_{crit}=\frac{{(1-D)}^4}{{(1+{\beta }_1-D)}^2}$$

(32)

$$k_{crit}=\left\{\begin{array}{l}If \mathrm{Kcrit}> \mathrm{K} \mathrm{Proposed} \mathrm{Converter} \mathrm{work} \mathrm{in} \mathrm{DCM}\\ If \mathrm{Kcrit}< \mathrm{K} \mathrm{Proposed} \mathrm{Converter} \mathrm{work} \mathrm{in} \mathrm{CCM}\end{array}\right.$$

(33)

The voltage across capacitor C₂ can be obtained using Equation (28), which is a function of RL, Vo, D, and Le when the converter operates in DCMC1. Here, Le represents the inductor equivalent of L₃ and L₄, which can be found in Equation (29). Equation (30) provides the voltage gain of the proposed converter at DCMC1. Equation (31) expresses the voltage gain equation of the proposed converter in DCMC1 as a function of the load loss factor (K). The boundary condition of the proposed converter, specifically the critical load loss factor (K_crit), can be determined using Equations (32) and (33) by applying the values of (β₁) in Equation (32).

3.2. Voltage Gain of Proposed Converter in DCMC2

In this section, the voltage gain of the proposed converter can be adjusted by varying the input voltage and the load resistance. This mode occurs when the input voltage source reaches its minimum value at a duty cycle above 50%, while the proposed converter provides a high load current. Consequently, the voltage gain of the proposed converter in the DCMC2 equations is presented below.

$$\left.\begin{array}{l}\frac{1}{Ts}({\displaystyle {\int }_0^{DTs}(VS)dt}+{\displaystyle {\int }_0^{(D-{\beta }_2)Ts}(Vc1)}dt+{\displaystyle {\int }_{DTs}^{Ts}(Vs-Vc1-Vc2})dt))=0\\ \frac{1}{Ts}({\displaystyle {\int }_0^{DTs}(Vc2)dt}+{\displaystyle {\int }_D^{D1Ts}(Vc2-Vc3)}dt=0\end{array}\right\}$$

(34)

$$D(Vin)+(1-D)(Vin-Vc1-Vc2)+(D-{\beta }_2)(Vc1)=0$$

(35)

By applying voltage second balance on L₁, L₂, L₃ and L₄, we obtain Equation (34) as a result in Equation (35). From Equation (36), we determine the value of Vc₁, which is almost equal to the difference between the input voltage and the voltage across capacitor C₂. Vc₂ can be found in Equation (37). The values of (β₂) is adjusted and can be found in Equation (38), depending on the values of C₁ and L₂. After using Equation (34) and concluding with Equation (40), we obtain the voltage gain of the proposed converter when operating in DCMC2.

$$V{c}_1=Vs-V{c}_2$$

(36)

$$V{c}_2=\frac{Vs}{(1-D)}$$

(37)

$${\beta }_2=D-\frac{\sqrt{C_1{L}_2}}{Ts}$$

(38)

$$D1=\frac{DV{c}_2}{Vo}$$

(39)

$$Gv(DCMC2)=\frac{Vs{D}^{2}TsRL}{2LeVo{(1-D)}^2}$$

(40)

3.3. Voltage Gain of Proposed Converter in CCM

The voltage gain of the proposed converter is derived in CCM as shown in the equations below:

$$\frac{1}{Ts}({\displaystyle {\int }_0^{DTs}(V{c}_2)dt}+{\displaystyle {\int }_D^{Ts}(V{c}_2-V{c}_3)}dt=0$$

(41)

$$Vo=\frac{Vc2D}{(1-D)}$$

(42)

$$Gv=\frac{Vo}{Vs}=\frac{D}{{(1-D)}^2}$$

(43)

By using the same Equations (34) and (35), by applying volt-second balance to L₁ and L₂ and, to L₃ and L₄, we obtain Equation (41) at different times. The result can be found in (42) and (43). The voltage gain of the proposed converter in CCM is given by Equation (43).

The voltage gain equations of the proposed converter in DCM and CCM demonstrate that it has a higher voltage transfer gain compared to previous DC-DC converters. Additionally, two passive components, L₂ and C₁, become open circuits as depicted in Figure 3f. Moreover, D₁ operates at Zero Current Switching and experiences low voltage stress, thereby reducing the total power loss of the converter. This reduction occurs because L₂ reaches zero charging when the charge across C₁ becomes zero. The current flowing through Sw₁ is solely sourced from iL₁.

4. Voltage across Power Diodes, MOSFETs and Capacitor

The proposed converter has two power switches, three power diodes, and four capacitors. Therefore, in this section, the voltage stress across power MOSFETs is calculated. Furthermore, the voltages across the power diodes and capacitors of the proposed converter are also calculated.

$$V_{D_1}=\frac{Vs}{(1-D)}$$

(44)

$$V_{D_2}=\frac{Vs}{(1-D)}$$

(45)

$$V_{D_3}=\frac{VsD}{{(1-D)}^2}$$

(46)

In order to find the voltage stress across the power diodes in the proposed converter, we can use Equation (44) to determine the voltage stress across D₁, which is a very small value. Equation (45) can be used to obtain the voltage stress across D₂, while Equation (46) provides the means to find the voltage stress across D₃. It can be observed that the voltage across the power diodes is very small and depends on the input voltage, which ranges from 20 V to 40 V.

$$Vs{w}_1=\frac{VsD}{(1-D)}$$

(47)

$$Vs{w}_2=\frac{Vs}{(1-D)},average voltage$$

(48)

To determine the voltage stress across the Power MOSFETs, we can use Equation (47) to find the voltage across MOSFET Sw₁. This voltage is also very small and depends on the input voltage, which varies from 20 V to 40 V. Additionally, Equation (48) allow us to calculate the average voltage stress across Sw₂. During the time period D < t < D1, the voltage across Sw₂ is equal to the output voltage. During the time period D1 < t < Ts, it is equal to the average voltage across C₂.

$$V{c}_1=\frac{Vs}{(1-D)}-\sqrt{\frac{2LeV{o}^2}{RL{D}^{2}Ts}} \left(D<0.5\right)$$

(49)

$$V{c}_2=\frac{Vs}{(1-D)}$$

(50)

$$Vc4=Vo$$

(51)

To determine the voltage across capacitors, we can refer to Equation (49) for the voltage across C₁ and Equation (50) for the voltage across C₂. Additionally, Equation (51) provides the means to find the voltage across the filter capacitor, which is equal to the output voltage. By reducing the voltage stress on all power diodes and power MOSFETs, the proposed converter experiences decreased losses, leading to improved efficiency.

5. Features Components of Proposed Converter

In this section, we discuss the main components of 200 W prototype of proposed converter, which include inductors, capacitors, power diodes, power Mosfet, and gate drive circuit. Therefore, these components are crucial for designing and verifying the high voltage gain of the proposed converter. The suggested converter has four small values of inductors, four small values of capacitors.

Table 1. Prototype parameters design for the proposed converter.

SiC MOSFET	650 V, 40 A. 35 mΩ
SiC Schottcky diode	1200 V 40 A
L1 L2 L3 L4	100 uh 2.9 mΩ 3 uh 1.5 mΩ 100 uh 2.9 mΩ 15 uh 2.2 mΩ
C1 C2 C3 C4	1 uF 100 V 200 uF 100 V 2 uF 500 V 100 uF 500 V
Vs	20–40 V
Vo	200 V
Power	200 w
Duty Cycle (D)	0.45
Fs Switching Frequency	150 KHZ
Inductor size (L1 = L3 = L4)	(L/2.85 cm·W/2.75 cm·H/2.5 cm)
Inductor size L2	(L/1.85 cm·W/1.5 cm·H/2 cm)

provides the parameters of the prototype design for the proposed converter.

It can be observed from Table 1 that the values of the inductors become significantly smaller when a high switching frequency is employed. Furthermore, the internal resistance of the inductors is also minimized, resulting in reduced total power losses for the proposed converter. The sizes of the inductors are provided in Table 1. It is evident that by utilizing a high switching frequency, the overall dimensions of the proposed converter are substantially reduced. The inductor specifications used in the proposed converter involve a ferrite core with flat wire to minimize internal resistance. To design the inductors of the proposed converter, L₁ can be designed using Equation (52), C₁ and L₂ can be designed using Equation (53). Inductor L₃ and L₄ can be found using Equation (54). C₂, C₃, and C₄ can be determined using Equations (55), (56), and (57), respectively.

$$L_1\ge \frac{VsD}{Fs\Delta iL1}$$

(52)

$$\left.\begin{array}{l}{L}_2=\frac{4{\pi }^{2}F{s}^{3}RL(1 - D)\Delta V{c}_1}{DVo}\\ C_1=\frac{VoD}{\Delta V{c}_{1}FsRL(1 - D)}\end{array}\right\}$$

(53)

$$\left.\begin{array}{l}{L}_3\ge \frac{VsD}{Fs\Delta i{L}_3(1 - D)}\\ L_4\ge \frac{8VsD}{Fs\Delta i{L}_4(1 - D)}\end{array}\right\}$$

(54)

$$C_2=\frac{VoD}{\Delta Vc2RLFs(1 - D)}$$

(55)

$$C_3=\frac{6VoD}{FsRL}$$

(56)

$$C_4=\frac{VoD}{\Delta V{c}_{4}FsRL}$$

(57)

6. Comparison the Proposed Converter with Previous DC DC Converters

In this section, the proposed converter is compared to previous DC-DC converters. Both the previous works and the proposed converter are simulated in Matlab Simulink under the same conditions. From Figure 5, it can be observed that the voltage gain of the proposed converter is higher than that of the previous converters. A higher gain at a low duty cycle implies lower conduction losses, lower switching losses, higher efficiency, and a reduced number of inductors and capacitors. As shown in Figure 6a, the power MOSFET in the proposed converter experiences lower voltage stress compared to the power MOSFET in the previous converters. However, the voltage stress across the power MOSFET in the proposed converter slightly increases as the voltage gain increases. Regarding the voltage across the diodes, Figure 6b demonstrates that the voltage stress across the diode in the proposed converter is lower than in previous DC-DC converters.

The proposed DC-DC converter is compared with the previous DC-DC converters in

Table 2. Comparison between the Proposed Converter and Previous DC DC Converters.

Items	Proposed Converter	Ref [36]	Ref [9]	Ref [13]	Ref [15]	Ref [19]	Ref [21]	Ref [4]	Ref [31]
Switching Frequency	150	5	50	100	50	66	24	45	30
Vs	20–40	24	20–40	50 v	15 v	24	20	20	25 v
Vo	200 v	107 v	200 v	400 v	90 v	180	300 v	Out1 = 155	110 v
Inductors	4	2	4	3	3	3	2	2	4
capacitors	4	3	1	5	4	3	4	8	6
Diodes	3	4	7	4	5	2	4	7	3
switches	2	1	2	1	2	1	1	1	1
Duty cycle	45%	64%	70%	72%	50%	88%	77%	77%	60%
Power (w)	200	52	200	200	200	100	250	250	110
Efficiency	96.5%	91.2%	90%	94.5%	95%	94%	93.5%	90%	94.5%
Input Current	No Pulsating	Pulsating	Pulsating	Pulsating	No Pulsating	Pulsating	No Pulsating	Pulsating	Pulsating
Gain	$\frac{D}{{\left(1 - D\right)}^2}$	$\frac{\left(4 - 3D\right)}{\left(1 - D\right)}$	$\frac{\left(1 + 3D\right)}{\left(1 - D\right)}$	$\frac{\left(1 + 2D\right)}{\left(1 - D\right)}$	$\frac{\left(3 - D\right)}{\left(1 - D\right)}$	$\frac{\left(2D\right)}{\left(1 - D\right)}$	$\frac{(3 + D)}{2(1 - D)}$	$\frac{3}{\left(1 - 2D\right)}$	$\frac{\left(3D\right)}{{\left(1 - D\right)}^{}}$

. It can be seen that the proposed converter operates at a higher switching frequency than previous DC-DC converters. A low switching frequency requires high values of inductors and capacitors with high internal resistance, resulting in high switching and conduction losses, particularly at high duty cycles. Furthermore, high values of passive components result in high weight, high cost, and large size.

The proposed converter can step up a low input voltage at a duty cycle of 45% with a load of 200 W, but other converters in Table 2 can step up a low voltage at a high duty ratio. A high diode count leads to high internal resistance and high forward voltage (Vf), limiting the voltage gain and increasing the converter losses. In addition, a high diode count increases the reverse recovery time, which also affects the system’s performance. In addition, the proposed converter has zero pulsating input current at low and high duty cycles compared to the input current in the previous DC-DC converter. In terms of the voltage gain equations of the proposed and previous DC-DC converters, as shown in Table 2, the proposed converter can achieve a higher voltage gain than the previous DC-DC converters listed in Table 2. Moreover, this means that the proposed converter is more efficient for applications that require high DC voltage gain at different loads, with more flexibility in the duty ratio. It achieves an efficiency of 96.5%. Additionally, the proposed converter is more suitable for RES.

7. Control Strategy of the Proposed Converter

The suggested controller, as shown in Figure 7, uses dual PI controllers to enable the proposed converter to operate with high performance. The first PI controller, known as the inner loop controller, is designed to control the load current. The second PI controller, called the outer loop controller, is responsible for controlling the output voltage of the proposed converter. The voltage controller takes the difference between the desired voltage and the actual output voltage as its input. It then generates a reference current for the load based on this difference. This reference current is limited intentionally to prevent the converter from using high current. The difference between the reference current and the actual current is then used as input for the current controller. The Proportional and Integral gain parameters of the Pi controller are denoted as Kp and Ki, respectively. The parameters Ki and Kp of the outer loop are set to be ten times faster than the parameters of the inner PI loop controller. The method used for tuning the controller parameters is a trial-and-error approach.

After applying the suggested dual PI controller to the proposed converter to verify the fixed output voltage under variable input voltage, Figure 8a shows that the output voltage of the proposed converter stays at 200 V even when the input voltage drops to its lowest values. This means that the suggested controller for the proposed converter is more reliable for applications that need a high consistent output voltage, and it can handle a wide range of duty ratios for higher power density in renewable energy applications. In Figure 8b, it is demonstrated that the converter can provide a variable output voltage ranging from 100 V to 250 V while keeping the input voltage fixed. It also responds quickly to changes, ensuring a swift adjustment in the output voltage.

8. Simulation and Experimental Results and Discussion

In this section, a 200 W PCB prototype is designed to validate the experimental results, as shown in Figure 9a. An experimental test is performed in the laboratory for the proposed converter, as shown in Figure 9b. Additionally, MATLAB Simulink and PLECS software are used to verify the experimental results in different cases.

Figure 10a shows the source-to-gate voltage with a duty cycle of 27% and an output voltage of 218 V, with the input voltage at 40 V. It can be seen that the load current is 0.44 A at 95 W. Figure 10b shows the voltage across capacitors C₁, C₂, and C₃. It can be observed that Vc₁ is equal to the difference between Vs and Vc₂, while the voltage across C₂ is 54.6 V. Furthermore, the average voltage across C₃ is zero. In Figure 10c, the current through switching Sw₁ and Sw₂ and the voltage across Sw₁ and Sw₂ are depicted. It can be seen that the current through Sw₁ is equal to iL₁ and iL₂, matching the shape of both inductor currents. Additionally, the voltage across the MOSFET significantly decreases when the converter operates at low duty cycle.

Figure 10d illustrates the current through D₁, D₂, and D₃. The current through D₁ is in series with L₂ to prevent iL₂ from starting in the reverse direction, having the same shape as the current in L₂. This prevents the input current from becoming pulsating at a low duty cycle. The current across D₂ is equal to iL₂ and iL₁ when D₂ is on, while the current through D₃ is equal to iL₃ and iL₄ when D₃ is on. Figure 10e displays the voltage across diodes D₁, D₂, and D₃. It can be observed that the voltage across power diodes significantly decreases when the converter operates at a low duty cycle. Figure 10f shows the voltage across inductors. The voltage across inductor L₁ is substantially reduced in the on state, equal to the input voltage, while in the off state, it is equal to half the input voltage. The voltage across L₂ in the on state has the same shape as Vc₁, and in the off state, VL₂ is equal to Vc₂ for a short period of time. VL₃ and VL₄ are equal to the value of Vc₂, which is very small during the on state and equal to the output voltage during the off state for a very short time as well. This means low voltage stress on the inductors, reducing the total losses of the proposed converter.

Figure 11a indicates that current flows through the inductors during the on-state period. It is evident that the discharging time of L₂ is smaller than that of L₃ and L₄. Additionally, the discharging time of L₂ is denoted as β₁ when the proposed converter operates in DCMC1. Furthermore, the discharging times of L₃ and L₄ are equal to D1, and both discharging times (D1 and β₁) depend on the values of RL, Vo, D. The inductor L₁ exhibits a long discharge time, does not reach zero, and shows no pulsation during the off states. Figure 11b illustrates the current through the inductors when the proposed converter operates in CCM. Figure 11c presents the load current of the proposed converter, which is 1 A at an input voltage of Vs = 20 V and an output voltage of 212 V at 200 W. Figure 11d depicts an input voltage of Vs = 40 V and an output voltage of 208 V at a load current of 1 A at 200 W. It can be observed that the current through L₁ is still in CCM, while the current through L₃ and L₄ is in DCM at 200 W. This approach aims to reduce voltage stress across Sw₂ and inductors L₃ and L₄, thereby enhancing the performance and efficiency of the proposed converter. Figure 11e shows the voltage across D₁, and it can be seen that in the on state, the voltage across D₁ is around 22 V during the period (D − β₂ < t < D). D₁ works in ZCS, and inductor L₂ is an open circuit during this time. Therefore, when the input voltage is decreased to the minimum value, the proposed converter can work with high performance with one power diode working in ZCS, reducing the number of passive components. In addition, the voltage stress across D₂ will be reduced when the converter works in DCMC2 when capacitor C₁‘s charge becomes zero at (D − β₂).

Figure 11f shows that the current reduction of Sw₁ occurs when capacitor C₁’s charge becomes zero at (D − β₂). After this period, the current through Sw₁ will come only from L₁. This means that the RMS current of Sw₁ will be significantly reduced when the converter operates at high current. The value of β₂ depends on the values of C₁ and L₂. This means that the proposed converter can supply high load current with high efficiency, especially for battery charging and renewable energy applications.

Figure 12a shows the inductor currents L₁ and L₂ when the converter operates in DCMC1 at D = 0.45. In Figure 12b, the inductor currents L₁ and L₂ can be observed when the proposed converter operates in DCMC2. Figure 12c demonstrates that the current through inductors L₃ and L₄ operates in DCM, with both inductors having the same value but in opposite directions. This method aims to reduce voltage stress across Sw₂ during the very long period of time (D₁ < t < Ts), as previously mentioned.

In Figure 12d, the output voltage of the proposed converter is 200 V at a load current of 1 A, as shown in Figure 12e when the proposed converter operates in DCMC2. The currents through Sw₁ and Sw₂ are depicted in Figure 12f. It can be seen that the voltage across Sw₁ is equal to 54 V, which is a very low voltage as shown in Figure 13a. Figure 13b shows the voltage across Sw₂, which remains at 54 V for a long time period (D₁ < t < Ts). Figure 13c illustrates the voltage stress across D₃. Furthermore, Figure 13d shows the voltage across D₁, indicating that during the on state, the voltage across D₁ is around 22 V in the period (D − β₂ < t < D), with D₁ operating in ZCS, while the inductor L₂ acts as an open circuit during this time. As mentioned earlier, the voltage stress across D₂ will be reduced when the converter works in DCMC2, as capacitor C₁’s charge becomes zero at (D − β₂).

Figure 13e displays the voltage across C₂, which is equal to 52 V at D = 0.45. Additionally, the proposed converter can supply a variable output voltage, as shown in Figure 13f, where the output voltage is 250 V. These qualities make the suggested converter highly efficient and enable it to perform exceptionally well. Moreover, it can supply high currents, even when the duty ratios vary over a wide range.

The proposed converter demonstrates a higher level of performance compared to previous DC-DC converters. Notably, the power MOSFETs in the proposed converter experience significantly reduced voltage stress when operating in Discontinuous Conduction Mode (DCM) for both cases. Additionally, the single-cell switched inductor capacitor operates in resonant mode when the duty cycle exceeds 50%.

Furthermore, one of the passive elements, L₂, becomes an open circuit when the charge on capacitor C₁ reaches zero at (D − β₂). This approach effectively reduces the voltage stress across the power MOSFETs and all diodes, while also minimizing the current stress on the main switch. This is achieved by ensuring that the current through the main switch is solely derived from L₁, which is equal to the input current.

The proposed converter also achieves a reduction in power losses, resulting in increased overall efficiency. Specifically, the efficiency of the converter reaches 96.5% at 200 W. Additionally, the input current does not reach zero at low duty cycles, making the proposed converter more efficient and well-suited for Renewable Energy Systems (RESs).

9. The Proposed Converter Efficiency Calculation

The proposed converter consists of four inductors, four capacitors, two power switches, and three diodes. These components, both passive and active, are not ideal. For example, an inductor has internal resistance, which increases as its value increases. The internal resistances of the inductors are denoted as rl₁, rl₂, rl₃, and rl₄. Similarly, the capacitors C₁, C₂, C₃, and C₄ have equivalent series resistances rc₁, rc₂, rc₃, and rc₄. The power diode also incurs power losses due to its internal resistance and forward voltage Vf. Additionally, power losses occur due to conduction and switching losses in the power MOSFET devices. Therefore, it is important to consider all of these losses for the proposed converter. The internal resistances of all active and passive elements are illustrated in Figure 14.

$$Irms=\sqrt{\frac{1}{Ts}{\displaystyle \underset{0}{\overset{Ts}{\int }}{(I)}^{2}dt}}$$

(58)

$$Isw1rms=\sqrt{\frac{1}{Ts}[{\displaystyle \underset{0}{\overset{(D-{\beta }_2)Ts}{\int }}{(iL1+iL2)}^{2}dt+{\displaystyle \underset{(D-{\beta }_2)Ts}{\overset{D}{\int }}{(iL1)}^{2}dt]}}}$$

(59)

$$Isw2rms=\sqrt{\frac{1}{Ts}{\displaystyle \underset{0}{\overset{DTs}{\int }}{(iL3+iL4)}^{2}dt}}$$

(60)

To calculate the total power losses of the proposed converter, the rms current is required for calculations related to the inductors, capacitors, power MOSFET, and diodes in both the on and off states. Equation (58) represents the general equation for rms current, and Equations (59) and (60) can be used to obtain the rms current through Sw₁ and Sw₂ during the on state.

$$ID1rms=\sqrt{\frac{1}{Ts}{\displaystyle \underset{0}{\overset{(D-{\beta }_2)Ts}{\int }}{(iL2)}^{2}dt}}=iL2rms$$

(61)

$$ID2rms=\sqrt{\frac{1}{Ts}{\displaystyle \underset{D}{\overset{Ts}{\int }}{(iL1)}^{2}dt}}$$

(62)

$$ID3rms=\sqrt{\frac{1}{Ts}{\displaystyle \underset{D}{\overset{Ts}{\int }}{(iL3+iL4)}^{2}dt}}$$

(63)

To calculate the rms current through power diodes, Equation (61) provides the rms current through D₁ during the on state, which is equivalent to the rms current through inductor L₂. Equations (62) and (63) describe the rms current across D₂ and D₃, respectively.

$$Ic1rms=\sqrt{\frac{1}{Ts}[{\displaystyle \underset{0}{\overset{(D-{\beta }_2)Ts}{\int }}{(iL2)}^{2}dt+{\displaystyle \underset{D}{\overset{Ts}{\int }}{(iL1)}^{2}dt]}}}$$

(64)

$$Ic2rms=\sqrt{\frac{1}{Ts}[{\displaystyle \underset{0}{\overset{DTs}{\int }}{(iL3+iL4)}^{2}dt+{\displaystyle \underset{D}{\overset{Ts}{\int }}{(iL1)}^{2}dt]}}}$$

(65)

$$Ic3rms=\sqrt{\frac{1}{Ts}[{\displaystyle \underset{0}{\overset{DTs}{\int }}{(iL4)}^{2}dt+{\displaystyle \underset{D}{\overset{Ts}{\int }}{(iL3)}^{2}dt]}}}$$

(66)

$$Ic4rms=\sqrt{\frac{1}{Ts}[{\displaystyle \underset{0}{\overset{DTs}{\int }}{(iL4)}^{2}dt+{\displaystyle \underset{D}{\overset{Ts}{\int }}{(iL3+iL4)}^{2}dt]}}}$$

(67)

To calculate the rms current through capacitors C₁, C₂, C₃, and C₄, the values can be determined from Equations (64), (65), (66), and (67), respectively.

$$Is{w}_{1}rms=\frac{IoD\sqrt{4D-3{\beta }_2}}{{(1-D)}^2}$$

(68)

$$Is{w}_{2}rms=\frac{Io\sqrt{D}}{(1-D)}$$

(69)

After solving the rms values in Equations (59) and (60), the resulting Equations (68) and (69) describe the rms current through Sw₁ and Sw₂, respectively.

$$I{D}_{1}rms=\frac{IoD\sqrt{D-{\beta }_2}}{{(1-D)}^2}=i{L}_{2}rms$$

(70)

$$I{D}_{2}rms=\frac{IoD}{\sqrt{{(1-D)}^3}}$$

(71)

$$I{D}_{3}rms=\frac{Io}{\sqrt{(1-D)}}$$

(72)

After solving for the rms values, Equations (70)–(72) provide the rms currents through the power diodes.

$$i{L}_{1}rms=\frac{IoD}{{(1-D)}^2}$$

(73)

$$i{L}_{3}rms=iL4rms=\frac{Io}{(1-D)}$$

(74)

Furthermore, Equations (73) and (74) provide the rms current through inductors L₁, L₃, and L₄. Equations (75)–(78) yield the rms current for capacitors C₁, C₂, C₃, and C₄, respectively.

$$I{c}_1{}^{}rms=\frac{IoD\sqrt{(1-{\beta }_2)}}{{(1-D)}^2}$$

(75)

$$I{c}_{2}rms=\frac{IoD\sqrt{1+D(1-D)}}{\sqrt{{(1-D)}^3}}$$

(76)

$$I{c}_{3}rms=Io\sqrt{\frac{D}{1-D}}$$

(77)

$$I{c}_{4}rms=Io\sqrt{\frac{D}{1-D}}$$

(78)

9.1. Conduction Losses Calculation for MOSFET Devices

Conduction losses refer to the power losses that occur when current flows through a device, such as a power MOSFET or any other semiconductor device. These losses are primarily caused by the resistance of the device’s conducting path, resulting in power dissipation in the form of heat.

To calculate the conduction losses of the power MOSFET in the proposed converter, the square value of the rms current is multiplied by the internal resistance of the MOSFET, as shown in Equation (79).

$$\begin{gathered} Pcd1=\frac{Po{D}^2(4D-3{\beta }_2)}{RL{(1-D)}^4}rds1 \\ Pcd2=\frac{PoD}{RL{(1-D)}^2}rds2 \end{gathered}$$

(79)

From Equation (79), the power conduction losses of power MOSFETs, Pcd1, and Pcd2, can be obtained.

9.2. Switching Losses Calculation for MOSFET Devices

Switching losses, also known as dynamic losses, are the power losses that occur during the switching transitions of a power electronic device, such as a power MOSFET. These losses result from the energy dissipated as the device switches between the on and off states. Switching losses are mainly caused by the charging and discharging of internal capacitances, as well as the voltage and current overlapping during the switching process.

To calculate the switching losses of the power MOSFET in the proposed converter, half of the square of the voltage stress across the MOSFET during the off state is multiplied by the switching frequency and the output capacitor of the power MOSFET (Co).

$$\begin{gathered} \begin{array}{l}Esw=\frac{1}{2}CoVs{w}^2\\ P_{SW}=EswFs\end{array} \\ {P}_{SWL1}=\frac{V{s}^2{D}^2}{2{(1-D)}^2}FsCo \\ {P}_{SWL2}=\frac{V{s}^2{D}^2}{2{(1-D)}^4}FsCo \end{gathered}$$

(80)

where, (Esw) is the energy dissipated during one switching cycle. From Equation (80), the power switching losses of the MOSFETs Sw₁ and Sw₂, denoted as PSWL1,2, can be obtained.

9.3. Total Power Loss in MOSFET Devices

$$PTML1,2=\frac{Po{D}^2(4D-3{\beta }_2)}{RL{(1-D)}^4}rds1+\frac{PoD}{RL{(1-D)}^2}rds2+\frac{V{s}^2{D}^2}{2{(1-D)}^2}FsCoFsCo+\frac{V{s}^2{D}^2}{2{(1-D)}^4}FsCo$$

(81)

From Equation (81), PTML1,2 can be obtained as the total power losses of Sw₁ and Sw₂ by adding Equations (79) and (80).

9.4. Losses in Power Diode

Power losses in the diode can be divided into two components: losses due to internal resistance rd and losses due to the forward diode voltage Vf. Therefore, all power losses from the three diodes in the converter must be taken into account. From Equation (82), the average current (IDav) through diodes can be calculated:

$$\left.\begin{array}{l}{I}_{D1av}=\frac{PoD(D - {\beta }_2)}{RL{(1 - D)}^2}\\ I_{D2av}=\frac{IoD}{(1 - D)}\\ \\ I_{D3av}=Io\end{array}\right\}$$

(82)

In order to find the power losses due to forward voltage (Pvf), Equation (82) is multiplied by Vf, resulting in Equation (83).

$$\left.\begin{array}{l}{P}_{Vf}={}_{IDav}Vf\\ P_{Vf1}={Vf}_1\frac{PoD(D - {\beta }_2)}{RL{(1 - D)}^2}\\ P_{Vf2}={Vf}_2\frac{IoD}{(1 - D)}\\ \\ P_{Vf3=}Vf3Io\end{array}\right\}$$

(83)

To calculate the diode power losses due to internal resistance (rd), the square of the diode’s rms current is multiplied by rd, as shown in Equation (84).

$$\left.\begin{array}{l}{P}_{Dr}=IDrmsrd\\ P_{Dr1}=\frac{Po{D}^2(D - {\beta }_2)}{RL{(1 - D)}^2}rd1\\ P_{Dr2}=\frac{Po{D}^2}{RL{(1 - D)}^3}rd2\\ P_{Dr3}=\frac{Po}{RL(1 - D)}rd3\end{array}\right\}$$

(84)

The total power losses PDL_1,2,3 across the three diodes can be found in Equation (85), by adding all the losses in the power diodes.

$$P_{DL1,2,3}=P_{Dr1,2,3}+P_{Vf1,2,3}$$

(85)

9.5. Power Losses in Inductors and Capacitors

The inductor used in the proposed converter has a very low internal resistance, as shown in Table 1. Additionally, the inductors and capacitors of the proposed converter are designed for high switching frequency, resulting in the converter operating with very high efficiency and performance. Calculation of the power losses due to the internal resistance of the inductors and capacitors are shown below:

$$\left.\begin{array}{l}PL=iLrm{s}^{2}rl\\ PL1=\frac{Po{D}^2}{RL{(1 - D)}^4}rl1\\ PL2=\frac{Po{D}^2(D - {\beta }_2)}{RL{(1 - D)}^2}rl2\\ PL3=\frac{Po}{RL{(1 - D)}^2}rl3\\ PL4=\frac{Po}{RL{(1 - D)}^2}rl4\end{array}\right\}$$

(86)

$$\left.\begin{array}{l}PC=Icrm{s}^{2}rc\\ P{C}_1=\frac{Po{D}^2(1 - {\beta }_2)}{RL{(1 - D)}^4}r{c}_1\\ P{C}_2=\frac{Po{D}^2(1 + D(1 - D))}{RL{(1-D)}^3}r{c}_2\\ P{C}_3=\frac{PoD}{RL(1 - D)}r{c}_3\\ P{C}_4=\frac{PoD}{RL(1 - D)}r{c}_4\end{array}\right\}$$

(87)

From Equations (86) and (87), the power losses P_L and P_C in the inductors and capacitors can be found, respectively.

9.6. Total Power Losses in Proposed Converter

The proposed converter losses can be divided into MOSFET losses, diode losses, inductor losses, and capacitor losses. The total power loss (T_PPCL) of the proposed converter can be found in Equation (88), which involves summing the power losses in the power MOSFETs (P_TML1,2), the total power losses in the diodes (P_DL1,2,3), and the losses in the inductors and capacitors (P_L1,2,3,4) and (P_C1,2,3,4), respectively. The proposed converter efficiency can be obtained using Equation (89).

$$T_{PPCL}=P_{TML1,2}+P_{DL1,2,3}+P_{L1,2,3,4}+P_{C1,2,3,4}$$

(88)

$$\eta =\frac{Po}{Po+T_{PPCL} }100\%$$

(89)

The use of SiC MOSFETs with very low on-state resistance is a better choice to reduce conduction losses. Additionally, using inductors with low values and very low internal resistance can increase the performance and efficiency of the proposed converter.

Figure 15a shows that the proposed converter’s output voltage increases as the switching frequency increases. This implies that the design of the proposed converter allows for boosting low voltage to high voltage at a low duty cycle, achieving high power density with an efficiency of 96.5%. Figure 15b provides a comprehensive visual representation of the losses incurred by the proposed converter. It is worth noting that a significant proportion of these losses can be attributed to the power MOSFETs and diodes used in the converter. These losses result from the switching and conduction characteristics exhibited by these components during the converter’s operation. Furthermore, a portion of the losses can be attributed to the inherent resistance of the inductors and capacitors present in the system.

Figure 16a,b illustrates the conduction power losses of MOSFETs Sw₁ and Sw₂ at different input voltages. It can be observed that the conduction power losses for both MOSFET switches slightly increased as the input voltage rose from 10 V to 40 V. Additionally, the conduction losses showed a significant decrease as the duty cycle decreased.

This indicates that the SiC MOSFET utilized in the proposed converter exhibits very low power conduction losses, particularly at variable duty cycles. Consequently, the proposed converter achieves higher efficiency compared to previous DC-DC converters. By employing WBG (Wide Bandgap) MOSFETs, both conduction and switching losses can be substantially reduced, leading to a significant increase in the converter’s efficiency.

Figure 17a,b displays the efficiency of the proposed converter at various input voltages. The results indicate that at an input voltage of 30 V and a duty cycle of 50%, the converter achieves an efficiency of approximately 97.3% when operating at a power level of 200 W. This demonstrates that the proposed converter is capable of stepping up a low input voltage under light load current conditions, while also providing high load current at the maximum input voltage.

10. Conclusions

As a result, a new single-cell hybrid switched inductor DC-DC converter is proposed to demonstrate the verification of ultra-high voltage gain in photovoltaic applications. The modification in the proposed converter helps prevent the input current from pulsating to zero at very low duty cycles, making it more efficient for renewable energy applications. The single cell of the hybrid inductor is interleaved with the main switch to reduce current stress when the load current increases and the capacitor charge becomes zero. Moreover, the addition of a modified hybrid switch inductor with a capacitor, operating in dual boosting mode with a single switch, allows the converter to achieve ultra-high voltage gain.

The proposed converter offers several advantages, including ultra-high voltage gain, high efficiency, low voltage stress on power MOSFETs, diodes, inductors, and capacitors, as well as low switching and conduction losses. Furthermore, the proposed converter utilizes transformerless and non-coupled inductors. Additionally, the proposed converter’s efficiency is around 96.5% when the input voltage is 20 V with a duty cycle of 0.6. The increased flexibility in the duty cycle allows the proposed converter to operate at high power density and convert very low input voltage to high output voltage for renewable energy systems.

In addition, the output voltage of the proposed converter increases when the switching frequency is increased to boost low input to high output voltage at a low duty cycle. The voltage stress on the power devices has been reduced compared to existing DC-DC converters. Moreover, using a high switching frequency reduces the component values and circuit size, resulting in a significant reduction in the weight of the proposed converter. Passive components of the proposed converter are reduced when the converter operates in (DCM) and (CCM), which improves converter efficiency and performance.