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9 pages, 6367 KB  
Article
1200V 4H-SiC MOSFET with a High-K Source Gate for Improving Third-Quadrant and High Frequency Figure of Merit Performance
by Mingyue Li, Zhaofeng Qiu, Tianci Li, Yi Kang, Shan Lu and Xiarong Hu
Micromachines 2025, 16(5), 508; https://doi.org/10.3390/mi16050508 - 27 Apr 2025
Viewed by 1262
Abstract
This paper proposes a 1200V 4H-SiC MOSFET incorporating a High-K dielectric-integrated fused source-gate (HKSG) structure, engineered to concurrently enhance the third-quadrant operation and high-frequency figure of merit (HF-FOM). The High-K dielectric enhances the electric field effect, reducing the threshold voltage of the source-gate. [...] Read more.
This paper proposes a 1200V 4H-SiC MOSFET incorporating a High-K dielectric-integrated fused source-gate (HKSG) structure, engineered to concurrently enhance the third-quadrant operation and high-frequency figure of merit (HF-FOM). The High-K dielectric enhances the electric field effect, reducing the threshold voltage of the source-gate. As a result, the reverse conduction voltage drops from 2.79 V (body diode) to 1.53 V, and the bipolar degradation is eliminated. Moreover, by incorporating a shielding area within the merged source-gate architecture, the gate-to-drain capacitance Cgd of the HKSG-MOS is reduced. The simulation results show that the HF-FOM Cgd × Ron,sp and Qgd × Ron,sp of the HKSG-MOS are decreased by 48.1% and 58.9%, respectively, compared with that of conventional SiC MOSFET. The improved performances make the proposed SiC MOSFEET have great potential in high-frequency power applications. Full article
(This article belongs to the Section D1: Semiconductor Devices)
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13 pages, 5715 KB  
Communication
Enhanced Short-Circuit Robustness of 1.2 kV Split Gate Silicon Carbide Metal Oxide Semiconductor Field-Effect Transistors for High-Frequency Applications
by Kanghee Shin, Dongkyun Kim, Minu Kim, Junho Park and Changho Han
Electronics 2025, 14(1), 163; https://doi.org/10.3390/electronics14010163 - 3 Jan 2025
Cited by 1 | Viewed by 2714
Abstract
Split Gate SiC MOSFETs (SG-MOSFETs) have been demonstrated to exhibit excellent power dissipation at high operating frequencies due to their low specific reverse transfer capacitance (Crss,sp); however, there are several reliability issues of SG-MOSFETs, including electric field crowding at the [...] Read more.
Split Gate SiC MOSFETs (SG-MOSFETs) have been demonstrated to exhibit excellent power dissipation at high operating frequencies due to their low specific reverse transfer capacitance (Crss,sp); however, there are several reliability issues of SG-MOSFETs, including electric field crowding at the gate oxide and insufficient short-circuit (SC) robustness. In this paper, we propose a device structure to enhance the short-circuit withstand time (SCWT) of 1.2 kV SG-MOSFETs. The proposed P-shielded SG-MOSFETs (PSG-MOSFETs) feature a P-shielding region that expands the depletion region within the JFET region under both blocking mode and SC conditions. Compared to the conventional structure, this reduces the maximum electric field in the gate oxide, enabling a higher doping concentration in the JFET region, which can reduce the specific on-resistance (Ron,sp) to minimize power dissipation during device operation. The SC robustness of PSG-MOSFETs, with an Ron,sp identical to those of SG-MOSFETs, was investigated by adjusting the width of the P-shielding region (WP). Furthermore, the Crss,sp of PSG-MOSFETs was compared with that of SG-MOSFETs to analyze the relationship between the WP and high-frequency figure of merit (HF-FOM), defined as Ron,sp × Crss,sp. These results demonstrated that the PSG-MOSFET achieved an enhanced SC robustness and HF-FOM in comparison to the SG-MOSFET. Thus, the proposed PSG-MOSFET is a highly suitable candidate for high-frequency and reliable applications. Full article
(This article belongs to the Special Issue Wide-Bandgap Device Application: Devices, Circuits, and Drivers)
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13 pages, 6005 KB  
Article
A Novel SiC Vertical Planar MOSFET Design and Optimization for Improved Switching Performance
by Rui Jin, Zheyang Li, Shijie Liu, Ling Sang, Xiran Chen, Handoko Linewih, Yu Zhong, Feng He, Yawei He and Jisheng Han
Electronics 2024, 13(24), 4933; https://doi.org/10.3390/electronics13244933 - 13 Dec 2024
Cited by 2 | Viewed by 3399
Abstract
A novel cell topology for a vertical 1200 V SiC planar double-implanted MOSFET (DMOSFET) is proposed in this work. Based on the conventional linear cell topology and the calibrated two-dimensional (2D) technology computer-aided design (TCAD) model parameters, a novel cell topology with the [...] Read more.
A novel cell topology for a vertical 1200 V SiC planar double-implanted MOSFET (DMOSFET) is proposed in this work. Based on the conventional linear cell topology and the calibrated two-dimensional (2D) technology computer-aided design (TCAD) model parameters, a novel cell topology with the insertion of P+ body implanted regions over a fractional part of the channel and junction field effect transistor (JFET) regions was designed and optimized to achieve a low high-frequency figure of merit (HF-FOM, Ron × Cgd). Utilizing three-dimensional (3D) TCAD simulations, the new proposed cell topology with optimized selected structure parameters exhibits an HF-FOM of 328.748 mΩ·pF, which is 10.02% lower than the conventional linear topology. It also shows an improvement in the switching performance, with an 11.73% reduction in switching loss. Moreover, the impact of source ohmic contact resistivity on the performance of the proposed cell topology was highlighted, indicating the dependency of the source ohmic contact resistivity on the switching performance. This research provides a new perspective for enhancing the switching performance of SiC MOSFETs in high-frequency applications, considering practical factors such as contact resistivity. Full article
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13 pages, 5105 KB  
Communication
A Low-Loss 1.2 kV SiC MOSFET with Improved UIS Performance
by Lijuan Wu, Mengyuan Zhang, Jiahui Liang, Mengjiao Liu, Tengfei Zhang and Gang Yang
Micromachines 2023, 14(5), 1061; https://doi.org/10.3390/mi14051061 - 17 May 2023
Viewed by 2744
Abstract
In this article, a 1.2-kV-rated double-trench 4H-SiC MOSFET with an integrated low-barrier diode (DT-LBDMOS) is proposed which eliminates the bipolar degradation of the body diode and reduces switching loss while increasing avalanche stability. A numerical simulation verifies that a lower barrier for electrons [...] Read more.
In this article, a 1.2-kV-rated double-trench 4H-SiC MOSFET with an integrated low-barrier diode (DT-LBDMOS) is proposed which eliminates the bipolar degradation of the body diode and reduces switching loss while increasing avalanche stability. A numerical simulation verifies that a lower barrier for electrons appears because of the LBD; thus, a path that makes it easier for electrons to transfer from the N+ source to the drift region is provided, finally eliminating the bipolar degradation of the body diode. At the same time, the LBD integrated in the P-well region weakens the scattering effect of interface states on electrons. Compared with the gate p-shield trench 4H-SiC MOSFET (GPMOS), the reverse on-voltage (VF) is reduced from 2.46 V to 1.54 V; the reverse recovery charge (Qrr) and the gate-to-drain capacitance (Cgd) are 28% and 76% lower than those of the GPMOS, respectively. The turn-on and turn-off losses of the DT-LBDMOS are reduced by 52% and 35%. The specific on-resistance (RON,sp) of the DT-LBDMOS is reduced by 34% due to the weaker scattering effect of interface states on electrons. The HF-FOM (HF-FOM = RON,sp × Cgd) and the P-FOM (P-FOM = BV2/RON,sp) of the DT-LBDMOS are both improved. Using the unclamped inductive switching (UIS) test, we evaluate the avalanche energy of devices and the avalanche stability. The improved performances suggest that DT-LBDMOS can be harnessed in practical applications. Full article
(This article belongs to the Special Issue Power Semiconductor Devices and Applications)
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11 pages, 3279 KB  
Article
Surface Plasmon Resonance Biosensor Chip for Human Blood Groups Identification Assisted with Silver-Chromium-Hafnium Oxide
by Purnendu Shekhar Pandey, Sanjeev Kumar Raghuwanshi, Rajesh Singh and Santosh Kumar
Magnetochemistry 2023, 9(1), 21; https://doi.org/10.3390/magnetochemistry9010021 - 5 Jan 2023
Cited by 16 | Viewed by 2897
Abstract
Chromium (Cr), silver (Ag) and hafnium oxide (HfO2) are used in a surface plasmon resonance (SPR)-based biosensor with an optimized design for measuring blood groups at a wavelength of 633 nm. A buffer layer was placed on the SPR active metal [...] Read more.
Chromium (Cr), silver (Ag) and hafnium oxide (HfO2) are used in a surface plasmon resonance (SPR)-based biosensor with an optimized design for measuring blood groups at a wavelength of 633 nm. A buffer layer was placed on the SPR active metal in this investigation to avoid oxidation and contamination of blood samples. A theoretical model based on experimental data considered the refractive index of blood samples. The BK7 prism is the optimum substrate material for blood type identification analysis using a combination of Ag and Cr as an SPR active metal. The sensor’s performance is carefully researched in terms of its angular shift and curve width to predict the design aspects that provide precise blood-group identification. The SPR dip slope, detection accuracy and figure of merit (FOM) have been investigated concerning the subsequent generation of biosensor applications. Full article
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6 pages, 1865 KB  
Communication
A New Cell Topology for 4H-SiC Planar Power MOSFETs for High-Frequency Switching
by Shengnan Zhu, Tianshi Liu, Junchong Fan, Arash Salemi, Marvin H. White, David Sheridan and Anant K. Agarwal
Materials 2022, 15(19), 6690; https://doi.org/10.3390/ma15196690 - 27 Sep 2022
Cited by 6 | Viewed by 3220
Abstract
A new cell topology named the dodecagonal (a polygon with twelve sides, short for Dod) cell is proposed to optimize the gate-to-drain capacitance (Cgd) and reduce the specific ON-resistance (Ron,sp) of 4H-SiC planar power MOSFETs. [...] Read more.
A new cell topology named the dodecagonal (a polygon with twelve sides, short for Dod) cell is proposed to optimize the gate-to-drain capacitance (Cgd) and reduce the specific ON-resistance (Ron,sp) of 4H-SiC planar power MOSFETs. The Dod and the octagonal (Oct) cells are used in the layout design of the 650 V SiC MOSFETs in this work. The experimental results confirm that the Dod-cell MOSFET achieves a 2.2× lower Ron,sp, 2.1× smaller high-frequency figure of merit (HF-FOM), higher turn on/off dv/dt, and 29% less switching loss than the fabricated Oct-cell MOSFET. The results demonstrate that the Dod cell is an attractive candidate for high-frequency power applications. Full article
(This article belongs to the Special Issue Silicon Carbide: Material Growth, Device Processing and Applications)
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11 pages, 2437 KB  
Article
Effects of JFET Region Design and Gate Oxide Thickness on the Static and Dynamic Performance of 650 V SiC Planar Power MOSFETs
by Shengnan Zhu, Tianshi Liu, Junchong Fan, Hema Lata Rao Maddi, Marvin H. White and Anant K. Agarwal
Materials 2022, 15(17), 5995; https://doi.org/10.3390/ma15175995 - 30 Aug 2022
Cited by 15 | Viewed by 6060
Abstract
650 V SiC planar MOSFETs with various JFET widths, JFET doping concentrations, and gate oxide thicknesses were fabricated by a commercial SiC foundry on two six-inch SiC epitaxial wafers. An orthogonal P+ layout was used for the 650 V SiC MOSFETs to [...] Read more.
650 V SiC planar MOSFETs with various JFET widths, JFET doping concentrations, and gate oxide thicknesses were fabricated by a commercial SiC foundry on two six-inch SiC epitaxial wafers. An orthogonal P+ layout was used for the 650 V SiC MOSFETs to reduce the ON-resistance. The devices were packaged into open-cavity TO-247 packages for evaluation. Trade-off analysis of the static and dynamic performance of the 650 V SiC power MOSFETs was conducted. The measurement results show that a short JFET region with an enhanced JFET doping concentration reduces specific ON-resistance (Ron,sp) and lowers the gate-drain capacitance (Cgd). It was experimentally shown that a thinner gate oxide further reduces Ron,sp, although with a penalty in terms of increased Cgd. A design with 0.5 μm half JFET width, enhanced JFET doping concentration of 5.5×1016 cm−3, and thin gate oxide produces an excellent high-frequency figure of merit (HF-FOM) among recently published studies on 650 V SiC devices. Full article
(This article belongs to the Special Issue Silicon Carbide: Material Growth, Device Processing and Applications)
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8 pages, 3336 KB  
Communication
A High-Sensitivity Gravimetric Biosensor Based on S1 Mode Lamb Wave Resonator
by Tiancheng Luo, Wenjuan Liu, Zhiwei Wen, Ying Xie, Xin Tong, Yao Cai, Yan Liu and Chengliang Sun
Sensors 2022, 22(15), 5912; https://doi.org/10.3390/s22155912 - 8 Aug 2022
Cited by 7 | Viewed by 3185
Abstract
The development of MEMS acoustic resonators meets the increasing demand for in situ detection with a higher performance and smaller size. In this paper, a lithium niobate film-based S1 mode Lamb wave resonator (HF-LWR) for high-sensitivity gravimetric biosensing is proposed. The fabricated [...] Read more.
The development of MEMS acoustic resonators meets the increasing demand for in situ detection with a higher performance and smaller size. In this paper, a lithium niobate film-based S1 mode Lamb wave resonator (HF-LWR) for high-sensitivity gravimetric biosensing is proposed. The fabricated resonators, based on a 400-nm X-cut lithium niobate film, showed a resonance frequency over 8 GHz. Moreover, a PMMA layer was used as the mass-sensing layer, to study the performance of the biosensors based on HF-LWRs. Through optimizing the thickness of the lithium niobate film and the electrode configuration, the mass sensitivity of the biosensor could reach up to 74,000 Hz/(ng/cm2), and the maximum value of figure of merit (FOM) was 5.52 × 107, which shows great potential for pushing the performance boundaries of gravimetric-sensitive acoustic biosensors. Full article
(This article belongs to the Special Issue Advances and Applications of Micro/Nano-Electronic Sensors)
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31 pages, 2157 KB  
Article
Evolution Trends and Paradigms of Low Noise Frequency Synthesis and Signal Conversion Using Silicon Technologies
by Jean-Guy Tartarin, Éric Tournier and Christophe Viallon
Electronics 2022, 11(5), 684; https://doi.org/10.3390/electronics11050684 - 23 Feb 2022
Viewed by 3964
Abstract
Silicon technologies for HF applications have been proven for more than two decades, and technologies have greatly evolved. Whether CMOS or BiCMOS technologies, the unique combination of radio frequency, baseband, and digital functions allow a very high level of integration. While it is [...] Read more.
Silicon technologies for HF applications have been proven for more than two decades, and technologies have greatly evolved. Whether CMOS or BiCMOS technologies, the unique combination of radio frequency, baseband, and digital functions allow a very high level of integration. While it is possible to achieve fully integrated transceivers, the major advantages of these silicon technologies lie mainly in their unparalleled performance in the field of frequency synthesis and frequency conversion. We propose in this paper a review of the major results obtained on these RF components since the beginning of the 2000s, also considering the impact of the technology node. The back-end of line (BEOL) process on which depends the quality of microwave monolithic integrated circuits (MMICs) is briefly presented in the introductory part. If circuit performances are tightly bound to the active devices (i.e., the heterojunction bipolar transistor SiGe HBT or CMOS transistor), passive elements (i.e., quality factor of inductors and varactors, losses of transmission, or interconnection lines) as well as the definition of the substrate also play a major role. The core of the article is oriented toward the noise of synthesized signals and frequency conversion. Frequency synthesis is presented through the analog design of a voltage-controlled oscillator (VCO) or through the direct digital frequency synthesis (DDFS), for which respective figures of merit are presented and discussed in a second section. The spectral purity of the oscillators being decisive in the definition of the throughput of a link is approached through the comparison of different figures of merit (FoM) for a set of circuits achievements over the selected period. If the realization of free oscillators is closely bound to the phase-locked loop (PLL)-type control loop for VCOs, the DDFS solution provides more direct and more flexible alternative at first sight. Therefore, these two solutions are analyzed collectively. Finally, the oscillator integrated in the transmitter or receiver supplies the needed LO (local oscillator) power to the frequency mixer in the frequency conversion module: henceforth, the third part of this study focuses on high-frequency mixer realizations. We thus consider this LO power in some advanced figure of merit mentioned in the second section. The design trade-off of the mixer is presented in an approach combining LO (conversion gain, channel isolation, and phase noise) and RF (HF noise figure and channel isolation) constraints. The final section provides a summary of the results and trends mentioned in the paper. Full article
(This article belongs to the Special Issue Recent Advances in Silicon-Based RFIC Design)
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12 pages, 5516 KB  
Article
A 1.2 kV SiC MOSFET with Integrated Heterojunction Diode and P-shield Region
by Jongwoon Yoon, Jaeyeop Na and Kwangsoo Kim
Energies 2021, 14(24), 8582; https://doi.org/10.3390/en14248582 - 20 Dec 2021
Cited by 4 | Viewed by 6080
Abstract
A 1.2 kV SiC MOSFET with an integrated heterojunction diode and p-shield region (IHP-MOSFET) was proposed and compared to a conventional SiC MOSFET (C-MOSFET) using numerical TCAD simulation. Due to the heterojunction diode (HJD) located at the mesa region, the reverse recovery time [...] Read more.
A 1.2 kV SiC MOSFET with an integrated heterojunction diode and p-shield region (IHP-MOSFET) was proposed and compared to a conventional SiC MOSFET (C-MOSFET) using numerical TCAD simulation. Due to the heterojunction diode (HJD) located at the mesa region, the reverse recovery time and reverse recovery charge of the IHP-MOSFET decreased by 62.5% and 85.7%, respectively. In addition, a high breakdown voltage (BV) and low maximum oxide electric field (EMOX) could be achieved in the IHP-MOSFET by introducing a p-shield region (PSR) that effectively disperses the electric field in the off-state. The proposed device also exhibited 3.9 times lower gate-to-drain capacitance (CGD) than the C-MOSFET due to the split-gate structure and grounded PSR. As a result, the IHP-MOSFET had electrically excellent static and dynamic characteristics, and the Baliga’s figure of merit (BFOM) and high frequency figure of merit (HFFOM) were increased by 37.1% and 72.3%, respectively. Finally, the switching energy loss was decreased by 59.5% compared to the C-MOSFET. Full article
(This article belongs to the Special Issue Advances in Power Electronics Technologies)
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12 pages, 12132 KB  
Article
3.3-kV 4H-SiC Split-Gate DMOSFET with Floating p+ Polysilicon for High-Frequency Applications
by Kyuhyun Cha, Jongwoon Yoon and Kwangsoo Kim
Electronics 2021, 10(6), 659; https://doi.org/10.3390/electronics10060659 - 11 Mar 2021
Cited by 2 | Viewed by 3469
Abstract
A split-gate metal–oxide–semiconductor field-effect transistor (SG-DMOSFET) is a well-known structure used for reducing the gate–drain capacitance (CGD) to improve switching characteristics. However, SG-DMOSFETs have problems such as the degradation of static characteristics and a high gate-oxide electric field. To solve these [...] Read more.
A split-gate metal–oxide–semiconductor field-effect transistor (SG-DMOSFET) is a well-known structure used for reducing the gate–drain capacitance (CGD) to improve switching characteristics. However, SG-DMOSFETs have problems such as the degradation of static characteristics and a high gate-oxide electric field. To solve these problems, we developed a SG-DMOSFET with floating p+ polysilicon (FPS-DMOSFET) and compared it with a conventional planar DMOSFET (C-DMOSFET) and a SG-DMOSFET through Technology Computer-Aided Design (TCAD) simulations. In the FPS-DMOSFET, floating p+ polysilicon (FPS) is inserted between the active gates to disperse the high drain voltage in the off state and form an accumulation layer over the entire junction field effect transistor (JFET) region, similar to a C-DMOSFET, in the on state. Therefore, the FPS-DMOSFET can minimize the degradation of static characteristics such as the breakdown voltage (BV) and specific on resistance (RON,SP) in the split-gate structure. Consequently, the FPS-DMOSFET can shorten the active gate length and achieve a gate-to-drain capacitance (CGD) that is less than those of the C-DMOSFET and SG-DMOSFET by 48% and 41%, respectively. Moreover, the high-frequency figure of merit (HF-FOM = RON,SP × CGD) of the FPS-DMOSFET is lower than those of the C-DMOSFET and SG-DMOSFET by 61% and 49%, respectively. In addition, the FPS-DMOSFET shows an EMOX of 2.1 MV/cm, which guarantees a gate oxide reliability limit of 3 MV/cm. Therefore, the proposed FPS-DMOSFET is the most appropriate device to be used in high-voltage and high-frequency electronic applications. Full article
(This article belongs to the Special Issue Advances in Wide Bandgap Semiconductor for Power Device Applications)
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15 pages, 7396 KB  
Article
Numerical Simulation Analysis of Switching Characteristics in the Source-Trench MOSFET’s
by Jinhee Cheon and Kwangsoo Kim
Electronics 2020, 9(11), 1895; https://doi.org/10.3390/electronics9111895 - 11 Nov 2020
Cited by 9 | Viewed by 4097
Abstract
In this paper, we compare the static and switching characteristics of the 4H-SiC conventional UMOSFET (C-UMOSFET), double trench MOSFET (DT-MOSFET) and source trench MOSFET (ST-MOSFET) through TCAD simulation. In particular, the effect of the trenched source region and the gate trench bottom P+ [...] Read more.
In this paper, we compare the static and switching characteristics of the 4H-SiC conventional UMOSFET (C-UMOSFET), double trench MOSFET (DT-MOSFET) and source trench MOSFET (ST-MOSFET) through TCAD simulation. In particular, the effect of the trenched source region and the gate trench bottom P+ shielding region on the capacitance is analyzed, and the dynamic characteristics of the three structures are compared. The input capacitance is almost identical in all three structures. On the other hand, the reverse transfer capacitance of DT-MOSFET and ST-MOSFET is reduced by 44% and 24%, respectively, compared to C-UMOSFET. Since the reverse transfer capacitance of DT-MOSFET and ST-MOSFET is superior to that of C-UMOSFET, it improves high frequency figure of merit (HF-FOM: RON-SP × QGD). The HF-FOM of DT-MOSFET and ST-MOSFET is 289 mΩ∙nC, 224 mΩ∙nC, respectively, which is improved by 26% and 42% compared to C-UMOSFET. The switching speed of DT-MOSFET and ST-MOSFET are maintained at the same level as the C-UMOSFET. The switching energy loss and power loss of the DT-MOSFET and ST-MOSFET are slightly improved compared to C-UMOSFET. Full article
(This article belongs to the Section Power Electronics)
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12 pages, 3703 KB  
Article
Fluoride Fiber-Based Plasmonic Biosensor with Two-Dimensional Material Heterostructures: Enhancement of Overall Figure-of-Merit via Optimization of Radiation Damping in Near Infrared Region
by Anuj K. Sharma, Ankit Kumar Pandey and Baljinder Kaur
Materials 2019, 12(9), 1542; https://doi.org/10.3390/ma12091542 - 10 May 2019
Cited by 23 | Viewed by 4543
Abstract
Two-dimensional (2D) heterostructure materials show captivating properties for application in surface plasmon resonance (SPR) sensors. A fluoride fiber-based SPR sensor is proposed and simulated with the inclusion of a 2D heterostructure as the analyte interacting layer. The monolayers of two 2D heterostructures (BlueP/MoS [...] Read more.
Two-dimensional (2D) heterostructure materials show captivating properties for application in surface plasmon resonance (SPR) sensors. A fluoride fiber-based SPR sensor is proposed and simulated with the inclusion of a 2D heterostructure as the analyte interacting layer. The monolayers of two 2D heterostructures (BlueP/MoS2 and BlueP/WS2, respectively) are considered in near infrared (NIR). In NIR, an HBL (62HfF4-33BaF2-5LaF3) fluoride glass core and NaF clad are considered. The emphasis is placed on figure of merit (FOM) enhancement via optimization of radiation damping through simultaneous tuning of Ag thickness (dm) and NIR wavelength (λ) at the Ag-2D heterostructure–analyte interfaces. Field distribution analysis is performed in order to understand the interaction of NIR signal with analyte at optimum radiation damping (ORD) condition. While the ORD leads to significantly larger FOM for both, the BlueP/MoS2 (FOM = 19179.69 RIU−1 (RIU: refractive index unit) at dm = 38.2 nm and λ = 813.4 nm)-based sensor shows massively larger FOM compared with the BlueP/WS2 (FOM = 7371.30 RIU−1 at dm = 38.2 nm and λ = 811.2 nm)-based sensor. The overall sensing performance was more methodically evaluated in terms of the low degree of photodamage of the analyte, low signal scattering, high power loss, and large field variation. The BlueP/MoS2-based fiber SPR sensor under ORD conditions opens up new paths for biosensing with highly enhanced overall performance. Full article
(This article belongs to the Special Issue Flexible Sensors and Actuators for Novel Wearable Solutions)
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