A New Cell Topology for 4H-SiC Planar Power MOSFETs for High-Frequency Switching

A new cell topology named the dodecagonal (a polygon with twelve sides, short for Dod) cell is proposed to optimize the gate-to-drain capacitance (Cgd) and reduce the specific ON-resistance (Ron,sp) of 4H-SiC planar power MOSFETs. The Dod and the octagonal (Oct) cells are used in the layout design of the 650 V SiC MOSFETs in this work. The experimental results confirm that the Dod-cell MOSFET achieves a 2.2× lower Ron,sp, 2.1× smaller high-frequency figure of merit (HF-FOM), higher turn on/off dv/dt, and 29% less switching loss than the fabricated Oct-cell MOSFET. The results demonstrate that the Dod cell is an attractive candidate for high-frequency power applications.


Introduction
The silicon carbide (SiC) power MOSFET has been expected to be the alternative to silicon power devices in multiple applications, such as renewable energy, drivers for electrical machines, and power converters for hybrid and electric vehicles, due to its various advantages, including a low power loss, high switching frequency, and high operating temperature [1][2][3]. Improving energy efficiency (reducing power dissipation) is the driving force for the commercialization of SiC power MOSFETs [3]. The total power loss of a SiC power MOSFET consists of an on-state conduction loss and switching loss. The conduction loss can be reduced by reducing the ON-resistance (R on ). The switching loss of a SiC power MOSFET can be reduced by decreasing device capacitances [4,5]. Studies show that the layout topology design affects the on-state and dynamic performances of SiC power devices [6,7]. Different cell topologies (Linear, Hexagonal, Square, and Octagonal) were used on 600 V SiC planar MOSFETs [7]. All the figure of merits (FOMs) for the Octagonal cell topology are comparable to those of the state-of-the-art Si COOLMOS and are much better than the ROHM SiC MOSFET product [7]. In addition, simulations show that the oxide electric field for an Octagonal cell is much lower in comparison to other topologies [7]. The Linear, Hexagonal, and Octagonal cell topologies were used on 650 V SiC planar JBSFETs and reported in [8]. It is demonstrated that the Hexagonal cell topology provides the lowest specific ON-resistance (R on,sp ) but a higher gate-drain charge than Linear and Octagonal cells [8]. It indicates that the Hexagonal cell is suitable for powerswitching applications at a nominal frequency. However, for applications where a faster switching frequency is desired, such as reducing the size of power converters, the layout, such as the Octagonal (Oct) cell, is preferred, which tends to reduce the C gd at the cost of a higher R on [9].
In this work, a new cell topology named the dodecagonal (Dod) cell is proposed and compared with the Oct cell. Additionally, 650 V SiC power MOSFETs with the Dod and Oct cells have been designed, fabricated, and characterized. The static and dynamic performances of the fabricated 650 V SiC power MOSFETs are compared. Figure 1a shows the structure of the proposed Dod cell. A twelve-sided P + region with the ohmic contact on top is surrounded by six hexagonal poly-Si gate regions. The hexagonal gate regions are connected by poly-Si bars. The hexagonal JFET regions are placed inside gate regions. This Dod cell is applied to 650 V SiC power MOSFETs. The Oct cell is shown in Figure 1b. The cross-sectional views along the AA' direction for both Dod-cell and Oct-cell MOSFETs in this work are shown in Figure 1c. All MOSFETs have the same edge termination design and die size. The die size is 1.15 × 1.15 mm 2 , including the termination. The MOSFETs are fabricated on a 6-inch SiC wafer by X-Fab using the same SiC power MOSFET process. Figure 1d shows the cross-sectional SEM image of the fabricated Dod-cell MOSFETs. Due to the lateral straggle of Aluminum implantation in the P-well, the narrowest portion of the JFET region is reduced by 0.2 µm on each side. Five Dod-cell and five Oct-cell MOSFETs are packaged into open-cavity TO-247 packages for device characterization. Design parameters and experimental results are listed in Table 1.

Statistic Performance
The static performance, including the transfer, blocking, and output characteristics, is measured using a Keysight 1506A power semiconductor analyzer at room temperature. The results of one MOSFET from each cell type are shown in Figure 2. The threshold voltages (V th ) of all packaged MOSFETs are extracted using the linear extrapolation method from the transfer curves, as shown in Figure 2a. The average value and the standard derivation are shown in Table 1 Table 1. Therefore, the Dod cell does not degrade the blocking capability of the fabricated power MOSFET.
The output characteristics are shown in Figure 2c. A 2× higher drain current is observed on the fabricated Dod-cell MOSFET than on the Oct-cell MOSFET, which can be explained by the higher channel density and JFET density of the Dod cell. A higher channel density (total channel width in a unit cell/unit cell area) implies a larger total channel width and more current conduction within a specific die size. The channel densities for the Dod and Oct cells are calculated according to the geometry with the known cross section and cell pitch. The results are listed in Table 1. A 1.6× higher channel density is obtained for the Dod cell than the Oct cell. The higher channel density allows more current conduction for the fabricated Dod-cell MOSFET, resulting in a lower R on,sp than the fabricated Oct-cell MOSFET. The higher JFET density (JFET area/unit cell area) indicates a lower JFET region resistance, which contributes to the lower R on,sp [10]. The R on,sp of all the measured MOSFETs is calculated at a drain-source voltage (V D ) of 1.5 V. The mean values and standard derivations are listed in Table 1. A 2.2× reduction in the R on,sp is achieved for the Dod-cell MOSFET compared to the fabricated Oct-cell MOSFET.

Dynamic Performance
The C gd vs. drain voltage characteristics are shown in Figure 3. The C gd significantly affects the dynamic behavior of SiC MOSFETs due to the well-known Miller effect [11,12]. The C gd of a SiC planar MOSFET consists of the gate oxide capacitance on the top of the JFET region and the depletion capacitance of the JFET region and drift layer [13]. The results in Figure 3 show that the Dod-cell MOSFET has a higher C gd than the fabricated Oct-cell MOSFET under any drain bias. Because the Dod-cell and Oct-cell MOSFETs are fabricated following the same process flow, their gate oxide thickness, JFET doping profile, and drift-layer doping profile are the same. Thus, the difference in the C gd is caused by the different overlap areas of the gate and drain terminals (JFET region area) within a die. The calculated JFET density of the Dod cell is 1.6× higher than the Oct cell, which causes a higher C gd of the Dod-cell MOSFET. The C gd values at V D = 400 V are extracted for all the measured MOSFETs. Additionally, the HF-FOMs, which are defined as the product of R on and C gd , are calculated. The HF-FOM of the Dod-cell MOSFET is 2.1× smaller than the fabricated Oct-cell MOSFET, indicating a better high-frequency performance.
A Double-Pulse Test (DPT), which provides straightforward data on the switching behavior of SiC MOSFETs [14], is conducted to investigate the switching performance of the fabricated MOSFETs. The results are shown in Figure 4. During the turn-on process (Figure 4a), the Dod-cell MOSFET shows a shorter transient time (higher turn-on speed) than the fabricated Oct-cell MOSFET. The turn-on and turn-off dv/dt, switching energy, and total switching energy of the measured MOSFETs are extracted and listed in Table 1. The Dod-cell MOSFET has a higher dv/dt and less switching energy than the measured Oct-cell MOSFET during both the turn-on and turn-off processes. The Dod-cell MOSFET obtains a 29% reduction in total switching loss compared to the measured Oct-cell MOSFET.

Conclusions
A new cell topology named the Dod cell is proposed for SiC planar power MOSFETs. The Dod cell minimizes the JFET region area to achieve a low C gd and improves the channel density to reduce the R on,sp . A low C gd indicates a higher switching speed and makes the Dod-cell MOSFET an attractive candidate for high-frequency applications. The reduced R on,sp decreases the conduction loss. The Dod cell and a recently published Oct cell (designed with minimal JFET region area) have been used for the layout design of 650 V SiC power MOSFETs. The fabricated Dod-cell MOSFET achieves a higher C gd , but a 2.2× lower R on,sp , 2.1× smaller HF-FOM, and 29% less switching losses compared with the fabricated Oct-cell MOSFET.