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Keywords = HEMTs

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14 pages, 3433 KB  
Article
Defect Reduction in HEMT Epilayers on SiC Meta-Substrates
by Vin-Cent Su, Ting-Yu Wei, Meng-Hsin Chen, Chien-Te Ku and Guan-Shian Liu
Nanomaterials 2026, 16(3), 158; https://doi.org/10.3390/nano16030158 - 23 Jan 2026
Abstract
Dislocation reduction in gallium nitride (GaN) epitaxial layers remains a critical challenge for high-performance GaN-based electronic devices. In this study, GaN epitaxial growth on newly-developed 4H-Silicon Carbide (SiC) meta-substrates was systematically investigated to elucidate the role of surface pattern geometry in modulating dislocation [...] Read more.
Dislocation reduction in gallium nitride (GaN) epitaxial layers remains a critical challenge for high-performance GaN-based electronic devices. In this study, GaN epitaxial growth on newly-developed 4H-Silicon Carbide (SiC) meta-substrates was systematically investigated to elucidate the role of surface pattern geometry in modulating dislocation propagation. A series of truncated-hexagonal-pyramid meta-structures with a fixed array period and varying pattern ratios (R) were designed and fabricated to enable controlled tuning of the effective surface morphology. Atomic force microscopy confirmed comparable surface flatness for all samples after epitaxial growth. Cathodoluminescence analysis revealed a non-monotonic dependence of defect density on R, indicating the existence of an optimal pattern geometry. Among all configurations, the outstanding sample exhibited the lowest defect density, achieving a 54.96% reduction in threading dislocations (edge + mixed) compared with a planar reference. Cross-sectional transmission electron microscopy further confirmed a substantially reduced dislocation density and clear evidence of dislocation bending and termination near the meta-structured regions. These results demonstrate that geometry-engineered 4H-SiC meta-substrates provide an effective and scalable strategy for dislocation modulation in GaN epitaxy on SiC meta-substrates, offering a promising pathway toward advanced GaN power and RF devices. Full article
(This article belongs to the Special Issue Nonlinear Optics of Nanostructures and Metasurfaces)
15 pages, 9483 KB  
Article
Air Gaps Fabrication for Sub-100 nm GaN HEMTs by Novel SF6 Plasma Etching
by Simon St-Jacques, Mariyam Salmi, Oleh Fesiienko, Erwine Pargon, Ali Soltani, Bassem Salem and Hassan Maher
Microelectronics 2026, 2(1), 1; https://doi.org/10.3390/microelectronics2010001 - 13 Jan 2026
Viewed by 167
Abstract
We demonstrate the fabrication of air gaps in a PECVD SiN interlayer through lateral recess by employing two consecutive plasma etch steps on an AlN/SiN/Al2O3 stack. This approach enables the preservation of sub-100 nm openings in Al2O3 [...] Read more.
We demonstrate the fabrication of air gaps in a PECVD SiN interlayer through lateral recess by employing two consecutive plasma etch steps on an AlN/SiN/Al2O3 stack. This approach enables the preservation of sub-100 nm openings in Al2O3, offering a potential optimization for the GaN-HEMT gate stack in RF applications while retaining low gate foot dimensions. A low-power, SF6-based plasma etch is introduced, and time-dependent etch profiles reveal the formation of a skirt-like profile. The process exhibits excellent selectivity between SiN and Al2O3 etch rates. Furthermore, low-power SF6 plasma produces a small self-bias voltage, and surface fluorine contamination which can subsequently be eliminated by annealing. Full article
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17 pages, 5627 KB  
Article
Thermal Management with AlN Passivation in AlGaN/GaN HEMTs with an Air Gap Gate for Improved RF Performance: A Simulation Study
by Young-Hyun Won, Tae-Sung Kim, Jae-Hun Lee, Chae-Yun Lim, Byoung-Gue Min, Dong-Min Kang and Hyun-Seok Kim
Micromachines 2026, 17(1), 92; https://doi.org/10.3390/mi17010092 - 10 Jan 2026
Viewed by 287
Abstract
This study introduces an air gap gate with AlN passivation to enhance the radio frequency (RF) performance of AlGaN/GaN high-electron-mobility transistors (HEMTs) while addressing thermal challenges. The air gap gate improves RF performance by reducing gate capacitance, resulting in a 23.9% increase in [...] Read more.
This study introduces an air gap gate with AlN passivation to enhance the radio frequency (RF) performance of AlGaN/GaN high-electron-mobility transistors (HEMTs) while addressing thermal challenges. The air gap gate improves RF performance by reducing gate capacitance, resulting in a 23.9% increase in cutoff frequency (35.82 GHz) and enhancing saturation drain current and maximum transconductance by 3.7% and 10.27%, respectively, compared to a 0.15 μm planar gate baseline. However, reduced heat dissipation degrades thermal performance, as reflected in higher thermal resistance and temperature gradients. Incorporating high thermal conductivity AlN passivation mitigates these drawbacks, lowering operating temperatures and improving heat distribution, while maintaining a 17.5% cutoff frequency improvement over the baseline. These results demonstrate that the air gap gate with AlN passivation provides an effective strategy for achieving reliable, high-performance AlGaN/GaN HEMTs under high-frequency and high-power operations. Full article
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18 pages, 3932 KB  
Article
Drain-Voltage Assessment-Based RC Snubber Design Approach for GaN HEMT Flyback Converters
by Byeong-Je Park, Chae-Jeong Hwang, Geon-Ung Park, Min-Su Park and Daeyong Shim
Electronics 2026, 15(2), 271; https://doi.org/10.3390/electronics15020271 - 7 Jan 2026
Viewed by 233
Abstract
Conventional RC snubber design relies on oscillation frequency-based estimation, which is often influenced by uncontrolled parasitic elements and can therefore limit the accuracy of surge voltage prediction in GaN HEMT flyback converters. To overcome this limitation, a drain-voltage assessment-based design approach is introduced, [...] Read more.
Conventional RC snubber design relies on oscillation frequency-based estimation, which is often influenced by uncontrolled parasitic elements and can therefore limit the accuracy of surge voltage prediction in GaN HEMT flyback converters. To overcome this limitation, a drain-voltage assessment-based design approach is introduced, in which the snubber parameters are extracted directly from the measured voltage characteristics during the turn off transition. This method allows the surge voltage to be modeled more precisely and enables the snubber capacitance to be selected without unnecessary oversizing. Simulation results using the GaN Systems GS66516T device show that the proposed approach reduces the total power loss by 27.67% and 21.84% relative to two empirical design methods and achieves up to 53.64% lower loss compared with other RC combinations in the explored design space. The method suppresses the surge voltage from 877 V to 556 V, which closely aligns with the design target of 550 V, whereas the empirical methods result in maximum voltages of 637 V and 603 V. Finally, the thermal feasibility of the snubber resistor is analytically assessed, indicating that the estimated temperature rise remains within the safe operating range of commercial components. Full article
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13 pages, 3784 KB  
Article
Design and Implementation of an L-Band 400 W Continuous-Wave GaN Power Amplifier
by Xiaodong Jing, Hailong Wang, Fei You, Xiaofan Zhang and Kuo Ma
Electronics 2026, 15(1), 203; https://doi.org/10.3390/electronics15010203 - 1 Jan 2026
Viewed by 212
Abstract
Based on a large-signal chip model, this paper designs and implements an L-band broadband continuous-wave 400 W high-efficiency power amplifier fabricated using 0.5 μm GaN High Electron Mobility Transistor (HEMT) technology. The input-matching circuit employs a hybrid structure combining a lumped-element pre-matching network [...] Read more.
Based on a large-signal chip model, this paper designs and implements an L-band broadband continuous-wave 400 W high-efficiency power amplifier fabricated using 0.5 μm GaN High Electron Mobility Transistor (HEMT) technology. The input-matching circuit employs a hybrid structure combining a lumped-element pre-matching network and a multi-section microstrip capacitor network to achieve impedance matching with a 50 Ω port. The output-matching circuit uses a multi-segment microstrip structure to meet the impedance requirements of the continuous mode, thereby achieving broadband impedance matching. In addition, in the circuit implementation, by optimizing the placement of the blocking capacitor, the current flowing through it is minimized to a low level, enhancing the circuit’s high-power handling capability under continuous-wave operation. Additionally, the power amplifier’s reliability lifetime was calculated based on simulation results of the operating temperature of the GaN amplifier chip. Measurement results demonstrate that across a wide operating bandwidth within the L-band, the output power exceeds 400 W with a drain efficiency greater than 70%. The estimated reliability lifetime (MTTF) of the power amplifier is 8.1 × 107 h. Full article
(This article belongs to the Special Issue RF/Microwave Integrated Circuits Design and Application)
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6 pages, 1993 KB  
Proceeding Paper
Comparative Study of T-Gate Structures in Nano-Channel GaN-on-SiC High Electron Mobility Transistors
by Yu-Chen Liu, Dian-Ying Wu, Hung-Cheng Hsu, I-Hsuan Wang and Meng-Chyi Wu
Eng. Proc. 2025, 120(1), 8; https://doi.org/10.3390/engproc2025120008 - 25 Dec 2025
Viewed by 338
Abstract
We investigated the radio frequency (RF) performance of AlGaN/GaN high electron mobility transistors (HEMTs) fabricated on silicon carbide substrates, featuring two distinct T-shaped gate structures. A comparative analysis between a silicon nitride (SiNx)-passivated T-gate and a floating T-gate design reveals significant [...] Read more.
We investigated the radio frequency (RF) performance of AlGaN/GaN high electron mobility transistors (HEMTs) fabricated on silicon carbide substrates, featuring two distinct T-shaped gate structures. A comparative analysis between a silicon nitride (SiNx)-passivated T-gate and a floating T-gate design reveals significant differences in parasitic capacitance and high-frequency behavior. The floating gate structure effectively reduces fringe capacitance, resulting in improved cut-off frequency (fT) and maximum oscillation frequency (fmax), achieving fT = 82.7 GHz and fmax = 80.2 GHz, respectively. These enhancements underscore the critical importance of optimizing gate structures to advance GaN-based HEMTs for high-speed and high-power applications. The findings provide valuable insights for the design of future RF and millimeter-wave (mm-wave) devices. Full article
(This article belongs to the Proceedings of 8th International Conference on Knowledge Innovation and Invention)
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13 pages, 6272 KB  
Article
A Design of 1.2–3.6 GHz Power Amplifier Based on Filters of Negative Feedback Network
by Zhenghao Yang, Chucai Cai, Zhengxian Meng, Zhiyong Ding, Quanbin Fu, Xiaogang Wang and Zhiqun Cheng
Electronics 2025, 14(24), 4944; https://doi.org/10.3390/electronics14244944 - 17 Dec 2025
Viewed by 327
Abstract
This work proposes a broadband, high-efficiency extended continuous class-F (ECCF) power amplifier (PA) with a negative-feedback network structure. Compared with the traditional direct cascade connection of a PA and a filter, the design introduces a novel negative feedback filter structure. The transistor and [...] Read more.
This work proposes a broadband, high-efficiency extended continuous class-F (ECCF) power amplifier (PA) with a negative-feedback network structure. Compared with the traditional direct cascade connection of a PA and a filter, the design introduces a novel negative feedback filter structure. The transistor and filter synthesis network co-design method aims to compensate for the gain and efficiency drop of this PA in both high and low frequency bands, resulting in relatively flat gain and efficiency performance over a wide band. Consequently, there is a need to enhance the security and efficiency of wireless communication systems. This work verifies the proposed method using a designed and fabricated 10 W GaN HEMT device. The measured data reveal that the designed PA achieves 100% relative bandwidth from 1.2 GHz to 3.6 GHz, with a drain efficiency (DE) of 59.5~67.4%, an output power of 38.8~41.8 dBm, and a large signal gain of 8.8~11.8 dB. Full article
(This article belongs to the Section Microwave and Wireless Communications)
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13 pages, 3982 KB  
Article
High Reliability and Breakdown Voltage of GaN HEMTs on Free-Standing GaN Substrates
by Shiming Li, Mei Wu, Ling Yang, Hao Lu, Bin Hou, Meng Zhang, Xiaohua Ma and Yue Hao
Nanomaterials 2025, 15(24), 1882; https://doi.org/10.3390/nano15241882 - 15 Dec 2025
Viewed by 460
Abstract
Gallium nitride (GaN)-based high electron mobility transistors (HEMTs) are pivotal for next-generation power-switching applications, but their reliability under high electric fields remains constrained by lattice mismatches and high dislocation densities in heterogeneous substrates. Herein, we systematically investigate the electrical performance and reliability of [...] Read more.
Gallium nitride (GaN)-based high electron mobility transistors (HEMTs) are pivotal for next-generation power-switching applications, but their reliability under high electric fields remains constrained by lattice mismatches and high dislocation densities in heterogeneous substrates. Herein, we systematically investigate the electrical performance and reliability of GaN-on-GaN HEMTs in comparison to conventional GaN-on-SiC HEMTs via DC characterization, reverse gate step stress, off-state drain step stress, and on-state electrical stress tests. Notably, the homogeneous epitaxial structure of GaN-on-GaN devices reduces dislocation density by 83.3% and minimizes initial tensile stress, which is obtained through HRXRD and Raman spectroscopy. The GaN-on-GaN HEMTs exhibit a record BFOM of 950 MW/cm2, enabled by a low specific on-resistance (RON-SP) of 0.6 mΩ·cm2 and a high breakdown voltage (BV) of 755 V. They withstand gate voltages up to −200 V and drain voltages beyond 200 V without significant degradation, whereas GaN-on-SiC HEMTs fail at −95 V (reverse gate stress) and 150 V (off-state drain stress). The reduced dislocation density suppresses leakage channels and defect-induced degradation, as confirmed by post-stress Schottky/transfer characteristics and Frenkel–Poole emission analysis. These findings establish GaN-on-GaN technology as a transformative solution for power electronics, offering a unique combination of high efficiency and long-term stability for demanding high-voltage applications. Full article
(This article belongs to the Special Issue Electro-Thermal Transport in Nanometer-Scale Semiconductor Devices)
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10 pages, 3795 KB  
Article
A Methodology for Designing High-Efficiency Power Amplifiers Using Simple Microstrip Harmonic Tuning Circuits
by Guohua Zhang and Shaohua Zhou
Electronics 2025, 14(23), 4767; https://doi.org/10.3390/electronics14234767 - 4 Dec 2025
Viewed by 361
Abstract
This paper presents a simple effective methodology for designing high-efficiency power amplifiers (PAs) utilizing a compact microstrip harmonic-tuned load network. The proposed approach employs a combination of a two-section transformer and three shunt-connected stubs, reducing component count relative to conventional harmonic-tuned circuits. The [...] Read more.
This paper presents a simple effective methodology for designing high-efficiency power amplifiers (PAs) utilizing a compact microstrip harmonic-tuned load network. The proposed approach employs a combination of a two-section transformer and three shunt-connected stubs, reducing component count relative to conventional harmonic-tuned circuits. The novel load network achieves optimized load impedances at the fundamental, second, and third harmonics while accounting for parasitic effects of packaged transistors. For experimental validation, an inverse Class-F (Class-F−1) PA is designed and fabricated using a Cree GaN HEMT (model CGH40010F) operating at 2.5 GHz. The measured results demonstrate a peak power-added efficiency (PAE) of 79.8% with a saturated output power (Psat) of 40.2 dBm. Full article
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11 pages, 16090 KB  
Article
Impact of OFF-State Stress on Dynamic RON of On-Wafer 100 V p-GaN HEMTs, Studied by Emulating Monolithically Integrated Half-Bridge Operation
by Lorenzo Modica, Nicolò Zagni, Marcello Cioni, Giacomo Cappellini, Giovanni Giorgino, Ferdinando Iucolano, Giovanni Verzellesi and Alessandro Chini
Electronics 2025, 14(23), 4756; https://doi.org/10.3390/electronics14234756 - 3 Dec 2025
Viewed by 373
Abstract
This paper presents the electrical characterization of the on-resistance (RON) of on-wafer 100 V p-GaN power High-Electron-Mobility Transistors (HEMTs). This study assesses device degradation in the context of a monolithically integrated half-bridge circuit, considering both Low-Side (LS) and High-Side (HS) [...] Read more.
This paper presents the electrical characterization of the on-resistance (RON) of on-wafer 100 V p-GaN power High-Electron-Mobility Transistors (HEMTs). This study assesses device degradation in the context of a monolithically integrated half-bridge circuit, considering both Low-Side (LS) and High-Side (HS) configurations. Since on-wafer samples have been characterized, a custom experimental setup was developed to emulate stress conditions experienced by the devices in the half-bridge circuit. A periodic signal (T = 10 µs, TON = 2 µs) switching from the OFF to the ON state was applied for a cumulative duration of 1000 s. Different OFF-state stress conditions were applied by varying the gate-source OFF voltage (VGS,OFF) between 0 V and −10 V. The on-resistance exhibited a positive drift over time for devices in either the LS or the HS configuration, with the latter showing a more pronounced degradation. Measurements at higher temperatures (up to 90 °C) were carried out to characterize the dynamics of the physical mechanism behind the degradation effects. We identified hole emission from C-related acceptor traps in the buffer as the main mechanism for the observed degradation, which is present in both the HS and the LS configurations. The additional degradation observed in the HS case was attributed to the back-gating effect, stemming from the non-null body-to-source voltage. Furthermore, we found that a more negative VGS,OFF further increases RON degradation, likely related to the higher electric field near the gate contact, which enhances hole emission from C-related acceptor traps. Full article
(This article belongs to the Section Semiconductor Devices)
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13 pages, 1888 KB  
Article
Exploring the Effects of Barrier Thickness and Channel Length on Performance of AlGaN/GaN HEMT Sensors Using Off-the-Shelf AlGaN/GaN Wafers
by Mohamed Taha Amen, Duy Phu Tran, Asad Feroze, Edward Cheah and Benjamin Thierry
Appl. Sci. 2025, 15(23), 12751; https://doi.org/10.3390/app152312751 - 2 Dec 2025
Viewed by 408
Abstract
AlGaN/GaN heterostructure high electron mobility transistors (HEMTs) have exceptional characteristics, but the structure-function relationship remains to be experimentally fully studied. This study presents a systematic experimental investigation of the synergistic effects of AlGaN barrier thickness and channel length on device performance, a critical [...] Read more.
AlGaN/GaN heterostructure high electron mobility transistors (HEMTs) have exceptional characteristics, but the structure-function relationship remains to be experimentally fully studied. This study presents a systematic experimental investigation of the synergistic effects of AlGaN barrier thickness and channel length on device performance, a critical gap in the literature, which is often dominated by simulation studies. We experimentally investigated how barrier thickness and channel length influence AlGaN/GaN FET performance. We observed that the transconductance increases with decreasing AlGaN barrier thickness for shorter channel lengths (15 and 50 µm) but showed the opposite trend for the longest channel length (100 µm). Meanwhile, the subthreshold swing was predominantly influenced by the barrier thickness, with thinner barriers generally yielding lower values. These results highlight the intricate interplay between barrier thickness and channel length, providing foundational insights into the design–performance relationship of AlGaN/GaN HEMTs and guiding the development of optimized sensors for different applications. Full article
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11 pages, 3556 KB  
Article
The Impact of Load-Dump Stress on p-GaN HEMTs Under Floating Gate Condition
by Zhipeng Shen, Yijun Shi, Lijuan Wu, Liang He, Xinghuan Chen, Yuan Chen, Dongsheng Zhao, Jiahong He, Gengbin Zhu, Huangtao Zeng and Guoguang Lu
Micromachines 2025, 16(12), 1369; https://doi.org/10.3390/mi16121369 - 30 Nov 2025
Viewed by 440
Abstract
This work investigates the impact of load-dump stress on p-GaN HEMTs under floating gate condition. The experiments show that preconditioning the device with a small load-dump stress (150 V, @td = 100 ms and tr = 8 ms) enhances its [...] Read more.
This work investigates the impact of load-dump stress on p-GaN HEMTs under floating gate condition. The experiments show that preconditioning the device with a small load-dump stress (150 V, @td = 100 ms and tr = 8 ms) enhances its robustness against a larger stress (190 V, @td = 100 ms and tr = 8 ms). If a large load-dump stress (≥160 V, @td = 100 ms and tr = 8 ms) is applied directly to the device’s drain, the device will burn out. This occurs because the rapidly changing drain voltage during a load-dump event can generate a capacitive coupling current, leading to transient positive charge accumulation in the gate region. Consequently, the channel under the gate is turned on, allowing a large current to flow through it. The coexistence of high current and high voltage leads to substantial Joule heating within the device, resulting in eventual burnout. When a small load-dump stress is initially applied, the resulting charging of electron traps in the gate region increases the threshold voltage. As a result, the device can withstand a larger load-dump stress before the channel turns on, which explains the device’s enhanced robustness. This work clarifies the failure threshold of p-GaN HEMTs under the load-dump stress, providing key support for improving the devices’ reliability in the practical applications. It can provide a basis for adding necessary protective measures in device circuit design, and clarify the triggering voltage threshold of protective measures to ensure that they can effectively avoid device damage due to the load-dump stress. Full article
(This article belongs to the Special Issue Power Semiconductor Devices and Applications, 3rd Edition)
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10 pages, 2350 KB  
Article
Design of Dual Continuous-Mode Class-J Power Amplifiers with Harmonic Matching Networks for X and Ku Bands
by Yang Yuan, Xuesong Zhao, Jingxin Fan and Zhongjun Yu
Micromachines 2025, 16(12), 1362; https://doi.org/10.3390/mi16121362 - 29 Nov 2025
Viewed by 323
Abstract
In this article, two wideband high-efficiency Class-J power amplifiers operating in X and Ku bands, respectively, are designed based on continuous mode. The optimal impedance regions of the transistors are determined using harmonic load-pull techniques. An on-chip output matching network with second harmonic [...] Read more.
In this article, two wideband high-efficiency Class-J power amplifiers operating in X and Ku bands, respectively, are designed based on continuous mode. The optimal impedance regions of the transistors are determined using harmonic load-pull techniques. An on-chip output matching network with second harmonic control functionality is designed to achieve Class-J operation. To verify the feasibility of designed circuits, both power amplifiers are designed and fabricated using a 0.25 mm GaAs pseudomorphic high electron mobility transistor (pHEMT) process. The power amplifiers are both biased at 6 V/−1 V. The measured results show the X-band and Ku-band power amplifiers achieve peak saturated output powers of 31.2 dBm and 30.8 dBm, respectively. The power-added efficiencies (PAEs) of the two amplifiers within their operating bands reach up to 48% and 45.3%, respectively. Compact size and high efficiency make them suitable for integration into phased array transmit/receiver (T/R) modules. Full article
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17 pages, 14218 KB  
Article
An Improved Nonlinear Capacitance Model for GaN HEMTs Based on the Angelov Model
by Yuchen Miao, Qingyu Yuan, Chuangye Wang and Jiali Cheng
Micromachines 2025, 16(12), 1318; https://doi.org/10.3390/mi16121318 - 25 Nov 2025
Viewed by 2271
Abstract
To accurately model the nonlinear characteristics of the intrinsic capacitance of Gallium Nitride High Electron Mobility Transistors (GaN HEMTs), this paper proposes an improved nonlinear capacitance model based on the traditional Angelov model. The experiments employed GaN HEMTs fabricated by United Monolithic Semiconductors [...] Read more.
To accurately model the nonlinear characteristics of the intrinsic capacitance of Gallium Nitride High Electron Mobility Transistors (GaN HEMTs), this paper proposes an improved nonlinear capacitance model based on the traditional Angelov model. The experiments employed GaN HEMTs fabricated by United Monolithic Semiconductors (UMS) using the GH15-10 process. These devices feature a uniform gate length of 150 nm, with gate widths designed as 2 × 10 μm, 4 × 20 μm, 6 × 30 μm, and 8 × 40 μm, respectively (gate width is calculated as “number of gate fingers × unit gate width”). In this study, two types of devices with gate widths of 2 × 10 μm and 4 × 20 μm were selected to extract intrinsic capacitance parameters, which were then substituted into the traditional Angelov model and the proposed improved model, respectively. By comparing the coefficient of determination (R2) and Root Mean Square Error (RMSE) of the two models, it is found that the improved model has a significantly higher degree of agreement with the experimental measurement dates and is more suitable for the quantitative characterization of the nonlinear capacitance characteristics of GaN HEMTs. This research provides support for the accurate application of device models in the design of high-frequency circuits in subsequent studies. Full article
(This article belongs to the Section D1: Semiconductor Devices)
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13 pages, 624 KB  
Review
Immunology and Biologics in the Treatment of Allergic Bronchopulmonary Aspergillosis in Cystic Fibrosis
by Esther S. Kim and Janice Wang
J. Respir. 2025, 5(4), 19; https://doi.org/10.3390/jor5040019 - 14 Nov 2025
Viewed by 1302
Abstract
Allergic bronchopulmonary aspergillosis (ABPA) is mediated by hypersensitivity reactions to Aspergillus fumigatus, which is ubiquitous in the environment. People with Cystic Fibrosis (PwCF) are at an increased risk for developing ABPA, which can lead to frequent pulmonary exacerbations and progressive decline in [...] Read more.
Allergic bronchopulmonary aspergillosis (ABPA) is mediated by hypersensitivity reactions to Aspergillus fumigatus, which is ubiquitous in the environment. People with Cystic Fibrosis (PwCF) are at an increased risk for developing ABPA, which can lead to frequent pulmonary exacerbations and progressive decline in lung function. In the age of highly effective modulator therapies (HEMT), PwCF have improved clinical outcomes and overall life expectancy, but they continue to suffer from comorbidities such as ABPA, which may be difficult to diagnose and treat. Establishing the diagnosis of ABPA in PwCF requires high clinical suspicion due to similarities in symptoms with the underlying disease. First-line treatment involves corticosteroids and anti-fungals, which have multiple side effects and drug interactions, especially with HEMT. Given this challenge, biologics have gained attention as potential agents directly targeting the Th-2 inflammatory pathway of ABPA with good tolerability and without significant drug interactions with HEMT. In this review, we discuss the diagnostic process and management of ABPA in PwCF, including a brief overview of the current literature on biologic agents. Full article
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