Design of Dual Continuous-Mode Class-J Power Amplifiers with Harmonic Matching Networks for X and Ku Bands

Abstract

In this article, two wideband high-efficiency Class-J power amplifiers operating in X and Ku bands, respectively, are designed based on continuous mode. The optimal impedance regions of the transistors are determined using harmonic load-pull techniques. An on-chip output matching network with second harmonic control functionality is designed to achieve Class-J operation. To verify the feasibility of designed circuits, both power amplifiers are designed and fabricated using a 0.25 mm GaAs pseudomorphic high electron mobility transistor (pHEMT) process. The power amplifiers are both biased at 6 V/−1 V. The measured results show the X-band and Ku-band power amplifiers achieve peak saturated output powers of 31.2 dBm and 30.8 dBm, respectively. The power-added efficiencies (PAEs) of the two amplifiers within their operating bands reach up to 48% and 45.3%, respectively. Compact size and high efficiency make them suitable for integration into phased array transmit/receiver (T/R) modules.

1. Introduction

Modern active phased arrays demand multifunctionality and lightweight design [1]. Accordingly, the widebanding and miniaturization of transmit/receiver (T/R) modules become imperative. Among these requirements, thermal design is a core factor restricting the miniaturization of T/R modules, while the efficiency of T/R modules is primarily determined by their internal power amplifiers [2]. However, the widebanding of power amplifiers leads to efficiency degradation. Therefore, designing wideband high-efficiency power amplifiers is key to realizing the multifunctionality and lightweight design of phased arrays.

Based on waveform engineering analysis, continuous-mode power amplifiers maintain high efficiency over a wide bandwidth, making them ideal for designing saturated power amplifiers in T/R modules [3]. A waveform-engineered sequential load-modulated balanced amplifier, which employs continuous Class-F⁻¹ and Class-J operations, achieves a saturated drain efficiency of 60.2–68.3% across 1.80–2.75 GHz [4]. An ultrawideband power amplifier utilizing a novel multi-branch matching network and extended continuous Class-B/J modes delivers a drain efficiency of 56–70% over 0.4–3.8 GHz, with a relative bandwidth of 162% [5]. The power amplifiers reported in [4,5] employ off-chip high-Q output matching networks (OMNs), achieving high efficiency over a wide bandwidth. However, their large overall footprint renders them incompatible with the integration into transmit/receive (T/R) modules. In [6], an X-band Class-J power amplifier based on active load modulation is implemented in a 0.25 mm GaAs pseudomorphic high electron mobility transistor (pHEMT) process, achieving a peak power-added efficiency (PAE) of 50% over 9.1~10.8 GHz with a die area of 1.89 × 1.69 mm². Ref. [7] demonstrates a broadband power amplifier fabricated in a 0.25 μm GaN HEMT process, realizing a PAE of 36.3–47% across 2–6 GHz.

In this article, two wideband high-efficiency Class-J power amplifiers operating in the X band and Ku band, respectively, are designed and fabricated using a 0.25 mm GaAs pHEMT process. On-chip second harmonic control network is integrated into the OMN to realize the Class-J operation. The measured results show that both power amplifiers exhibit high PAE within their respective bandwidths. Furthermore, their compact footprint renders them suitable for integration with miniaturized T/R modules.

2. Continuous-Mode Class-J Power Amplifier

Continuous-mode power amplifiers expand the solution space for the optimal load impedance, thereby enhancing the design flexibility of the output matching network and allowing the power amplifier to maintain high drain efficiency over a broad frequency band [8].

Taking the continuous Class-J power amplifier as an example, the drain-source current i_{d_J} and voltage v_{d_J} of the transistor can be given by Equations (1) and (2), respectively [9].

$$i_{d\_J}={\displaystyle \frac{I_m}{\pi }}+{\displaystyle \frac{I_m}{2}}\cos \theta +{\displaystyle \frac{2I_m}{3\pi }}\cos 2\theta -{\displaystyle \frac{2I_m}{15\pi }}\cos 4\theta +\dots$$

(1)

$$\begin{array}{l}{v}_{d\_J}=V_D\left(1-\cos \theta \right)\left(1-\alpha \sin \theta \right)\\ =V_D\left[1-\sqrt{{\alpha }^2+1}\sin \left(\theta +\arctan {\displaystyle \frac{1}{\alpha }}\right)+{\displaystyle \frac{\alpha }{2}}\sin 2\theta \right]\end{array}$$

(2)

Here, $\alpha \in [-1, 1]$, I_m and V_D are the peak current and the bias voltage, respectively. The power amplifier operates in Class-J mode for all values of a, with the exception of a = 0 (Class-B). Based on Equations (1) and (2), the impedance conditions for continuous Class-J power amplifiers are

$$Z_{n\_J}=\left\{\begin{array}{c}\begin{array}{c}{\displaystyle \frac{2V_D}{I_m}}\left(1+j\alpha \right), n=1\end{array}\\ \begin{array}{c}-j{\displaystyle \frac{3\pi V_D}{4I_m}}\alpha , n=2\end{array}\\ \hspace{1em}\begin{array}{cc}0, & n>2\end{array}\end{array}\right.$$

(3)

where n is the harmonic order. Equation (3) demonstrates that different values of a produce distinct impedance traces on the Smith chart, as shown in Figure 1, which facilitates broadband matching of the amplifier. Furthermore, as the additional impedance introduced at the second-harmonic frequency is purely reactive, it theoretically imposes no degradation on the amplifier efficiency. Figure 2 shows the waveforms of v_{d_J} and i_{d_J} for different values of a. For the Class-J amplifiers, it can be observed that affected by the second harmonic, the waveform of v_{d_J} shifts left or right under different values of a (relative to a = 0) [10].

3. Harmonic Load Pull

To achieve the design of a continuous-mode broadband high-efficiency power amplifier, in addition to performing fundamental load pull, it is also necessary to determine the range of the second harmonic impedance. The selected transistor based on a 0.25 mm GaAs pHEMT process features a maximum drain-source voltage of 18 V. As can be seen from Figure 2, in continuous-mode operation, the peak voltage of v_ds exceeds the drain bias voltage V_D by approximately 2.8 times. To avoid transistor breakdown caused by excessive peak voltage, V_D is ultimately set to 6 V.

Under a 6 V/−1 V bias condition, fundamental load pull is conducted on the output-stage transistors of the X-band and Ku-band power amplifiers. The resulting optimum impedances serve as the initial values for subsequent iterations. To simulate practical losses, the real part of the second harmonic impedance is fixed at 5 W, while a parameter sweep is performed over its imaginary part (Imload₂). Figure 3 plots the saturated output power (P_sat) and PAE of the X-band transistor versus Imload₂. The results reveal a sharp degradation in both P_sat and PAE within the Imload₂ range of −j24 W to j27 W.

Based on the second harmonic parameter sweep, appropriate harmonic load values are selected. After multiple iterations of fundamental load-pull and harmonic impedance sweeps, the final fundamental and harmonic impedance values are obtained.

Table 1. The results of source pull and harmonic load pull for the output-stage transistors of the X-band and Ku-band power amplifiers.

Frequency	8 GHz	10 GHz	12 GHz
Zs	(11.9 + j21.5) Ω	(5.2 + j15) Ω	(5.8 + j14.3) Ω
Zf0	(18.5 + j11.6) Ω	(14.6 + j9.1) Ω	(10.1 + j10.4) Ω
Z2f0	>j30 W	>j30 W	>j30 W
Frequency	13 GHz	15 GHz	17 GHz
Zs	(7.3 + j10.8) Ω	(6.3 + j2.4) Ω	(3.1 + j1.7) Ω
Zf0	(8.9 + j9.5) Ω	(7.8 + j8.1) Ω	(6.1 + j8.5) Ω
Z2f0	>j30 W	>j30 W	>j30 W

presents the results of source pull and harmonic load pull for the output-stage transistors of the X-band and Ku-band power amplifiers.

4. Design of the Harmonic Matching Network

As shown in Figure 1 and Table 1, the second harmonic load is purely reactive. Consequently, the output matching network must achieve a dual function: transforming the 50 Ω source impedance to the fundamental impedance Z_f0, while concurrently providing the required harmonic impedance Z_2f0. Although the off-chip branch-line structure can readily implement such harmonic matching, its large circuit area makes it unsuitable for integration in phased array T/R modules [11]. Fortunately, advances in semiconductor technology now permit the on-chip integration of harmonic control networks. While this approach may incur a slight efficiency penalty compared to off-chip, high-Q matching circuits, the significantly reduced amplifier area facilitates integration within T/R modules. Figure 4 shows the schematic diagram of the designed impedance matching network with a second harmonic control function.

In Figure 4, L_p and C_p resonate at 2f₀ to realize second harmonic short-circuiting, whereas at the fundamental frequency, they are equivalent to a shunt grounded capacitor C_eq. Equation (4) presents the relationship between C_p and C_eq. L_s is employed to tune Imload₂ to meet the requirements of Z_2f0 specified in Table 1. L₁, C₁, C₂, C_eq, and L_s form a fifth-order matching network, achieving fundamental impedance matching for both the X and Ku bands. The drain bias inductor L_d1 is placed before the series resonant network; to avoid affecting the second harmonic, it has a large inductance value and does not participate in impedance matching.

$$C_p={\displaystyle \frac{3}{4}}{C}_{eq}$$

(4)

Figure 5 presents the simulated impedance traces of the output matching networks (OMNs) for the X band and Ku band. The highest efficiency and output power of the output-stage transistor are achieved when its second harmonic impedance is tuned to lie within the green region. Combined with Table 1, it can be seen that at both the frequency bands, the designed harmonic matching network can not only meet the second harmonic impedance control requirements but also satisfy the fundamental load matching requirements.

5. Design of the X and Ku Bands Class-J Power Amplifiers

After completing the output impedance matching, the driver stages of the X-band and Ku-band amplifiers are designed. Figure 6 presents the schematic diagrams of the interstage and input matching networks, where L_d and L_g serve as the drain and gate bias lines, respectively.

Table 2. The results of source pull and load pull for the driver transistors of the X band and Ku band.

Frequency	8 GHz	10 GHz	12 GHz
Zs	(17.4 + j16) Ω	(15.2 + j14.5) Ω	(13.9 + j12.1) Ω
ZL	(31.3 + j28.5) Ω	(29.5 + j26) Ω	(28.6 + j23) Ω
Frequency	13 GHz	17 GHz	15 GHz
Zs	(2.4 + j4.6) Ω	(2 + j5.2) Ω	(2 + j4.3) Ω
ZL	(9.3 + j14.6) Ω	(7.1 + j12) Ω	(3.9 + j13) Ω

shows the source-pull and load-pull results of the driver transistor. Combined with Z_s of the output transistors in Table 1, the component values are optimized.

Figure 7 shows the optimized schematic diagrams of the proposed X-band and Ku-band power amplifiers. The optimized component values are provided in

Table 3. The optimized component values shown in Figure 6.

Components	Values	Components	Values
L1	10 mm × 1500 μm	C12	0.52 pF
L2	10 mm × 340 μm	Lg1	10 mm × 1550 μm
L3	10 mm × 300 μm	Lg2	10 mm × 1400 μm
L4	15 mm × 400 μm	Lg3	10 mm × 900 μm
L5	15 mm × 300 μm	Lg4	10 mm × 1000 μm
L6	10 mm × 1800 μm	Ld1	15 mm × 1350 μm
L7	10 mm × 1050 μm	Ld2	30 mm × 1600 μm
L8	10 mm × 250 μm	Ld3	15 mm × 650 μm
L9	10 mm × 800 μm	Ld4	30 mm × 1100 μm
C1	0.67 pF	Ls1	20 mm × 450 μm
C2	6.10 pF	Ls2	30 mm × 400 μm
C3	0.52 pF	Lp1	10 mm × 160 μm
C4	0.62 pF	Lp2	30 mm × 120 μm
C5	1.01 pF	Cp1	0.39 pF
C6	0.68 pF	Cp2	0.35 pF
C7	2.30 pF	M1	6 × 100 μm
C8	0.19 pF	M2	10 × 150 μm
C9	0.52 pF	M3	8 × 200 μm
C10	0.56 pF	M4	12 × 200 μm
C11	0.83 pF

. Among them, some components are omitted as their minimal contribution to matching. All inductors are implemented using microstrip lines. Figure 8 presents the output-stage drain-source voltage and current waveforms of the amplifiers operating in the X and Ku bands. It can be observed that affected by the second harmonic, the peaks of the drain voltage all shift to the left, which is consistent with the characteristics of Class-J power amplifiers.

6. Simulated and Measured Results

The two proposed continuous-mode power amplifiers are fabricated using a 0.25 mm GaAs pHEMT process. Figure 9 shows the microscope photographs of the two power amplifiers, with die areas of 2.75 mm × 1.2 mm and 2.2 mm × 1.2 mm, respectively. The S-parameters of the chips are measured using a Cascade Summit 1200 M probe station and a Keysight N5245A microwave network analyzer. Both chips undergo large-signal measurement after being eutectically bonded to a package with molybdenum-copper carriers, as shown in Figure 10. During the measurement, a heat sink is placed at the bottom to ensure efficient heat dissipation of the power amplifier chips.

Figure 11a presents the S-parameter simulated and measured results of proposed X-band power amplifier. It can be observed that the simulated results are in good agreement with the measured results. Within the frequency range of 8 GHz to 12 GHz, the power amplifier achieves an average small-signal gain of approximately 20 dB, and the measured input reflection coefficient is better than −8 dB. Figure 11b shows the large-signal characteristic simulated and measured results. Within the operating frequency band, the power amplifier delivers a saturated output power exceeding 30 dBm, with a PAE higher than 39% across the band and a maximum of 48.5%.

The simulated and measured results of the designed Ku-band power amplifier are shown in Figure 12. Over the frequency range of 12 GHz to 18 GHz, the power amplifier achieves an average small-signal gain of approximately 16.5 dB, and the measured input reflection coefficient is better than −6.3 dB. The measured saturated output power achieves an average of 30.8 dBm across the band and 29 dBm at the band edges. Meanwhile, the measured PAE within the band reaches a maximum of 45.3% and an average of 40.32%.

The detailed performance metrics of two fabricated power amplifiers are listed in Table 4 and compared with several similar GaAs-process-based power amplifier studies in the literature [12,13,14,15,16,17]. Compared with the power amplifiers in [12,13,16], the proposed design demonstrates a higher PAE under a comparable bandwidth. Although [14,15] achieve high efficiency by employing only fundamental load-pull techniques, they are narrowband. The well-engineered matching network in [17] enables excellent bandwidth but sacrifices PAE.

Table 4. Comparison with other similar research on power amplifiers in GaAs process.

Ref.	Technology	Frequency (GHz)	BW (%)	Psat * (dBm)	PAE * (%)	Area (mm2)
[12]	0.15-μm GaAs	7~11.5	48.7	33.8	43	3.6 × 1.8
[13]	0.25-μm GaAs	8~13	47.6	31	35	1 × 3.5
[14]	0.25-μm GaAs	8.5~11.5	30	35	49	3 × 1.8
[15]	0.25-μm GaAs	8.5~9.5	11.1	29.6	44.4	2 × 2
		15.5~16.5	6.3	30.1	38.4
[16]	0.25-μm GaAs	11.7~17.6	40.3	31	38.8	3.8 × 3.3
[17]	0.25-μm GaAs	6~18	100	40.5	29	5 × 3.6
This work	0.25-μm GaAs	8~12	40	31.2	48	2.75 × 1.2
		12~18	40	30.8	45.3	2.2 × 1.2

* maximum values.

Table 4. Comparison with other similar research on power amplifiers in GaAs process.

Ref.	Technology	Frequency (GHz)	BW (%)	Psat * (dBm)	PAE * (%)	Area (mm2)
[12]	0.15-μm GaAs	7~11.5	48.7	33.8	43	3.6 × 1.8
[13]	0.25-μm GaAs	8~13	47.6	31	35	1 × 3.5
[14]	0.25-μm GaAs	8.5~11.5	30	35	49	3 × 1.8
[15]	0.25-μm GaAs	8.5~9.5	11.1	29.6	44.4	2 × 2
		15.5~16.5	6.3	30.1	38.4
[16]	0.25-μm GaAs	11.7~17.6	40.3	31	38.8	3.8 × 3.3
[17]	0.25-μm GaAs	6~18	100	40.5	29	5 × 3.6
This work	0.25-μm GaAs	8~12	40	31.2	48	2.75 × 1.2
		12~18	40	30.8	45.3	2.2 × 1.2

* maximum values.

7. Conclusions

In this article, two wideband high-efficiency power amplifiers operating in the X and Ku bands, respectively, are designed and fabricated using a 0.25 µm-GaAs pHEMT process. A harmonic matching network is introduced in both power amplifiers, which extends the operating bandwidth without sacrificing efficiency. The proposed X-band power amplifier achieves a peak saturated output power of 31.2 dBm and a maximum PAE of 48%. The proposed Ku-band amplifier delivers a peak saturated output power of 30.8 dBm and a maximum PAE of 45.3%. Both chips feature a compact footprint, rendering them suitable for integration into miniaturized phased array T/R modules.