Search Results (549)

Offset voltage ($V_{\mathrm{OS}}$) is a critical parameter of sense amplifiers (SAs), determining both the read reliability and performance of SRAM. This paper proposes SC-DISBSA, a low-$V_{\mathrm{OS}}$ SA that combines self-adaptive calibration with dynamic body bias technology. Based on the linear relationship between the transfer gate voltage and $V_{\mathrm{OS}}$, a three-step self-adaptive calibration algorithm is established. Supported by the calibration control circuit, this approach quantitatively calibrates circuit mismatch while dynamic body bias further suppresses remaining variations. Under a 28 nm CMOS process, the $V_{\mathrm{OS}}$ standard deviation (${\sigma }_{\mathrm{OS}}$) of SC-DISBSA remains below 3.1 mV across a 0.7 V to 1.1 V supply range, representing reductions of 49.9% and 69.3% compared to the voltage-latch SA (VLSA) and current-latch SA (CLSA), respectively. At a typical case (TT/0.9 V/27 °C) with a BL differential ($\Delta V_{\mathrm{BL}}$) of $6{\sigma }_{\mathrm{OS}}$, SC-DISBSA reduces the required bitline discharge delay by 51.7% and improves average read sensing power by 24.9% compared to VLSA. By adopting an non-conventional bitline power supply strategy, SC-DISBSA decreases worst case (FF/1.1 V/125 °C) static power by 36.8% relative to VLSA. Additionally, it reduces gate area by 18.9%. Overall, SC-DISBSA effectively optimizes SRAM read latency and power efficiency. Full article

With the continuous advancement of display technology and advanced integrated circuits, oxide thin-film transistors (TFTs) have become core devices due to their high mobility, low leakage current and excellent large-area uniformity. To achieve low power consumption, high performance and high reliability, the introduction of high-k gate insulating layers is crucial. Among the numerous high-k materials, hafnium oxide (HfO₂) has attracted significant attention due to its excellent dielectric properties and good compatibility with CMOS processes. In this paper, uniform and dense HfO₂ films were successfully fabricated using the sol–gel method to serve as insulating layers for TFT devices. Through experimental analysis, 400 °C was determined to be the optimal annealing temperature. At this temperature, the effects of replacing SiO₂ with HfO₂ as the insulating layer, as well as the impact of reducing film thickness, on TFT devices were investigated. Ultimately, at an annealing temperature of 400 °C, an 85 nm-thick HfO₂ film achieved the highest on/off current ratio (I_on/off = 1.11 × 10⁶), the lowest subthreshold swing (SS = 0.53 V/dec), the lowest threshold voltage (Vth = −1.1 V) and the lowest off-current ratio (I_off = 2.5 × 10⁻¹² A). It was confirmed that replacing SiO₂ with HfO₂ as the insulating layer is a viable approach for reducing the volume of TFT devices. Full article

THz detectors based on CMOS technology have garnered widespread attention due to their potential in building compact, low-power, and scalable THz sensing and imaging systems. This paper proposes a 3.2 THz plasmonic wave detector fabricated in a standard 28 nm CMOS process, featuring an integrated on-chip antenna and NMOS transistor design. A response model was established, in which the NMOS input impedance at 3.2 THz extracted from the calibrated TCAD model was incorporated to evaluate the detector performance. At a modulation frequency of 2 kHz, the highest R_v of 830.1 V/W and the lowest NEP of 63.1 pW/Hz^1/2 were obtained. The predicted results show good agreement with the experimental measurements, confirming the effectiveness of the TCAD-assisted response modeling approach. Furthermore, demonstration experiments such as concealed object detection and high-resolution biological sample imaging further confirm the practical value of this CMOS detector in compact THz sensing and imaging systems. Full article

This paper presents a 2-GS/s voltage–time hybrid pipelined analog-to-digital converter (ADC) with a 14-bit digital output, implemented in a 28-nm CMOS process. To alleviate the gain–bandwidth–power trade-off in deeply scaled technologies, the proposed architecture employs a SHA-less front-end and a low-gain inverter-based push–pull RA for energy-efficient coarse quantization. The residue is then transferred to the time domain via a highly linear constant-current voltage-to-time converter (CC-VTC) and digitized by a four-channel time-interleaved gated-ring-oscillator (GRO) TDC. To recover dynamic linearity degraded by low-gain amplification and interleaving mismatches, a multiplier-less digital background calibration engine is implemented. Leveraging mean absolute value (MAV) statistics and dither-injected least-mean-squares (LMS) algorithms, it effectively compensates for inter-channel and interstage errors with minimal hardware overhead. The prototype occupies an active area of 0.16 mm². At 2 GS/s, the ADC achieves a Nyquist SNDR of 63.42 dB and an SFDR of 73.71 dB, corresponding to an ENOB of 10.24 bits. Consuming 86.9 mW from a 1-V supply, it achieves a Walden FoM of 35.9 fJ/conv.-step. Measurement results from multiple chips under a wide range of operating conditions verify the robustness of the proposed ADC. Full article

This paper presents a novel voltage differencing transconductance amplifier (VDTA)-based mixed-mode inverse filter capable of operating in voltage mode, transadmittance mode, transimpedance mode, and current mode using a single topology. The proposed configuration employs only three VDTAs with two resistors and three capacitors, offering low component count, high input/output impedance flexibility, and no requirement for component matching. It simultaneously realizes first-order inverse lowpass and highpass, as well as second-order inverse bandpass responses. A comprehensive non-ideal analysis, which includes the effects of VDTA parasitic impedances, determines the practical operating frequency range. The design is validated through PSPICE simulations using 0.18 μm CMOS technology, showing close alignment between theoretical predictions and simulation results, with cutoff frequencies of approximately 1.60 MHz and low power consumption of 0.972 mW. Further analyses confirm orthogonal tuning capability, acceptable temperature stability, and robustness against component tolerances. In a practical application, the proposed inverse filter is employed to implement a mixed-mode PID controller, which significantly improves transient response characteristics by reducing rise time, settling time, and steady-state error. These findings highlight the effectiveness and versatility of the proposed design for analog signal processing and control system applications. Full article

This paper describes two front-end architectures developed in a 28 nm CMOS process for the readout of pixel detectors in future high-energy physics (HEP) colliders and advanced X-ray imaging instrumentation. The front-end channels have been developed in the framework of the PiHEX project, funded by the Italian Ministry of University and Research. PiHEX aims to improve the state of the art of pixel readout chip technology in high-luminosity colliders and X-ray imagers in the next generation of free electron lasers (FELs) by developing, in 28 nm CMOS technology, the fundamental microelectronic building blocks for pixel readout chips. Such blocks, also implementing innovative circuit ideas, will enable, in future applications, the integration of large-scale readout chips, meeting a set of challenging requirements, such as high spatial resolution, high signal-to-noise ratio, very wide dynamic range and the capability to withstand unprecedented radiation levels. Two different front-end channels were designed, integrated into two prototype chips, and tested. One architecture, featuring a pixel size of 25 µm × 100 µm, was optimized for tracking applications in high-energy physics experiments, like the ones that take place at CERN in the high-luminosity upgrade of the Large Hadron Collider (LHC), while the second one, featuring a pixel size of 110 µm × 55 µm, was devised for X-ray imaging applications in FELs. Full article

Single-event effects (SEEs) present a significant challenge to the radiation reliability of integrated circuits. Conventional SEE analysis methods for single-photon avalanche diode (SPAD) devices primarily rely on Sentaurus Technology Computer-Aided Design (TCAD) numerical simulation, which is computationally intensive and time-consuming. In this study, we propose a generalized deep learning (DL) model, using a silicon-based SPAD device with a double-junction double-buried-layer (DJDB) structure fabricated in 180 nm CMOS process as the research subject. By incorporating key parameters that influence SEEs as model inputs, the proposed approach enables rapid prediction of critical parameter metrics, including transient current peaks and dark count rates. Experimental results show that the DL model achieves a prediction accuracy of 97.32% for transient current peaks and 99.87% for dark count rates, demonstrating extremely high prediction precision. To further validate the generalization capability of the proposed network, the model is applied to predict the detection performance of the DJDB-SPAD device. The prediction accuracies for four key performance parameters all exceed 97.5%, further confirming the accuracy and robustness of the developed model. Meanwhile, compared with the conventional Sentaurus TCAD simulation method, the proposed method achieves a 336-fold improvement in computational efficiency. Overall, this method realizes the dual advantages of high precision and high efficiency, which provides an efficient and accurate technical solution for the rapid characteristic analysis and reliability evaluation of SPAD devices under single-event effects (SEEs). Full article

This paper presents a low-noise analog front-end (AFE) integrated circuit (IC) circuit for capacitive micro-electromechanical system (MEMS) accelerometers that can be used for optical image stabilization (OIS) in various optical imaging systems. The AFE circuit design features a fully differential chopper stabilization technique that efficiently minimizes low-frequency 1/f noise and parasitic coupling. The AFE circuit chip is fabricated in a 0.18 $\mathsf{\mu }$m complementary metal-oxide-semiconductor (CMOS) technology and co-packaged with an x-axis capacitive MEMS accelerometer based on a silicon-on-glass (SOG) process. The SOG accelerometer has a footprint of 1000 $\mathsf{\mu }\mathrm{m}$ $\times$ 950 $\mathsf{\mu }\mathrm{m}$. The packaged system demonstrates a sensitivity of 342 mV/g and a nonlinearity of 1.1% between −1 g and +1 g, a dynamic range of 88 dB, and an equivalent noise floor of 14 $\mathsf{\mu }\mathrm{g}/\sqrt{\mathrm{H}\mathrm{z}}$. Full article

The growing demand for intelligent environmental monitoring is driving the advancement of high-performance, low-cost, and highly integrated gas sensors. Silicon-compatible semiconductor gas sensors provide a promising platform to achieve this goal by leveraging their compatibility with complementary metal–oxide semiconductor (CMOS) processes. The established mass-manufacturing capabilities of micro-electromechanical systems (MEMS) and the high sensitivity and signal amplification characteristics of field effect transistors (FETs) in recent years have made the development of next-generation sensing devices feasible. In this review, we systematically summarize the latest advances in silicon-compatible gas sensors, with a focus on MEMS and FET technologies. We discuss their sensing mechanisms and performance optimization strategies, and further highlight the evolution of gas sensor technology toward on-chip intelligent olfactory systems that integrate sensing, computing, and storage capabilities. Full article

Emerging non-volatile memories based on ferroelectric materials are currently under development to be integrated in the back-end-of-line of advanced complementary metal-oxide-semiconductor (CMOS) nodes. A life cycle assessment (LCA) over 16 impact categories has been carried out to compare planar (2D) and vertical (3D) integration strategies for the manufacturing of Hf_0.5Zr_0.5O₂-based ferroelectric capacitors on a 22 nm CMOS technology node. The LCA demonstrates that the 3D approach allows us to reduce the environmental impacts by up to 20% over several impact categories. The device isolation by a single chemical–mechanical polishing (CMP) step instead of the standard photolithography and plasma etching processes proved to be the main source of reduction on the overall environmental footprint. Full article

We report a versatile, CMOS-compatible fabrication module for sub-100 nm TiN and TaN pillar electrodes, a key building block for sandwich-type test structures. As a demonstration, the electrodes were integrated into carbon nanotube-based nonvolatile random-access memory (CRAM) test structures. High-resolution hydrogen silsesquioxane (HSQ) masks defined by electron beam lithography were transferred into TiN films using optimized Ar/Cl₂ inductively coupled plasma reactive ion etching. Optical emission spectroscopy was used for real-time endpoint detection, ensuring precise etch control. The process achieved a TiN-to-HSQ selectivity of ~1.6 and reproducible nanoscale features with smooth sidewalls and an average taper angle of ~77°. Buffered hydrogen fluoride treatment effectively removed residual HSQ, revealing sharp TiN features and preserving pillar geometry. Atomic force microscopy (AFM) confirmed pillar height and profile fidelity, while conductive AFM verified electrical conductivity after planarization. The module was further demonstrated through the fabrication of TiN pillar arrays, TaN pillars, and sub-100 nm TiN line arrays. A CRAM test structure incorporating TiN pillars exhibited preliminary switching, indicating that both the test structure and fabrication process are feasible. This fabrication module provides a reproducible platform for nanoscale TiN and TaN electrodes, supporting laboratory-scale research and providing a pathway toward future integration of emerging memory and nanoelectronic technologies. Full article

This paper presents a process-controlled study of illumination engineering in single-photon avalanche diodes (SPADs) fabricated in a 110 nm standard CMOS image sensor (CIS) technology. Front-illuminated (FI) and back-illuminated (BI) SPADs were implemented with identical front-end-of-line (FEOL) structures, including the junction and guard-ring configurations, enabling the isolation of the effects of illumination direction and back-end-of-line (BEOL) configuration without modifying the junction structure. Through TCAD simulations and comprehensive experimental characterizations, including current–voltage, light-emission, dark count rate (DCR), photon detection probability (PDP), and timing-jitter measurements, we systematically analyze the performance trade-offs introduced by the BI configuration. The BI SPAD exhibits enhanced near-infrared PDP and a broader spectral response due to its deeper absorption region and the incorporation of a metal reflector, while maintaining identical avalanche characteristics, as evidenced by an unchanged 72 ps full-width-at-half-maximum (FWHM) timing jitter. However, the backside illumination increases the diffusion tail, indicating a trade-off between near-infrared sensitivity and diffusion-related timing performance. These results provide design guidelines for optimizing SPAD performance through illumination-direction and BEOL engineering while preserving the FEOL design and demonstrate a useful approach for SPAD integration in standard CMOS technology. Full article

Solid-state lighting, especially light-emitting diodes (LEDs), is revolutionizing indoor lighting due to its energy efficiency, long lifespan, low heat output, and enhanced color rendering. LEDs can quickly adjust light intensity, enabling the development of visible light communication (VLC) technology. However, the modulation bandwidth of phosphor-converted white LEDs commonly used for illumination is limited, potentially affecting the speed of the VLC links. This paper presents a receiver-side equalization technique to overcome bandwidth limitations in VLC links due to LEDs. The proposed approach utilizes a novel transimpedance amplifier with an embedded T-network shunt-feedback equalizer (TIA-TE) to introduce adjustable high-frequency peaking in the TIA’s frequency response. By incorporating this peaking, the system’s bandwidth is extended without sacrificing important performance parameters like gain, noise, or power dissipation. The TIA-TE is followed by a main amplifier and a standalone continuous-time linear equalizer (CTLE) for further signal conditioning, while a 50 Ω buffer interfaces the receiver with measurement equipment. Post-layout simulations in a 0.35 µm CMOS process validate the approach. Using a 4 pF photodiode, the system bandwidth was initially limited by the LED’s 3 MHz modulation bandwidth. The proposed TIA-TE extends the bandwidth to 8.4 GHz without sacrificing the gain or power dissipation. The subsequent CTLE further extends the bandwidth to 14 MHz. The receiver front end achieves a mid-band transimpedance of 110 dBΩ and an input-referred noise current of 7.2 nA_rms, while dissipating 2.48 mW (excluding the 50 Ω buffer). Simulated 28 Mb/s NRZ eye diagrams demonstrate the feasibility of the proposed TIA-TE architecture for LED-limited VLC links. Full article

The continuous scaling of microelectronic technology nodes has imposed fundamental physical constraints on conventional floating-gate (FG) non-volatile memory, driving the adoption of charge-trapping memory such as Silicon–Oxide–Nitride–Oxide–Silicon (SONOS) technology. SONOS devices offer advantages in scalability, endurance, and compatibility with advanced CMOS processes, yet their high-temperature reliability remains challenging due to charge loss mechanisms influenced by device structure and material properties. In this work, we systematically evaluate the reliability of two-transistor SONOS memory fabricated using a 28 nm high-K metal gate (HKMG) process. A refined temperature-dependent charge loss model (T-model) is introduced, which, by incorporating a characteristic temperature parameter (T₀) that captures the dynamic shift in activation energy, fundamentally departs from the constant-activation energy assumption of the conventional Arrhenius model. This approach more accurately describes charge retention behavior across a wide temperature range. Experimental results demonstrate excellent device performance, including endurance exceeding 10⁴ program/erase cycles at 85 °C and data retention over 10 years at 85 °C. The T-model shows strong agreement with measured data, providing a physically grounded framework for predicting long-term reliability. This study not only validated a novel charge loss model, providing insights for predicting the failure time of SONOS memory, but also demonstrated that HKMG-integrated SONOS memory exhibits high reliability. Full article

Porous silicon (PSi), characterized by its high specific surface area and highly tunable morphology, presents significant potential across optoelectronics, energy storage, and biomedical applications. This review provides a systematic analysis of the synthesis methodologies, interfacial chemical engineering, and diverse applications of PSi. Initially, fabrication techniques are examined, contrasting the pore formation mechanisms of electrochemical anodization, metal-assisted chemical etching (MACE), and emerging vapor-phase etching methods, while elucidating the control of geometric parameters from microporous to macroporous scales. To address the thermodynamic instability of the hydride-terminated surface, this review systematically evaluates modification strategies such as thermal oxidation, hydrosilylation, carbonization, and atomic layer deposition (ALD). We critically analyze their efficacy in mitigating oxidative drift and enabling specific functionalization. Subsequently, the review summarizes current applications in sensing (refractive index and photoluminescence modulation), energy storage (lithium-ion battery anodes and supercapacitors), and microsystem technologies (radio frequency (RF) isolation, gettering, and micro-electro-mechanical systems (MEMS) sacrificial layers), emphasizing the critical role of structure–property relationships. Finally, an objective assessment is provided regarding the challenges in translating PSi technology to industrial scales, specifically addressing the trade-offs between biodegradability and stability, wafer-scale process uniformity, and the compatibility of wet-chemical processing with standard complementary metal–oxide–semiconductor (CMOS) integration flows. Full article