VDTA-Based Mixed-Mode Inverse Filter and Its Application to Mixed-Mode PID Controller

Abstract

This paper presents a novel voltage differencing transconductance amplifier (VDTA)-based mixed-mode inverse filter capable of operating in voltage mode, transadmittance mode, transimpedance mode, and current mode using a single topology. The proposed configuration employs only three VDTAs with two resistors and three capacitors, offering low component count, high input/output impedance flexibility, and no requirement for component matching. It simultaneously realizes first-order inverse lowpass and highpass, as well as second-order inverse bandpass responses. A comprehensive non-ideal analysis, which includes the effects of VDTA parasitic impedances, determines the practical operating frequency range. The design is validated through PSPICE simulations using 0.18 μm CMOS technology, showing close alignment between theoretical predictions and simulation results, with cutoff frequencies of approximately 1.60 MHz and low power consumption of 0.972 mW. Further analyses confirm orthogonal tuning capability, acceptable temperature stability, and robustness against component tolerances. In a practical application, the proposed inverse filter is employed to implement a mixed-mode PID controller, which significantly improves transient response characteristics by reducing rise time, settling time, and steady-state error. These findings highlight the effectiveness and versatility of the proposed design for analog signal processing and control system applications.

1. Introduction

Inverse filters play a vital role in control, instrumentation, and speech processing applications, where they are employed to compensate for signal distortions introduced by linear or nonlinear systems. By providing a frequency response that is inversely proportional to that of the target system, inverse filters enable effective restoration of degraded signals. They are also widely utilized in communication systems, for example, in signal quality monitoring and frequency modulation de-emphasis. Furthermore, in control engineering, inverse lowpass (ILP), inverse highpass (IHP), and inverse bandpass (IBP) are essential for realizing proportional–integral (PI), proportional–derivative (PD), and proportional–integral–derivative (PID) controllers. Consequently, extensive research efforts have been devoted to the design and implementation of inverse filters using various modern active building blocks [1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22].

Existing inverse filter realizations have been reported in different operation modes, including voltage-mode (VM) [1,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22], current-mode (CM) [1,3,16,18], and transadmittance-mode configurations [2]. Among these, both first-order [9,15,17,18,21] and second-order [1,2,3,4,5,6,7,8,9,10,12,13,14,15,16,18,19,20,21,22] inverse filters have been widely investigated. Numerous inverse filter circuits have since been proposed using different active elements, although many of these configurations realize only a single filtering function [1,2,3,9,10,11,13,15,16,17]. Multifunction second-order inverse filters have also been reported [4,5,6,7,8,12,14,18,19,20,21,22]; however, they often suffer from increased circuit complexity due to the use of multiple active elements and a relatively large number of passive components, in some cases exceeding seven elements [3,6,7,10,11,15,16,22]. In [4,6,8,14,18,19,20,21,22], multifunction filtering functions can be achieved by altering external passive elements. Some of them also necessitate the use of external analog switches to produce multifunction filtering responses [5,7,12]. In VM designs, several reported circuits exhibit high output impedance [4,5,6,7,9,10,14], which limits their suitability for cascaded operation. Importantly, none of the previous configurations can support all four operation modes—voltage mode (VM), transadmittance mode (TAM), transimpedance mode (TIM), and current mode (CM)—within a single design without changing the circuit topology.

In light of the above discussion, this work is motivated by the need for a compact, low-complexity, and versatile inverse filter capable of supporting multiple operation modes within a single design. To address the limitations of existing designs, this work focuses on the utilization of a voltage differencing transconductance amplifier (VDTA) as an active building block for the realization of a mixed-mode inverse filter. The proposed filter employs three VDTAs and a minimal number of passive components to simultaneously enable VM, TAM, TIM, and CM operations. The circuit also offers several key contributions, including multifunction inverse filtering (first-order ILP and IHP as well as second-order IBP responses), high input/output impedance suitability for cascading, absence of component matching constraints, and built-in tunability of key parameters. Furthermore, comprehensive non-ideal and parasitic analyses are provided to establish practical operating conditions, and the effectiveness of the design is validated through simulation results and its application to mixed-mode PID controller implementation. Comparative evaluations with previously reported designs are presented in

Table 1. Comparative evaluations of the proposed mixed-mode inverse filter with previously reported designs.

Ref.	Operation Mode	Filter Order	Filter Type	No. of Active Components	No. of Passive Components	Technology	Supply Voltages (V)	Total Power Consumption (mW)
[1]	VM	2nd	ILP, IBP, IHP, IBS	2 CFOA	ILP, IBP, IHP: 4R + 2C, IBS: 6R + 2C	AD844	N/A	N/A
	CM	2nd	ILP	3 CFOA	3R + 2C
[2]	TAM	2nd	IHP	3 CDTA	2R + 2C	MOSIS 0.35 μm	±3.5	N/A
[3]	VM	2nd	ILP, IBP, IHP	ILP, IBP: 6 CCII, IHP: 5 CCII	ILP, IBP: 6R + 2C, IHP: 5R + 2C	MOSIS 0.5 μm	±1.85	7.01–10.2
	CM	2nd	ILP, IBP, IHP	ILP, IBP: 5 CCII, IHP: 4 CCII	ILP, IBP: 4R + 2C, IHP: 3R + 2C
[4]	VM	2nd	ILP, IBP, IHP	2 OTRA	ILP, IBP: 4R + 2C, IHP: 3R + 3C	TSMC 0.18 μm	N/A	N/A
[5]	VM	2nd	ILP, IBP, IHP, IBS	ILP, IBP, IBS: 3 VDTA, IHP: 2 VDTA	2C	TSMC 0.18 μm	±0.9	N/A
				Unified filter: 4 VDTA, 2 SW	3C
[6]	VM	2nd	IBS, IAP	2 OTRA	4(6)R + 3(4)C	TSMC 0.18 μm	±0.9, −0.3	N/A
[7]	VM	2nd	IBS, IAP	2 CDBA, 1 SW	5R + 2C	TSMC 0.18 μm	±2.5	N/A
[8]	VM	2nd	ILP, IBP, IHP	2 CDBA	4R + 2C	TSMC 0.18 μm	±2.5	N/A
[9]	VM	1st	ILP, IHP	1 OA	ILP: 1(2)R + 1C, IHP: 1(2)R + 1(2)C	VCVS macro model	N/A	N/A
		2nd	IBP	1 OA	2R + 2C
[10]	VM	2nd	IBS	1 OTRA, 3 SW	5R + 5C	CMOS 0.18 μm	±1.5, −0.5	1.46
[11]	VM	6th	IBP	2 CDBA	9R + 9C	TSMC 0.18 μm	±0.6	0.918
[12]	VM	2nd	ILP, IBP, IHP, IBS	4 VDTA, 3 SW	2C	TSMC 0.18 μm	±0.9	2.16
[13]	VM	2nd	ILP, IBP, IHP, IBS	ILP, IBP, IHP: 4 OTA, IBS: 5 OTA	2C	TSMC 0.18 μm	±0.9, −0.6–−0.78	N/A
[14]	VM	2nd	ILP, IBP, IHP, IBS	1 CDBA	ILP: 3R + 2C, IBP, IBS: 2R + 2C, IHP: 2R + 3C	TSMC 0.35 μm	±2.5	N/A
[15]	VM	1st	ILP, IHP	2 VCII	4R + 1C	TSMC 0.18 μm	±0.9	0.6
		2nd	IBP	3 VCII	6R + 2C
[16]	VM	2nd	IBP	2 VCII	5R + 2C	TSMC 0.18 μm	±0.9	N/A
	CM	2nd	ILP, IBP, IHP, IBS	2 VCII	2R + 2C
[17]	VM	1st	ILP, IHP	2 CFOA	3R + 2C	AD844	N/A	N/A
[18]	VM	1st	ILP, IHP	1 VCII	ILP: 1R + 2C, IHP: 2R + 1C	TSMC 0.18 μm	±0.75	0.255
		2nd	ILP, IBP, IHP	2 VCII	ILP: 2R + 4C, IBP: 3R + 3C, IHP: 4R + 2C			0.511
	CM	1st	ILP, IHP	2 VCII	ILP: 1R + 2C, IHP: 2R + 1C			0.511
		2nd	ILP, IBP, IHP	3 VCII	ILP: 4R + 2C, IBP: 3R + 3C, IHP: 4R + 2C			0.766
[19]	VM	2nd	ILP, IBP, IHP	1 VCII	3R + 2C	TSMC 0.18 μm	±0.3	N/A
[20]	VM	2nd	ILP, IBP, IHP, IBS	1 OTRA	ILP: 3R + 2C IHP: 2R + 3C IBP: 3R + 2C IBS: 3R + 3C	TSMC 0.18 μm	±1.5	N/A
[21]	VM	1st	ILP, IHP	1 DVCC	ILP: 1R + 2C IHP: 2R + 1C	TSMC 0.18 μm	±1.5, +0.75	N/A
		2nd	ILP, IBP, IHP	2 DVCC	ILP: 2R + 4C IHP: 4R + 2C IBP: 3R + 3C
[22]	VM	2nd	ILP, IBP, IHP	3 DDCC	3R + 3C	BSIM 90 nm	±1, −0.33	2.48
				4 DDCC	5R + 3C
Proposed circuit	VM, TAM, TIM, CM	1st	ILP, IHP	3 VDTA	2R + 3C	TSMC 0.18 μm	±0.9	0.972
		2nd	IBP
		PID controller function

Note: ILP = inverse lowpass, IHP = inverse highpass, IBP = inverse bandpass, IBS = inverse bandstop, IAP = inverse allpass, R = resistor, C = capacitor, N/A = not available or not measured, CFOA = Current-Feedback Operational Amplifier, CDTA = Current Differencing Transconductance Amplifier, CCII = Second-Generation Current Conveyor, OTRA = Operational Transresistance Amplifier, VDTA = Voltage Differencing Transconductance Amplifier, CDBA= Current Differencing Buffered Amplifier, OA = Operational Amplifier, OTA = Operational Transconductance Amplifier, VCII = Second-Generation Voltage Conveyor, DVCC = Differential Voltage Current Conveyor, DDCC = Differential Difference Current Conveyor.

to emphasize the advantages of the proposed configuration regarding operation mode, filter order, available responses, component count, technology used, bias voltage levels, and total power consumption.

The remainder of this paper is organized as follows: Section 2 introduces the VDTA and its fundamental characteristics. Section 3 presents the proposed mixed-mode inverse filter and its operational principles. Section 4 analyzes non-ideal effects. Section 5 discusses simulation results and performance evaluation. Section 6 demonstrates the application of the proposed method to PID controller design; and finally, Section 7 concludes the paper.

2. Voltage Differencing Transconductance Amplifier (VDTA)

The VDTA is a versatile active building block consisting of two cascaded transconductance stages. Its symbolic representation and a CMOS implementation are shown in Figure 1 and Figure 2, respectively. The VDTA provides differential voltage processing at its input stage and transconductance-based current outputs (i_z± and i_x±) at its output stage. The ideal terminal characteristics of the VDTA are described by the following matrix equation [5,12]:

$$\left[\begin{array}{c}{i}_{z+}\\ i_{z-}\\ i_x\end{array}\right]=\left[\begin{array}{ccc}{g}_{mF}& -g_{mF}& 0\\ -g_{mF}& g_{mF}& 0\\ 0& 0& g_{mS}\end{array}\right]\left[\begin{array}{c}{v}_p\\ v_n\\ v_{z+}\end{array}\right],$$

(1)

where g_mF and g_mS denote the first- and second-stage transconductance gains, respectively. From (1), the VDTA operates in two successive stages. In the first stage, the differential input voltage (v_p–v_n) is converted into output currents, i_z+ and i_z−, with opposite polarities, through the transconductance gain g_mF. In the second stage, the voltage at the terminal z+ (v_z+) is transformed into the output current, i_x, via the transconductance gain g_mS. This structure enables flexible voltage-to-current conversion and current-mode signal processing.

For the CMOS implementation shown in Figure 2, the transconductance gains g_mF and g_mS can be expressed as [23]

$$g_{mF}\cong \left({\displaystyle \frac{g_1{g}_2}{g_1+g_2}}\right)+\left({\displaystyle \frac{g_3{g}_4}{g_3+g_4}}\right),$$

(2)

and

$$g_{mS}\cong \left({\displaystyle \frac{g_5{g}_6}{g_5+g_6}}\right)+\left({\displaystyle \frac{g_7{g}_8}{g_7+g_8}}\right),$$

(3)

where the parameter g_i (i = 1, 2, …, 8) represents the intrinsic transconductance of the i-th MOS transistor, given by [24]

$$g_i=\sqrt{I_{Bi}\mu C_{ox}{\displaystyle \frac{W_i}{L_i}}}.$$

(4)

Here, I_Bi is the bias current of the corresponding transistor, μ is the carrier mobility, C_ox is the gate oxide capacitance per unit area, and W_i and L_i are the channel width and length, respectively. These expressions indicate that the transconductance values g_mF and g_mS can be electronically adjusted through the bias currents. This electronic tunability makes the VDTA particularly suitable for analog signal processing applications requiring adaptive or controllable circuit parameters. Based on these advantageous properties, the VDTA is employed in this work as the sole active element to realize the proposed tunable mixed-mode inverse biquad filter circuit described in the following section.

3. Proposed VDTA-Based Mixed-Mode Inverse Filter

Figure 3 illustrates the proposed VDTA-based mixed-mode inverse filter employing two resistors and three capacitors. The circuit supports mixed-mode operation and enables realization of first-order inverse LP and HP and second-order inverse BP filtering responses. The proposed mixed-mode inverse filter includes several notable features: (i) it can operate in all four possible modes—VM, TAM, TIM, and CM—using a single circuit topology; (ii) it boasts high input impedance for VM and TAM, as well as high output impedance for TIM and CM operations; (iii) there is no need for matching active and passive components; and (iv) it offers built-in tunability of passband gain and pole frequency. Assuming ideal VDTA characteristics, the circuit behavior in each mode is described as follows.

3.1. Operation in VM and TAM

According to the configuration shown in Figure 3, both input currents are set to zero (i_i1 = i_i2 = 0), which enables the circuit to operate as a two-input four-output inverse filter. By selecting the appropriate input voltage (v_in), it is possible to realize first-order LP and HP inverse filters, as well as a second-order BP inverse filter for VM and TAM operations.

3.1.1. VM Inverse Filter Realization

• When the input voltage (v_in) is set as v_in = v_i1 and v_i2 = 0 (grounded), the first-order ILP filter is implemented with

$${\displaystyle \frac{V_{out1}(s)}{V_{in}(s)}}=\left({\displaystyle \frac{g_{mF1}{g}_{mS1}{C}_3}{g_{mF2}{g}_{mS2}{C}_1}}\right)\left(s{R}_1{C}_1+1\right).$$

(5)

• When v_in = v_i2 and v_i1 = 0, the first-order IHP filter is implemented with

$${\displaystyle \frac{V_{out1}(s)}{V_{in}(s)}}=-g_{mS1}{R}_1\left({\displaystyle \frac{s{R}_1{C}_1+1}{s{R}_1{C}_1}}\right).$$

(6)

• When v_in = v_i1 and v_i2 = 0, the second-order IBP filter is implemented with

$${\displaystyle \frac{V_{out2}(s)}{V_{in}(s)}}={\displaystyle \frac{H_{0}N(s)}{s\left(R_1{C}_1+R_2{C}_2\right)}},$$

(7)

where the minimum gain (H₀) and the numerical polynomial N(s) are

$$N(s)=s^2{R}_1{R}_2{C}_1{C}_2+s\left(R_1{C}_1+R_2{C}_2\right)+1,$$

(8)

and

$$H_0={\displaystyle \frac{g_{mF1}{g}_{mS1}{g}_{mF3}{C}_3\left(R_1{C}_1+R_2{C}_2\right)}{g_{mF2}{g}_{mS2}{C}_1{C}_2}}.$$

(9)

Therefore, the proposed circuit effectively realizes the ILP and IHP sections as described by Equations (5) and (6), respectively, with a cutoff frequency defined as

$${\omega }_c=2\pi f_c={\displaystyle \frac{1}{R_1{C}_1}}.$$

(10)

Additionally, as evident from Equations (7) through (9) of the second-order IBP filter, the key characteristics of the filter, namely cutoff frequency (ω_c) and quality factor (Q), are determined as follows:

$${\omega }_c={\displaystyle \frac{1}{\sqrt{R_1{R}_2{C}_1{C}_2}}},$$

(11)

and

$$Q={\displaystyle \frac{\sqrt{R_1{R}_2{C}_1{C}_2}}{R_1{C}_1+R_2{C}_2}}.$$

(12)

Table 2. Input voltage selection and corresponding performance parameters for VM inverse filter realization in Figure 3.

Inverse Filter Response	Input Voltage		VM Transfer Function	Minimum Gain (H0)	Cutoff Frequency (ωc)	Quality Factor (Q)
	vi1	vi2
1st-order ILP	vin	0	${\displaystyle \frac{V_{out1}(s)}{V_{in}(s)}}=H_0\left(s{R}_1{C}_1+1\right)$	${\displaystyle \frac{g_{mF1}{g}_{mS1}{C}_3}{g_{mF2}{g}_{mS2}{C}_1}}$	${\displaystyle \frac{1}{R_1{C}_1}}$	-
1st-order IHP	0	vin	${\displaystyle \frac{V_{out1}(s)}{V_{in}(s)}}=-H_0\left({\displaystyle \frac{s{R}_1{C}_1+1}{s{R}_1{C}_1}}\right)$	$g_{mS1}{R}_1$	${\displaystyle \frac{1}{R_1{C}_1}}$	-
2nd-order IBP	vin	0	${\displaystyle \frac{V_{out2}(s)}{V_{in}(s)}}={\displaystyle \frac{H_{0}N(s)}{s\left(R_1{C}_1+R_2{C}_2\right)}}$	${\displaystyle \frac{g_{mF1}{g}_{mS1}{g}_{mF3}{C}_3\left(R_1{C}_1+R_2{C}_2\right)}{g_{mF2}{g}_{mS2}{C}_1{C}_2}}$	${\displaystyle \frac{1}{\sqrt{R_1{R}_2{C}_1{C}_2}}}$	${\displaystyle \frac{\sqrt{R_1{R}_2{C}_1{C}_2}}{R_1{C}_1+R_2{C}_2}}$

summarizes the selection of the input voltage and the corresponding performance parameters for the VM inverse filter implementation illustrated in Figure 3.

3.1.2. TAM Inverse Filter Realization

Using the same circuit topology, the first-order ILP and IHP filters, along with the second-order IBP filter in TAM operation, can be implemented by selecting the appropriate input voltage (v_in), as indicated in

Table 3. Input voltage selection and corresponding performance parameters for TAM inverse filter realization in Figure 3.

Inverse Filter Response	Input Voltage		TAM Transfer Function	Minimum Gain (H0)	Cutoff Frequency (ωc)	Quality Factor (Q)
	vi1	vi2
1st-order ILP	vin	0	${\displaystyle \frac{I_{out1}(s)}{V_{in}(s)}}=-H_0\left(s{R}_1{C}_1+1\right)$	${\displaystyle \frac{g_{mF1}{g}_{mS1}{g}_{mF3}{C}_3}{g_{mF2}{g}_{mS2}{C}_1}}$	${\displaystyle \frac{1}{R_1{C}_1}}$	-
1st-order IHP	0	vin	${\displaystyle \frac{I_{out1}(s)}{V_{in}(s)}}=H_0\left({\displaystyle \frac{s{R}_1{C}_1+1}{s{R}_1{C}_1}}\right)$	$g_{mS1}{g}_{mF3}{R}_1$	${\displaystyle \frac{1}{R_1{C}_1}}$	-
2nd-order IBP	vin	0	${\displaystyle \frac{I_{out2}(s)}{V_{in}(s)}}=-{\displaystyle \frac{H_{0}N(s)}{s\left(R_1{C}_1+R_2{C}_2\right)}}$	${\displaystyle \frac{g_{mF1}{g}_{mS1}{g}_{mF3}{g}_{mS3}{C}_3\left(R_1{C}_1+R_2{C}_2\right)}{g_{mF2}{g}_{mS2}{C}_1{C}_2}}$	${\displaystyle \frac{1}{\sqrt{R_1{R}_2{C}_1{C}_2}}}$	${\displaystyle \frac{\sqrt{R_1{R}_2{C}_1{C}_2}}{R_1{C}_1+R_2{C}_2}}$

.

3.2. Operation in TIM and CM

From the same circuit configuration with v_i1 = v_i2 = 0, we can derive the TIM and CM inverse filters with the following description.

3.2.1. TIM Inverse Filter Realization

In this design, when the appropriate input current signal (i_in) is applied as detailed in

Table 4. Input current selection and corresponding performance parameters for TIM inverse filter realization in Figure 3.

Inverse Filter Response	Input Current		TIM Transfer Function	Minimum Gain (H0)	Cutoff Frequency (ωc)	Quality Factor (Q)
	ii1	ii2
1st-order ILP	iin	0	${\displaystyle \frac{V_{out1}(s)}{I_{in}(s)}}=-H_0\left(s{R}_1{C}_1+1\right)$	${\displaystyle \frac{g_{mS1}{C}_3}{g_{mF2}{g}_{mS2}{C}_1}}$	${\displaystyle \frac{1}{R_1{C}_1}}$	-
1st-order IHP	0	iin	${\displaystyle \frac{V_{out1}(s)}{I_{in}(s)}}=H_0\left({\displaystyle \frac{s{R}_1{C}_1+1}{s{R}_1{C}_1}}\right)$	R1	${\displaystyle \frac{1}{R_1{C}_1}}$	-
2nd-order IBP	iin	0	${\displaystyle \frac{V_{out2}(s)}{I_{in}(s)}}=-{\displaystyle \frac{H_{0}N(s)}{s\left(R_1{C}_1+R_2{C}_2\right)}}$	${\displaystyle \frac{g_{mF3}{g}_{mS1}{C}_3\left(R_1{C}_1+R_2{C}_2\right)}{g_{mF2}{g}_{mS2}{C}_1{C}_2}}$	${\displaystyle \frac{1}{\sqrt{R_1{R}_2{C}_1{C}_2}}}$	${\displaystyle \frac{\sqrt{R_1{R}_2{C}_1{C}_2}}{R_1{C}_1+R_2{C}_2}}$

, the proposed circuit in Figure 3 performs as a TIM filter. This configuration allows the circuit to derive first-order ILP and IHP and second-order IBP filter responses, all within the same topology.

3.2.2. CM Inverse Filter Realization

Furthermore, the circuit is capable of operating as a CM inverse filter by setting the current i_in according to

Table 5. Input current selection and corresponding performance parameters for CM inverse filter realization in Figure 3.

Inverse Filter Response	Input Current		CM Transfer Function	Minimum Gain (H0)	Cutoff Frequency (ωc)	Quality Factor (Q)
	ii1	ii2
1st-order ILP	iin	0	${\displaystyle \frac{I_{out1}(s)}{I_{in}(s)}}=H_0\left(s{R}_1{C}_1+1\right)$	${\displaystyle \frac{g_{mS1}{g}_{mS3}{C}_3}{g_{mF2}{g}_{mS2}{C}_1}}$	${\displaystyle \frac{1}{R_1{C}_1}}$	-
1st-order IHP	0	iin	${\displaystyle \frac{I_{out1}(s)}{I_{in}(s)}}=-H_0\left({\displaystyle \frac{s{R}_1{C}_1+1}{s{R}_1{C}_1}}\right)$	$g_{mF3}{R}_1$	${\displaystyle \frac{1}{R_1{C}_1}}$	-
2nd-order IBP	iin	0	${\displaystyle \frac{I_{out2}(s)}{I_{in}(s)}}={\displaystyle \frac{H_{0}N(s)}{s\left(R_1{C}_1+R_2{C}_2\right)}}$	${\displaystyle \frac{g_{mF3}{g}_{mS1}{g}_{mS3}{C}_3\left(R_1{C}_1+R_2{C}_2\right)}{g_{mF2}{g}_{mS2}{C}_1{C}_2}}$	${\displaystyle \frac{1}{\sqrt{R_1{R}_2{C}_1{C}_2}}}$	${\displaystyle \frac{\sqrt{R_1{R}_2{C}_1{C}_2}}{R_1{C}_1+R_2{C}_2}}$

.

4. Non-Ideal Performance Analysis

In practical implementations, the VDTA exhibits non-ideal parasitic impedances at its terminals, which may influence the performance of the proposed mixed-mode inverse filter shown in Figure 3. The complete non-ideal VDTA model including these parasitic elements is depicted in Figure 4, where R_p, R_n, R_z+, R_z-, and R_x, together with C_p, C_n, C_z+, C_z−, and C_x, represent the parasitic resistances and capacitances at the respective terminals. Under ideal conditions, the parasitic impedances become negligible as R_p, R_n, R_z+, R_z-, and R_x approach infinity, while C_p, C_n, C_z+, C_z−, and C_x approach zero.

In practice, these parasitic elements introduced extra dominant poles into the realized filter functions, thereby affecting the frequency responses of the proposed circuit. Considering the VDTA-based mixed-mode inverse filter in Figure 3, the effective impedances at terminals v_out1 and v_out2 are expressed as

$$Z_1^{\prime }={\displaystyle \frac{s{R}_1{C}_1+1}{s^2{R}_1{C}_1{C}_A+s{C}_1\left(1+\frac{R_1}{R_A}+\frac{C_A}{C_1}\right)+\left(\frac{1}{R_A}\right)}},$$

(13)

and

$$Z_2^{\prime }={\displaystyle \frac{s{R}_2{C}_2+1}{s^2{R}_2{C}_2{C}_{z3+}+s{C}_2\left(1+\frac{R_2}{R_{z3+}}+\frac{C_{z3+}}{C_2}\right)+\left(\frac{1}{R_{z3+}}\right)}},$$

(14)

where R_A = (R_x1− // R_p3), C_A = (C_x1− + C_p3). Here, R_x1−, R_p3, R_z3+, and C_x1−, C_p3, C_z3+ refer to parasitic resistances and capacitances associated with the corresponding terminal of the i-th VDTA (where i = 1, 2, 3). It is noted from the practical perspective that R_A >> R₁, C₁ >> C_A and C₂ >> C_z3+. Consequently, Equations (13) and (14) can be approximated as follows:

$$Z_1^{\prime }\cong {\displaystyle \frac{s{R}_1{C}_1+1}{s{C}_1\left(s{R}_1{C}_A+1\right)+\left(\frac{1}{R_A}\right)}},$$

(15)

and

$$Z_2^{\prime }={\displaystyle \frac{s{R}_2{C}_2+1}{s{C}_2\left(s{R}_2{C}_{z3+}+1\right)+\left(\frac{1}{R_{z3+}}\right)}}.$$

(16)

Equation (15) indicates that two extra parasitic poles are introduced at low and high frequencies, as described below:

$${\omega }_{L1}={\displaystyle \frac{1}{\left(R_{p3}//R_{x1-}\right)C_1}} \mathrm{and} {\omega }_{H1}={\displaystyle \frac{1}{R_1\left(C_{p3}+C_{x1-}\right)}}.$$

(17)

Therefore, the useful frequency range is considerably constrained by these parasitic poles, i.e.,

$$\left\{{\omega }_{L1}\right\}<<\omega <<\left\{{\omega }_{H1}\right\}.$$

(18)

Similarly, based on Equation (16), two additional poles resulting from parasitic effects are found at a specified location as

$${\omega }_{L2}={\displaystyle \frac{1}{R_{z3+}{C}_2}} \mathrm{and} {\omega }_{H2}={\displaystyle \frac{1}{R_2{C}_{z3+}}},$$

(19)

and the frequency limitation of the circuit can also be defined, as shown in

$$\left\{{\omega }_{L2}\right\}<<\omega <<\left\{{\omega }_{H2}\right\}.$$

(20)

Furthermore, considering parasitics, the equivalent impedance at terminals z+ of VDTA-1 and VDTA-2 can be computed as follows:

$$Z_3^{\prime }={\displaystyle \frac{R_B}{s{R}_B{C}_B+1}},$$

(21)

and

$$Z_4^{\prime }={\displaystyle \frac{R_{z2+}}{s{R}_{z2+}{C}_3+1}}.$$

(22)

where R_B = (R_z1+ // R_p2 // R_x2−), C_B = (C_z1+ + C_p2 + C_x2−). Additionally, there is also a performance limit at low frequencies due to extra unwanted poles arising from parasitic impedances of the VDTA:

$${\omega }_{L3}={\displaystyle \frac{1}{\left(R_{z1+}//R_{p2}//R_{x2-}\right)\left(C_{z1+}+C_{p2}+C_{x2-}\right)}} \mathrm{and} {\omega }_{L4}={\displaystyle \frac{1}{R_{z2+}{C}_3}}.$$

(23)

Therefore, in this case, the proposed circuit can be utilized within the following frequency ranges:

$$\omega >>\left\{{\omega }_{L3}\right\} \mathrm{and} \omega >>\left\{{\omega }_{L4}\right\}.$$

(24)

Lastly, parasitics at terminals directly connected to inputs v_i1 and v_i2 do not have any effect.

As indicated by Equations (18), (20) and (24), it can be concluded that the overall operating frequency of the proposed mixed-mode inverse filter given in Figure 3 must be derived within the following region:

$$\max \left\{{\omega }_{L1},{\omega }_{L2},{\omega }_{L3},{\omega }_{L4}\right\}<<\omega <<\min \left\{{\omega }_{H1},{\omega }_{H2}\right\}$$

(25)

5. Functional Simulations and Performance Discussions

The theoretical analysis and practical feasibility of the proposed VDTA-based mixed-mode inverse filter in Figure 3 were verified through extensive numerical simulations. These simulations utilized a CMOS implementation of the VDTA presented in Figure 2 and aim to evaluate the expected frequency characteristics, tuning capabilities, and overall filtering performance utilizing practical device parameters. In simulations, the PSPICE program was employed using TSMC 0.18 μm CMOS process parameters.

Table 6. Transistor aspect ratios (W/L) used in the CMOS implementation of the VDTA shown in Figure 2.

Transistors	W/L (μm/μm)
M1, M2, M5, M6	24/0.18
M3, M4, M7, M8	30/0.18
M13–M18	5/0.18
M9–M12	6/0.18

lists the effective width (W) and length (L) of the CMOS transistors in Figure 2. The circuits operated under symmetrical supply voltages of ±0.9 V.

For all simulations, identical active and passive components were used: g_mFj = g_mSj (j = 1, 2, 3) = 1 mA/V (I_BFj = I_BSj = 90 μA), R₁ = R₂ = 1 kΩ and C₁ = C₂ = C₃ = 100 pF. This yields the theoretical cutoff frequency of f_c = ω_c/2π = 1.59 MHz. The simulated transient and frequency responses of the VM, TAM, TIM, and CM inverse filters are shown in Figure 5, Figure 6, Figure 7 and Figure 8, accompanied by their corresponding theoretical characteristics. The filter was tested with input signal peak amplitudes of 50 mV for VM and TAM operations and 50 μA for TIM and CM, all at the nominal frequency of 1.59 MHz. The total power consumption was measured at 0.972 mW.

For the VM inverse filter, the first-order ILP and IHP responses, along with the second-order IBP response, exhibited the simulated f_c of 1.78 MHz, 1.73 MHz, and 1.66 MHz, respectively. In comparison, the first-order ILP and IHP responses and the second-order IBP response for the TAM filter yielded an f_c of 1.73 MHz, 1.64 MHz, and 1.64 MHz, respectively. Similarly, during TIM operation, the first-order ILP and IHP and second-order IBP filters produced f_c values of 1.75 MHz, 1.53 MHz, and 1.58 MHz. For the CM inverse filter, the simulated f_c values for ILP, IHP, and IBP were 1.71 MHz, 1.47 MHz, and 1.66 MHz. These results demonstrate a close alignment between simulated and theoretical values, thereby validating the accuracy of the proposed filter structures.

To verify the tunability of the f_c value, the VM inverse BP filter was simulated while maintaining a constant quality factor (Q = 0.5). The component values were set as C₁ = C₂ = C₃ = 100 pF, with R₁ = R₂ = 0.5 kΩ, 2 kΩ, and 5 kΩ. The corresponding calculated f_c values were 3.18 MHz, 795.77 kHz, and 318.31 kHz, respectively. The ideal and simulated gain–frequency responses are shown in Figure 9, where the simulated f_c values were recorded as 3.18 MHz, 794.33 kHz, and 316.23 kHz, respectively. It is noteworthy that the f_c can be tuned independently without affecting the Q factor, demonstrating the orthogonal tuning capability of the proposed filter.

Monte Carlo (MC) statistical analysis was conducted on the VM IBP filter at the f_c of 1.59 MHz by incorporating nominal 5% Gaussian deviations in the values of resistors and capacitors. Figure 10 presents the simulation results from the MC statistical analysis, which utilized a Gaussian distribution over 200 runs. The mean and standard deviation of the f_c resulting from the variations in resistor and capacitor tolerances were determined to be 1.77251 MHz and 49.461 kHz, respectively, although these changes are not significant.

Furthermore, the proposed inverse filter topology in Figure 3 is analyzed to demonstrate its robustness under various process, voltage, and temperature (PVT) variations. The selected process corners include typical–typical, fast–fast, slow–slow, fast–slow, and slow–fast. The supply voltage corners were varied by ±10% from the nominal value. The temperature corners were set at 0 °C and 100 °C. Figure 11 shows the simulation results for the VM IBP filter response under PVT variations. The voltage gain is observed to increase with rising the supply voltage. Conversely, as the temperature increases, the operating current of the transistor decreases, resulting in a reduction in voltage gain. Consequently, power dissipation decreases up to a certain temperature threshold. In both cases, the response of the proposed circuit is influenced by variations in temperature and voltage, as it depends on the transistor current.

To evaluate the linearity and the input dynamic range of the proposed inverse filter, a sinusoidal signal at a frequency of 1.59 MHz with varying amplitude is applied to the input. Figure 12 depicts the total harmonic distortion (THD) of the VM IBP output signal relative to the amplitude of the input signal. The analysis shows that the THD value increases steadily with the input voltage. For input signals below 100 mV (peak), the THD values remain below 5%, indicating the practical viability of the proposed circuit. Figure 13 shows the equivalent output-referred noise analysis of the VM IBP filter, which indicates a minimal noise output of approximately 10 μV within the 1 kHz to 10 kHz frequency band.

6. Application to Mixed-Mode PID Controller Implementation

Proportional–integral–derivative (PID) controllers are widely used in various industrial process systems. It is estimated that over 90% of all control loops utilize PID controllers [25]. The proposed VDTA-based mixed-mode inverse filter shown in Figure 3 effectively implements the PID controller, which is capable of functioning in all possible four modes. Therefore, this section outlines the approach for implementing the mixed-mode PID controller employing the proposed circuit.

6.1. PID Controller Implementation for VM and TAM Operations

From Figure 3, when v_i2 = 0, the voltage transfer function of a PID controller can be written as

$$G_{CV}(s)={\displaystyle \frac{V_{out2}(s)}{V_{i1}(s)}}=\left[{\displaystyle \frac{g_{mF1}{g}_{mS1}{g}_{mF3}{C}_3\left(R_1{C}_1+R_2{C}_2\right)}{g_{mF2}{g}_{mS2}{C}_1{C}_2}}\right]\left[1+{\displaystyle \frac{1}{s\left(R_1{C}_1+R_2{C}_2\right)}}+{\displaystyle \frac{s{R}_1{R}_2{C}_1{C}_2}{\left(R_1{C}_1+R_2{C}_2\right)}}\right]=K_{PV}+{\displaystyle \frac{K_{IV}}{s}}+K_{DV}s,$$

(26)

where K_PV, K_IV, and K_DV are the proportional, integral, and derivative coefficients in VM, respectively. Then, the corresponding controller coefficients in this case are given by

$$K_{PV}={\displaystyle \frac{g_{mF1}{g}_{mS1}{g}_{mF3}{C}_3\left(R_1{C}_1+R_2{C}_2\right)}{g_{mF2}{g}_{mS2}{C}_1{C}_2}},$$

(27)

$$K_{IV}={\displaystyle \frac{g_{mF1}{g}_{mS1}{g}_{mF3}{C}_3}{g_{mF2}{g}_{mS2}{C}_1{C}_2}},$$

(28)

and

$$K_{DV}={\displaystyle \frac{g_{mF1}{g}_{mS1}{g}_{mF3}{R}_1{R}_2{C}_3}{g_{mF2}{g}_{mS2}}}.$$

(29)

In a similar manner, the general form of the transfer function for the PID controller operating in TAM is presented as follows:

$$G_{CY}(s)={\displaystyle \frac{I_{out2}(s)}{V_{i1}(s)}}=-\left(K_{PY}+{\displaystyle \frac{K_{IY}}{s}}+K_{DY}s\right),$$

(30)

where the PID constants K_PI, K_II, and K_DI can be determined as

$$K_{PY}={\displaystyle \frac{g_{mF1}{g}_{mS1}{g}_{mF3}{g}_{mS3}{C}_3\left(R_1{C}_1+R_2{C}_2\right)}{g_{mF2}{g}_{mS2}{C}_1{C}_2}},$$

(31)

$$K_{IY}={\displaystyle \frac{g_{mF1}{g}_{mS1}{g}_{mF3}{g}_{mS3}{C}_3}{g_{mF2}{g}_{mS2}{C}_1{C}_2}},$$

(32)

and

$$K_{DY}={\displaystyle \frac{g_{mF1}{g}_{mS1}{g}_{mF3}{g}_{mS3}{R}_1{R}_2{C}_3}{g_{mF2}{g}_{mS2}}}.$$

(33)

6.2. PID Controller Implementation for TIM and CM Operations

In a TIM PID controller, connecting i_i2 = 0 in the configuration of Figure 3 yields the following TIM transfer function:

$$G_{CZ}(s)={\displaystyle \frac{V_{out2}(s)}{I_{i1}(s)}}=-\left(K_{PZ}+{\displaystyle \frac{K_{IZ}}{s}}+K_{DZ}s\right),$$

(34)

In this expression, the PID controller parameters are found to be

$$K_{PZ}={\displaystyle \frac{g_{mS1}{g}_{mF3}{C}_3\left(R_1{C}_1+R_2{C}_2\right)}{g_{mF2}{g}_{mS2}{C}_1{C}_2}},$$

(35)

$$K_{IZ}={\displaystyle \frac{g_{mS1}{g}_{mF3}{C}_3}{g_{mF2}{g}_{mS2}{C}_1{C}_2}},$$

(36)

and

$$K_{DZ}={\displaystyle \frac{g_{mS1}{g}_{mF3}{R}_1{R}_2{C}_3}{g_{mF2}{g}_{mS2}}}.$$

(37)

Furthermore, the general form of the CM PID controller can be written as

$$G_{CI}(s)={\displaystyle \frac{I_{out2}(s)}{I_{i1}(s)}}=K_{PI}+{\displaystyle \frac{K_{II}}{s}}+K_{DI}s,$$

(38)

where

$$K_{PI}={\displaystyle \frac{g_{mS1}{g}_{mF3}{g}_{mS3}{C}_3\left(R_1{C}_1+R_2{C}_2\right)}{g_{mF2}{g}_{mS2}{C}_1{C}_2}},$$

(39)

$$K_{II}={\displaystyle \frac{g_{mS1}{g}_{mF3}{g}_{mS3}{C}_3}{g_{mF2}{g}_{mS2}{C}_1{C}_2}},$$

(40)

and

$$K_{DI}={\displaystyle \frac{g_{mS1}{g}_{mF3}{g}_{mS3}{R}_1{R}_2{C}_3}{g_{mF2}{g}_{mS2}}}.$$

(41)

It is important to note that the second subscripts V, Y, Z, and I for the PID controller coefficients denote the VM, TAM, TIM, and CM operations, respectively.

For the performance evaluation of the proposed PID controller described above, the mixed-mode second-order lowpass (LP) filter using a single VDTA shown in Figure 14 is suggested as a plant for implementing a closed-loop control system. The open-loop transfer function of a second-order plant in VM, TAM, TIM, and CM can be represented respectively as follows:

$$G_{PV}(s)={\displaystyle \frac{V_{op}(s)}{V_{ip}(s)}}=\left({\displaystyle \frac{1}{g_{mS}{R}_p}}\right)\left({\displaystyle \frac{{\omega }_n^2}{s^2+2\xi {\omega }_{n}s+{\omega }_n^2}}\right),$$

(42)

$$G_{PY}(s)={\displaystyle \frac{I_{op}(s)}{V_{ip}(s)}}=\left({\displaystyle \frac{1}{R_p}}\right)\left({\displaystyle \frac{{\omega }_n^2}{s^2+2\xi {\omega }_{n}s+{\omega }_n^2}}\right),$$

(43)

$$G_{PZ}(s)={\displaystyle \frac{V_{op}(s)}{I_{ip}(s)}}=\left(-{\displaystyle \frac{1}{g_{mS}}}\right)\left({\displaystyle \frac{{\omega }_n^2}{s^2+2\xi {\omega }_{n}s+{\omega }_n^2}}\right),$$

(44)

and

$$G_{PI}(s)={\displaystyle \frac{I_{op}(s)}{I_{ip}(s)}}=-\left({\displaystyle \frac{{\omega }_n^2}{s^2+2\xi {\omega }_{n}s+{\omega }_n^2}}\right).$$

(45)

In these equations, the natural angular frequency (ω_n) and the damping ratio (ξ) are defined as

$${\omega }_n=\sqrt{{\displaystyle \frac{g_{mF}{g}_{mS}}{C_{p1}{C}_{p2}}}},$$

(46)

and

$$\xi =\left({\displaystyle \frac{1}{2R_p}}\right)\sqrt{{\displaystyle \frac{C_{p2}}{g_{mF}{g}_{mS}{C}_{p1}}}}$$

(47)

To evaluate the impact of various controllers, the performance of the closed-loop system is examined by establishing a unity-feedback system, as illustrated in Figure 15. The proposed PID controllers are utilized to improve the time-domain behavior of the second-order plant. Subsequently, the time-domain responses of both PID-controlled and uncontrolled systems are observed and compared. The component values for the second-order plant in Figure 14 are designed with g_mF = g_mS = 1 mA/V, R_p = 1 kΩ, and C_p1 = C_p2 = 100 pF, yielding f_n = ω_n/2π = 1.59 MHz and ξ = 0.5. For evaluation purposes, the PID controller parameters used to assess the step response behavior of the VM control systems are detailed in

Table 7. PID controller circuit components and their resulting coefficients.

	R1 = R2 (kΩ)	C1 (pF)	C2 (pF)	C3 (pF)	gmFi = gmSi (i = 1, 2, 3) (mA/V)	KPV	KIV (Ms−1)	KDV (ns)
Case 1	0.5	50	50	100	1.0	2.0	40	25
Case 2	0.5	50	100	100	1.0	1.5	20	25
Case 3	1.0	50	50	100	1.0	4.0	40	100

. Figure 16 displays the step responses of the PID-controlled system in Figure 15a under three different controller coefficient settings, compared to the response of the uncontrolled system. The characteristics obtained from the time responses for each case are summarized in

Table 8. Resulting time response characteristics of the PID-controlled and uncontrolled systems in Figure 15a.

		Delay Time, td (μs)	Rise Time, tr (μs)	Peak Time, tp (μs)	Settling Time at 2%, ts (μs)	Maximum Overshoot, Mp (mV)	Steady-State Error (mV)
PID- controlled system	Case 1	2.162	2.242	2.378	3.317	134.189	0.978
	Case 2	2.206	2.335	2.498	3.074	118.762	1.272
	Case 3	2.134	2.244	2.338	2.537	112.111	1.061
Uncontrolled system		2.222	3.298	3.298	2.921	115.683	15.683

.

It is observed from the results that the proposed PID controller improved the time response of the closed-loop control system, particularly t_d, t_r, t_p, and t_s. The times t_r and t_p of the controlled system were approximately 30% faster than that of the uncontrolled system. It also had a steady-state error of less than 1.30 mV. Additionally, the controlled system entered the steady-state faster than the uncontrolled system and tracked the step input with a reduced steady-state error.

7. Comparison with Existing PID Controllers

To evaluate the effectiveness of the proposed PID controller shown in Figure 3, a comparative analysis with recently published PID controllers from 2024 to 2025 [26,27,28,29] is presented in

Table 9. Comparative analysis of the performances of the proposed controller circuit against recently published PID controllers from 2024 to 2025 [26,27,28,29].

Ref.	Operation Mode	No. of Active Components	No. of Passive Components	Rise Time, tr (μs)	Peak Time, tp (μs)	Settling Time, ts (μs)	Maximum Overshoot, Mp (%)	Technology	Supply Voltages (V)	Total Power Consumption (mW)
[26]	VM, TAM, TIM, CM	3 CFOA	4R + 2C	6.88	7.81	9.06	11.43	AD844	±9	348
[27]	CM	2 CFOA	2R + 2C	18.6	1030	1130	11.57	TSMC 0.18 μm	±2	6.8
[28]	VM	2 VCII	2R + 2C	0.334	1.59	2.05	0.55	AD844	±9	235
[29]	TAM	1 DDCCTA	3R + 2C	0.0052	N/A	0.18	0	GPDK 0.18 μm	±0.9, −0.62	4
Proposed PID controller in Figure 3	VM, TAM, TIM, CM	3 VDTA	2R + 3C	2.244	2.338	2.537	11.11	TSMC 0.18 μm	±0.9	0.972

. The comparison considers key performance metrics, including circuit complexity, transient response characteristics, implementation technology, and power consumption.

From Table 9, it is observed that the controller in [26] employs three CFOAs and six passive components, resulting in relatively high power consumption (348 mW) and moderate transient performance (e.g., t_r = 6.88 μs, t_s = 9.06 μs). In contrast, the work of [27] achieves low power consumption (6.8 mW) using only two CFOAs and four passive elements; however, its transient response is significantly slower, with very large peak and settling times (t_p = 1030 μs, t_s = 1130 μs), which limits its suitability for high-speed applications.

The design described in [28], based on VCII active elements, demonstrates excellent dynamic performance with very fast response (t_r = 0.334 μs, t_s = 2.05 μs) and minimal overshoot (0.55%). This improvement, on the other hand, comes with a high power consumption (235 mW) and is primarily limited to voltage mode. Similarly, the study in [29] reports extremely fast rise and settling times (t_r = 0.0052 μs, t_s = 0.18 μs) with zero overshoot, but it relies on a specialized DDCCTA device and does not report complete transient metrics (e.g., lacking peak time), which may restrict practical implementation and general applicability. In comparison, the proposed PID controller offers a well-balanced trade-off among performance, complexity, and power efficiency. It employs only three VDTAs and a small number of passive components (two resistors and three capacitors), maintaining a relatively simple structure suitable for integration. The transient response characteristics (t_r = 2.244 μs, t_p = 2.338 μs, and t_s = 2.537 μs) indicate a significantly faster response compared to [26,27]. Additionally, its performance remains comparable to high-speed designs like [28], all while avoiding excessive power consumption.

Importantly, the proposed controller achieves very low power dissipation at 0.972 mW, which is substantially lower than all compared designs. This feature makes it highly suitable for low-power and portable applications. Although its overshoot (11.11%) is higher than that of some designs [28,29], it is still comparable to other practical implementations such as [26,27]. This comparison indicates that the proposed controller maintains acceptable stability performance in typical control scenarios.

Furthermore, unlike several prior works that are restricted to a single operation mode, the proposed controller supports multiple modes (VM, TAM, TIM, and CM). This characteristic enhances flexibility and wider applicability in mixed-mode signal processing systems.

In summary, the results in Table 9 confirm that the proposed PID controller achieves an advantageous compromise between speed, power consumption, and implementation simplicity. It outperforms many recent designs in terms of energy efficiency while also maintaining competitive transient response characteristics.

8. Conclusions

This paper has introduced a compact and versatile VDTA-based mixed-mode inverse filter that can realize multiple inverse filtering responses within a single topology. The proposed circuit utilizes only three VDTAs along with a minimal number of passive components, while supporting operations in VM, TAM, TIM, and CM. This design offers high design flexibility and integration suitability. It successfully provides first-order inverse LP and HP, as well as second-order inverse BP characteristics, with tunable pole frequency and gain. The impact of non-idealities, particularly parasitic impedances, has been analytically examined to establish realistic operating conditions. Simulation results based on a 0.18 μm CMOS process show good agreement with theoretical predictions, demonstrating accurate frequency responses, low power consumption, orthogonal tunability, and satisfactory temperature and process robustness. Furthermore, the applicability of the proposed filter has been validated through the implementation of mixed-mode PID controllers, where improved transient performance and reduced steady-state error were achieved. Owing to its simplicity, tunability, and multifunction capability, the proposed design is well suited for modern analog signal processing and control system applications.