Search Results (871)

Silicon (Si), the cornerstone semiconductor in the micro-electronics industry, can provide a cost-efficient platform with mature technologies for photodetection in visible and near-infrared regions. However, its intrinsic properties, such as a narrow bandgap and the shallow penetration depth of ultraviolet (UV) light into its surface with surface trap states, remain challenges, rendering it unsuitable for effective UV light detection. Various techniques have been reported to circumvent these surface defect-induced difficulties. In addition, wide-bandgap semiconductors that favor UV light absorption in a solar-blind way have been combined with Si for UV light detection in order to retain the device’s compatibility with Si-CMOS processes, though it still faces challenges that need to be overcome. This review starts with concepts of basic parameters of photodetectors and categorizes UV photodetectors according to their detection mechanisms. We also present a review of wide-bandgap semiconductor-based UV light detectors and those based on Si, with a discussion of surface defect minimization. In addition, we review the hybrid structure of the two kinds, i.e., wide-bandgap semiconductors and Si, and discuss their properties that produce synergistic effects. Lastly, we provide conclusions and outlooks for the possible development of next-generation UV light detectors based on Si. Full article

In order to solve the problem of the efficiency reduction and complex manufacturing of traditional grating couplers under environmental temperature fluctuations, a Si₃N₄ high-efficiency grating coupler integrating a distributed Bragg reflector (DBR) and thermo-optical tuning layer is proposed. In this paper, the double-layer DBR is used to make the down-scattered light interfere with other light and reflect it back into the waveguide. The finite difference time domain (FDTD) method is used to simulate and optimize the key parameters such as grating period, duty cycle, incident angle and cladding thickness, achieving a coupling efficiency of −1.59 dB and a 3 dB bandwidth of 106 nm. In order to further enhance the temperature stability, the amorphous silicon (a-Si) thermo-optical material layer and titanium metal serpentine heater are embedded in the DBR. The reduction in coupling efficiency caused by fluctuations in environmental temperature is compensated via local temperature control. The simulation results show that within the wide temperature range from −55 °C to 150 °C, the compensated coupling efficiency fluctuation is less than 0.02 dB, and the center wavelength undergoes a blue shift. This design is compatible with complementary metal-oxide-semiconductor (CMOS) processes, which not only simplifies the fabrication process but also significantly improves device stability over a wide temperature range. This provides a feasible and efficient coupling solution for photonic integrated chips in non-temperature-controlled environments, such as optical communications, data centers, and automotive systems. Full article

To enhance the RF power properties of CMOS-compatible gold-free GaN devices, this work introduces a kind of GaN-on-Si HEMT with a low parasitic regrown ohmic contact technology. Attributed to the highly doped n⁺ InGaN regrown layer and smooth morphology of gold-free ohmic stacks, the lowest ohmic contact resistance (R_c) was presented as 0.072 Ω·mm. More importantly, low RF loss and low total dislocation density (TDD) of the Si-based GaN epitaxy were achieved by a designed two-step-graded (TSG) transition structure for the use of scaling-down devices in high-frequency applications. Finally, the fabricated GaN HEMTs on the Si substrate presented a maximum drain current (I_drain) of 1206 mA/mm, a peak transconductance (G_m) of 391 mS/mm, and a breakdown voltage (V_BR) of 169 V. The outstanding material and DC performances strongly encourage a maximum output power density (P_out) of 10.2 W/mm at 8 GHz and drain voltage (V_drain) of 50 V in active pulse mode, which, to our best knowledge, updates the highest power level for gold-free GaN devices on Si substrates. The power results reflect the reliable potential of low parasitic regrown ohmic contact technology for future large-scale CMOS-integrated circuits in RF applications. Full article

Colloidal quantum dots (CQDs) have attracted significant attention in optoelectronics due to their size-tunable bandgap, high photoluminescence quantum yield, and solution processability, which enable integration into compact and energy-efficient systems. This review consolidates recent progress in multifunctional CQD-based light-emitting devices and on-chip integration strategies. This review systematically examines fundamental CQD properties (quantum confinement, carrier dynamics, and core–shell heterostructures), key synthesis methods including hot injection, ligand-assisted reprecipitation, and microfluidic flow synthesis, and device innovations such as light-emitting field-effect transistors, light-emitting solar cells, and light-emitting memristors, alongside on-chip components including ongoing electrically pumped lasers and photodetectors. This review concludes that synergies in material engineering, device design, and system innovation are pivotal for next-generation optoelectronics, though challenges such as environmental instability, Auger recombination, and CMOS compatibility require future breakthroughs in atomic-layer deposition, 3D heterostructures, and data-driven optimization. Full article

Implantable medical devices present several technological challenges, one of the most critical being how to provide power supply and communication capabilities to a device hermetically sealed within the body. Using a battery as a power source represents a potential harm for the individual’s health because of possible toxic chemical release or overheating, and it requires periodic surgery for replacement. This paper proposes a batteryless implantable device powered by an inductive link and equipped with bidirectional wireless communication channels. The device, designed in a 180 nm CMOS process, is based on two different pairs of mutually coupled inductors that provide, respectively, power and a low-bitrate bidirectional communication link and a separate, high-bitrate, one-directional upstream connection. The main link is based on a 13.56 MHz carrier and allows power transmission and a half-duplex two-way communication at 106 kbps (downlink) and 30 kbps (uplink). The secondary link is based on a 27 MHz carrier, which provides one-way communication at 2.25 Mbps only in uplink. The low-bitrate links are needed to send commands and monitor the implanted system, while the high-bitrate link is required to receive a continuous stream of information from the implanted sensing devices. The microchip acts as a hub for power and data wireless transmission capable of managing up to four different neural recording and stimulation front ends, making the device employable in a complex, distributed, bidirectional neural prosthetic system. Full article

This paper proposes a balanced dynamic Time Division Multiple Access bus architecture with a novel selectable–sequence–counter arbitration circuit. Most existing dTDMA-related studies focus on wireless communications, which involve significantly different architectural assumptions, design constraints, and implementation platforms compared to digital bus systems. Our comparative analysis was carried out against the only available implementation in the literature, aligning to the target domain of digital buses. The proposed SSC-based arbiter, evaluated on a 65 nm CMOS process, demonstrates superior performance, achieving substantial reductions in area and power consumption with an approximated linear resource scaling as the number of connected devices to the bus increases, unlike the quadratic growth in the conventional architecture. Thus, this work offers a practical and yet efficient novel dTDMA architecture solution for on-chip communication. Full article

The growing number of connected devices has strained traditional radio frequency wireless networks, driving interest in alternative technologies such as optical wireless communications (OWC). Among OWC solutions, optical camera communication (OCC) stands out as a cost-effective option because it leverages existing devices equipped with cameras, such as smartphones and security systems, without requiring specialized hardware. This paper proposes a novel deep learning-based detection and classification model designed to optimize the receiver’s performance in an OCC system utilizing color-shift keying (CSK) modulation. The receiver was experimentally validated using an $8\times 8$ LED matrix transmitter and a CMOS camera receiver, achieving reliable communication over distances ranging from 30 cm to 3 m under varying ambient conditions. The system employed CSK modulation to encode data into eight distinct color-based symbols transmitted at fixed frequencies. Captured image sequences of these transmissions were processed through a YOLOv8-based detection and classification framework, which achieved $98.4$% accuracy in symbol recognition. This high precision minimizes transmission errors, validating the robustness of the approach in real-world environments. The results highlight OCC’s potential for low-cost applications, where high-speed data transfer and long-range are unnecessary, such as Internet of Things connectivity and vehicle-to-vehicle communication. Future work will explore adaptive modulation and coding schemes as well as the integration of more advanced deep learning architectures to improve data rates and system scalability. Full article

This paper introduces a compact analog configuration that concurrently realizes a mixed-mode biquadratic filter and a dual-mode quadrature oscillator (QO) by employing a single differential differencing gain amplifier (DDGA) and all-grounded passive components. The proposed design supports four fundamental operation modes—voltage-mode (VM), current-mode (CM), trans-impedance-mode (TIM), and trans-admittance-mode (TAM)—utilizing the same circuit topology without structural modifications. In filter operation, it offers low-pass, high-pass, band-pass, band-stop, and all-pass responses with orthogonal and electronic pole frequency and quality factor. In oscillator operation, it delivers simultaneous voltage and current quadrature outputs with independent tuning of oscillator frequency and condition. The grounded-component configuration simplifies layout and enhances its suitability for monolithic integration. Numerical simulations in a 0.18-μm CMOS process with ±0.9 V supply confirm theoretical predictions, demonstrating precise gain-phase characteristics, low total harmonic distortion (<7%), modest sensitivity to 5% component variations, and stable operation from −40 °C to 120 °C. These results, combined with the circuit’s low component count and integration suitability, suggest strong potential for future development in low-power IoT devices, adaptive communication front-ends, and integrated biomedical systems. Full article

As the CMOS technology approaches its physical and economic limits, further advancement of Moore’s Law for enhanced computing performance can no longer rely solely on smaller transistors and higher integration density. Instead, the computing landscape is poised for a fundamental transformation that transcends hardware scaling to embrace innovations in architecture, software, application-specific algorithms, and cross-disciplinary integration. Among the most promising enablers of this transition is non-volatile memory (NVM), which provides new technological pathways for restructuring the future of computing systems. Recent advancements in non-volatile memory (NVM) technologies, such as flash memory, Resistive Random-Access Memory (RRAM), and magneto-resistive RAM (MRAM), have significantly narrowed longstanding performance gaps while introducing transformative capabilities, including instant-on functionality, ultra-low standby power, and persistent data retention. These characteristics pave the way for developing more energy-efficient computing systems, heterogeneous memory hierarchies, and novel computational paradigms, such as in-memory and neuromorphic computing. Beyond isolated hardware improvements, integrating NVM at both the architectural and algorithmic levels would foster the emergence of intelligent computing platforms that transcend the limitations of traditional von Neumann architectures and device scaling. Driven by these advances, next-generation computing platforms powered by NVM are expected to deliver substantial gains in computational performance, energy efficiency, and scalability of the emerging data-centric architectures. These improvements align with the broader vision of both “More Moore” and “More than Moore”—extending beyond MOS device miniaturization to encompass architectural and functional innovation that redefines how performance is achieved at the end of CMOS device downsizing. Full article

Visible Light Positioning (VLP), leveraging Light-Emitting Diodes (LEDs) and smartphone CMOS cameras, provides a high-precision solution for indoor localization. However, existing systems face challenges in accuracy, latency, and robustness due to line-of-sight (LOS) limitations and inefficient signal encoding. To overcome these constraints, this paper introduces a real-time VLP framework that integrates Multi-Pulse Position Modulation (MPPM) with smartphone multi-sensor fusion. By employing MPPM, a high-efficiency encoding scheme, the proposed system transmits LED identifiers (LED-IDs) with reduced inter-symbol interference, enabling robust signal detection even under dynamic lighting conditions and at extended distances. The smartphone’s camera is a receiver that decodes the MPPM-encoded LED-ID, while accelerometer and magnetometer data compensate for device orientation and motion-induced errors. Experimental results demonstrate that the MPPM-driven approach achieves a decoding success rate of over 97% at distances up to 2.4 m, while maintaining a frame processing rate of 30 FPS and sub-35 ms latency. Furthermore, the method reduces angular errors through sensor fusion, yielding 2D positioning accuracy below 10 cm and vertical errors under 16 cm across diverse smartphone orientations. The synergy of MPPM’s spectral efficiency and multi-sensor correction establishes a new benchmark for VLP systems, enabling scalable deployment in real-world environments without requiring complex infrastructure. Full article

Sea surface roughness (SSR) retrieval is a frontier topic in the field of ocean remote sensing, and SSR retrieval based on multi angle, passive, visible spectrum remote sensing images has been proven to have potential applications. Traditional multi angle retrieval models ignored the nonlinear relationship between radiation and digital signals, resulting in low accuracy in SSR retrieval using visible spectrum remote sensing images. Therefore, we analyze the transmission characteristics of signals and random noise in sea surface imaging, establish signals and noise transmission models for typical sea surface imaging visible spectrum remote sensing systems using Complementary Metal Oxide Semiconductor (CMOS) and Time Delay Integration-Charge Coupled Device (TDI-CCD) sensors, and propose a model for SSR retrieval using multi angle passive visible spectrum remote sensing images. The proposed model can effectively suppress the noise behavior in the imaging link and improve the accuracy of SSR retrieval. Simulation experiments show that when simulating the retrieval of multi angle visible spectrum images obtained using CMOS or TDI-CCD imaging systems with four SSR levels of 0.02, 0.03, 0.04, and 0.05, the proposed model relative errors using two angles are decreased by 4.0%, 2.7%, 2.3%, and 2.0% and 6.5%, 4.3%, 3.7%, and 3.2%, compared with the relative errors of the model without considering noise behavior, which are 7.0%, 6.7%, 7.8%, and 9.0% and 9.5%, 8.3%, 9.0%, and 10.2%. When using more fitting data, the relative errors of the model were decreased by 5.0%, 2.7%, 2.5%, and 2.0% and 7.0%, 5.0%, 4.3%, and 3.2%, compared with the relative errors of the model without considering noise behavior, which are 8.5%, 7.0%, 8.0%, and 9.4%, and 10.0%, 8.7%, 9.3%, and 10.0%. Full article

Microscopy is a fundamental tool in biological research. However, conventional microscopes require manual operation and depend on user and equipment availability, limiting their suitability for continuous observation. Moreover, their size and complexity make them impractical for in situ experimentation. In this work, we present a novel, compact, affordable, and portable microscope that enables continuous in situ monitoring by being placed directly on biological samples. This chip-sized lensless holographic microscope (CLHM) is specifically designed to overcome the limitations of traditional microscopy. The device consists solely of an ultra-compact, state-of-the-art micro-LED display and a CMOS sensor, all enclosed within a 3D-printed housing. This unique light source enables a size that is markedly smaller than any comparable technology, allowing a resolution of 2.19 μm within a 7 mm distance between the light source and the camera. This paper demonstrates the CLHM’s versatility by monitoring in vitro models and performing whole-organism morphological analyses of small specimens. These experiments underscore its potential as an on-platform sensing device for continuous, in situ biological monitoring across diverse models. Full article

Resistive switching (RS) phenomena are nowadays one of the most studied topics in the area of microelectronics. It can be observed in Metal–Insulator–Metal (MIM) structures that are the basis of resistive switching random-access memories (RRAMs). In the case of commercial use of RRAMs, it is beneficial that the applied materials would have to be compatible with Complementary Metal-Oxide-Semiconductor (CMOS) technology. Fabricating methods of these materials can determine their stoichiometry and structural composition, which can have a detrimental impact on the electrical performance of manufactured devices. In this study, we present the influence of the Ar/N₂ ratio during reactive magnetron sputtering of titanium nitride (TiN) electrodes on the resistive switching behavior of MIM devices. We used silicon oxide (SiOx) as a dielectric layer, which was characterized by the same properties in all fabricated MIM structures. The composition of TiN thin layers was controlled by tuning the Ar/N₂ ratio during the deposition process. The fabricated conductive materials were characterized in terms of chemical and structural properties employing X-ray photoelectron spectroscopy (XPS) and X-ray diffraction (XRD) analysis. Structural characterization revealed that increasing the Ar content during the reactive sputtering process affects the crystallite size of the deposited TiN layer. The resulting crystallite sizes ranged from 8 Å to 757.4 Å. The I-V measurements of fabricated devices revealed that tuning the Ar/N₂ ratio during the deposition of TiN electrodes affects the RS behavior. Our work shows the importance of controlling the stoichiometry and structural parameters of electrodes on resistive switching phenomena. Full article

Parallel-type slew-rate enhancers (PSREs) improve the driving capability of operational transconductance amplifiers (OTAs) for large capacitive loads. While capacitive-boosting (CB) techniques enhance PSRE efficiency in fully-differential designs, their application to single-ended configurations—common in off-chip load driving—remains unexplored. This work identifies a critical limitation of standard CB in single-ended unity-gain buffers: severe slew-rate degradation due to large common-mode input swings. To overcome this, we propose a novel split CB (SCB) technique for single-ended PSREs that strategically divides the boosting capacitance. Simulated in a 0.18-µm CMOS process, the proposed method achieves a ×5.53 reduction in settling time compared to standard CB when driving a 1-nF load. With only 4 µA quiescent current under a 3.3-V supply, it attains a 1% settling time of 2.56 µs for 2.64-V steps, demonstrating robust performance across process-voltage-temperature variations. This technique enables low-power, high-speed interfaces for drivers of off-chip devices. Full article

Integrating two-dimensional transition-metal dichalcogenides with graphene is attractive for low-power memory and neuromorphic hardware, yet sequential wet transfer leaves polymer residues and high contact resistance. We demonstrate a complementary metal–oxide–semiconductor (CMOS)-compatible, transfer-free route in which an atomically thin amorphous MoS₂ precursor is RF-sputtered directly onto chemical vapor-deposited few-layer graphene and crystallized by confined-space sulfurization at 800 °C. Grazing-incidence X-ray reflectivity, Raman spectroscopy, and X-ray photoelectron spectroscopy confirm the formation of residue-free, three-to-four-layer 2H-MoS₂ (roughness: 0.8–0.9 nm) over 1.5 cm × 2 cm coupons. Lateral MoS₂/graphene devices exhibit reproducible non-volatile resistive switching with a set transition (SET) near +6 V and an analogue ON/OFF ≈2.1, attributable to vacancy-induced Schottky-barrier modulation. The single-furnace magnetron sputtering + sulfurization sequence avoids toxic H₂S, polymer transfer steps, and high-resistance contacts, offering a cost-effective pathway toward wafer-scale 2D memristors compatible with back-end CMOS temperatures. Full article