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Integrated Circuits and Systems for Smart Sensory Applications

A special issue of Sensors (ISSN 1424-8220). This special issue belongs to the section "Intelligent Sensors".

Deadline for manuscript submissions: closed (17 November 2021) | Viewed by 36132

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Special Issue Information

Dear Colleagues,

Connected intelligent sensing reshapes our society by empowering people with increasing new ways of mutual interactions. As integration technologies keep their scaling roadmap, the horizon of sensory applications is rapidly widening, thanks to myriad light-weight self-powered smart devices with high-connectivity capabilities. Furthermore, the cost-effective large-scale manufacturing associated with these integration technologies makes their usage in low-end and disposable sensing devices also possible. In any case, integrated circuits based on CMOS technologies is clearly the best candidate to supply the required smartness and to pioneer these emerging sensory systems. As a result, new challenges are arising around the design of these integrated circuits and systems for sensory applications in terms of low-power edge computing, remote and self-powering strategies, low-range wireless communications and low-cost device packaging.

This Special Issue aims to track the recent advances in application-specific integrated circuits and systems for smart sensory applications among, but not limited to, the following emerging topics:

  • wearable systems capable to combine physical and chemical sensing of the body and environment.
  • self-powered autonomous systems, including miniaturized sensing fuel cells, for the recognition of chemical analytes.
  • smart swallowable pills for in-body diagnostic and drug delivery.
  • implantable devices for multiparametric physiological monitoring and for neural signal recording and tracking.
  • disposables smart devices, such as sensing tags for perishable goods.
  • hybrid sensors combining smart integrated circuits and low-cost large-area printed electronics.
Dr. Francesc Serra-Graells
Dr. Michele Dei
Prof. Dr. Kyoungrok Cho

Guest Editors

Manuscript Submission Information

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Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Sensors is an international peer-reviewed open access semimonthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 2600 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • smart sensors
  • integrated circuits and systems
  • CMOS
  • wearable
  • self-powered
  • disposable
  • swallowable
  • implantable
  • printed electronics

Published Papers (10 papers)

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Research

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17 pages, 5885 KiB  
Article
Design of a Capacitance-to-Digital Converter Based on Iterative Delay-Chain Discharge in 180 nm CMOS Technology
by Mattia Cicalini, Massimo Piotto, Paolo Bruschi and Michele Dei
Sensors 2022, 22(1), 121; https://doi.org/10.3390/s22010121 - 24 Dec 2021
Cited by 1 | Viewed by 2927
Abstract
The design of advanced miniaturized ultra-low power interfaces for sensors is extremely important for energy-constrained monitoring applications, such as wearable, ingestible and implantable devices used in the health and medical field. Capacitive sensors, together with their correspondent digital-output readout interfaces, make no exception. [...] Read more.
The design of advanced miniaturized ultra-low power interfaces for sensors is extremely important for energy-constrained monitoring applications, such as wearable, ingestible and implantable devices used in the health and medical field. Capacitive sensors, together with their correspondent digital-output readout interfaces, make no exception. Here, we analyse and design a capacitance-to-digital converter, based on the recently introduced iterative delay-chain discharge architecture, showing the circuit inner operating principles and the correspondent design trade-offs. A complete design case, implemented in a commercial 180 nm CMOS process, operating at 0.9 V supply for a 0–250 pF input capacitance range, is presented. The circuit, tested by means of detailed electrical simulations, shows ultra-low energy consumption (≤1.884 nJ/conversion), excellent linearity (linearity error 15.26 ppm), good robustness against process and temperature corners (conversion gain sensitivity to process corners variation of 114.0 ppm and maximum temperature sensitivity of 81.9 ppm/°C in the −40 °C, +125 °C interval) and medium-low resolution of 10.3 effective number of bits, while using only 0.0192 mm2 of silicon area and employing 2.93 ms for a single conversion. Full article
(This article belongs to the Special Issue Integrated Circuits and Systems for Smart Sensory Applications)
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17 pages, 7360 KiB  
Article
A Low-Power Spiking Neural Network Chip Based on a Compact LIF Neuron and Binary Exponential Charge Injector Synapse Circuits
by Malik Summair Asghar, Saad Arslan and Hyungwon Kim
Sensors 2021, 21(13), 4462; https://doi.org/10.3390/s21134462 - 29 Jun 2021
Cited by 14 | Viewed by 4233
Abstract
To realize a large-scale Spiking Neural Network (SNN) on hardware for mobile applications, area and power optimized electronic circuit design is critical. In this work, an area and power optimized hardware implementation of a large-scale SNN for real time IoT applications is presented. [...] Read more.
To realize a large-scale Spiking Neural Network (SNN) on hardware for mobile applications, area and power optimized electronic circuit design is critical. In this work, an area and power optimized hardware implementation of a large-scale SNN for real time IoT applications is presented. The analog Complementary Metal Oxide Semiconductor (CMOS) implementation incorporates neuron and synaptic circuits optimized for area and power consumption. The asynchronous neuronal circuits implemented benefit from higher energy efficiency and higher sensitivity. The proposed synapse circuit based on Binary Exponential Charge Injector (BECI) saves area and power consumption, and provides design scalability for higher resolutions. The SNN model implemented is optimized for 9 × 9 pixel input image and minimum bit-width weights that can satisfy target accuracy, occupies less area and power consumption. Moreover, the spiking neural network is replicated in full digital implementation for area and power comparisons. The SNN chip integrated from neuron and synapse circuits is capable of pattern recognition. The proposed SNN chip is fabricated using 180 nm CMOS process, which occupies a 3.6 mm2 chip core area, and achieves a classification accuracy of 94.66% for the MNIST dataset. The proposed SNN chip consumes an average power of 1.06 mW—20 times lower than the digital implementation. Full article
(This article belongs to the Special Issue Integrated Circuits and Systems for Smart Sensory Applications)
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16 pages, 34212 KiB  
Article
Low-Power Wireless Sensor Network Using Fine-Grain Control of Sensor Module Power Mode
by Seongwon You, Jason K. Eshraghian, Herbert C. Iu and Kyoungrok Cho
Sensors 2021, 21(9), 3198; https://doi.org/10.3390/s21093198 - 04 May 2021
Cited by 8 | Viewed by 3850
Abstract
Wireless sensor nodes are heavily resource-constrained due to their edge form factor, which has motivated increasing battery life through low-power techniques. This paper proposes a power management method that leads to less energy consumption in an idle state than conventional power management systems [...] Read more.
Wireless sensor nodes are heavily resource-constrained due to their edge form factor, which has motivated increasing battery life through low-power techniques. This paper proposes a power management method that leads to less energy consumption in an idle state than conventional power management systems used in wireless sensor nodes. We analyze and benchmark the power consumption between Sleep, Idle, and Run modes. To reduce sensor node power consumption, we develop fine-grained power modes (FGPM) with five states which modulate energy consumption according to the sensor node’s communication status. We evaluate the proposed method on a test bench Mica2. As a result, the power consumed is 74.2% lower than that of conventional approaches. The proposed method targets the reduction of power consumption in IoT sensor modules with long sleep mode or short packet data in which most networks operate. Full article
(This article belongs to the Special Issue Integrated Circuits and Systems for Smart Sensory Applications)
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22 pages, 7940 KiB  
Article
Analysis and Reduction of Nonlinear Distortion in AC-Coupled CMOS Neural Amplifiers with Tunable Cutoff Frequencies
by Beata Trzpil-Jurgielewicz, Władysław Dąbrowski and Paweł Hottowy
Sensors 2021, 21(9), 3116; https://doi.org/10.3390/s21093116 - 30 Apr 2021
Viewed by 2043
Abstract
Integrated CMOS neural amplifiers are key elements of modern large-scale neuroelectronic interfaces. The neural amplifiers are routinely AC-coupled to electrodes to remove the DC voltage. The large resistances required for the AC coupling circuit are usually realized using MOSFETs that are nonlinear. Specifically, [...] Read more.
Integrated CMOS neural amplifiers are key elements of modern large-scale neuroelectronic interfaces. The neural amplifiers are routinely AC-coupled to electrodes to remove the DC voltage. The large resistances required for the AC coupling circuit are usually realized using MOSFETs that are nonlinear. Specifically, designs with tunable cutoff frequency of the input high‑pass filter may suffer from excessive nonlinearity, since the gate-source voltages of the transistors forming the pseudoresistors vary following the signal being amplified. Consequently, the nonlinear distortion in such circuits may be high for signal frequencies close to the cutoff frequency of the input filter. Here we propose a simple modification of the architecture of a tunable AC-coupled amplifier, in which the bias voltages Vgs of the transistors forming the pseudoresistor are kept constant independently of the signal levels, what results in significantly improved linearity. Based on numerical simulations of the proposed circuit designed in 180 nm technology we analyze the Total Harmonic Distortion levels as a function of signal frequency and amplitude. We also investigate the impact of basic amplifier parameters—gain, cutoff frequency of the AC coupling circuit, and silicon area—on the distortion and noise performance. The post-layout simulations of the complete test ASIC show that the distortion is very significantly reduced at frequencies near the cutoff frequency, when compared to the commonly used circuits. The THD values are below 1.17% for signal frequencies 1 Hz–10 kHz and signal amplitudes up to 10 mV peak-to-peak. The preamplifier area is only 0.0046 mm2 and the noise is 8.3 µVrms in the 1 Hz–10 kHz range. To our knowledge this is the first report on a CMOS neural amplifier with systematic characterization of THD across complete range of frequencies and amplitudes of neuronal signals recorded by extracellular electrodes. Full article
(This article belongs to the Special Issue Integrated Circuits and Systems for Smart Sensory Applications)
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15 pages, 6039 KiB  
Communication
A Low-Power 12-Bit 20 MS/s Asynchronously Controlled SAR ADC for WAVE ITS Sensor Based Applications
by Khuram Shehzad, Deeksha Verma, Danial Khan, Qurat Ul Ain, Muhammad Basim, Sung Jin Kim, Behnam Samadpoor Rikan, Young Gun Pu, Keum Cheol Hwang, Youngoo Yang and Kang-Yoon Lee
Sensors 2021, 21(7), 2260; https://doi.org/10.3390/s21072260 - 24 Mar 2021
Cited by 9 | Viewed by 3627
Abstract
A low power 12-bit, 20 MS/s asynchronously controlled successive approximation register (SAR) analog-to-digital converter (ADC) to be used in wireless access for vehicular environment (WAVE) intelligent transportation system (ITS) sensor based application is presented in this paper. To optimize the architecture with respect [...] Read more.
A low power 12-bit, 20 MS/s asynchronously controlled successive approximation register (SAR) analog-to-digital converter (ADC) to be used in wireless access for vehicular environment (WAVE) intelligent transportation system (ITS) sensor based application is presented in this paper. To optimize the architecture with respect to power consumption and performance, several techniques are proposed. A switching method which employs the common mode charge recovery (CMCR) switching process is presented for capacitive digital-to-analog converter (CDAC) part to lower the switching energy. The switching technique proposed in our work consumes 56.3% less energy in comparison with conventional CMCR switching method. For high speed operation with low power consumption and to overcome the kick back issue in the comparator part, a mutated dynamic-latch comparator with cascode is implemented. In addition, to optimize the flexibility relating to the performance of logic part, an asynchronous topology is employed. The structure is fabricated in 65 nm CMOS process technology with an active area of 0.14 mm2. With a sampling frequency of 20 MS/s, the proposed architecture attains signal-to-noise distortion ratio (SNDR) of 65.44 dB at Nyquist frequency while consuming only 472.2 µW with 1 V power supply. Full article
(This article belongs to the Special Issue Integrated Circuits and Systems for Smart Sensory Applications)
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12 pages, 3329 KiB  
Communication
A Digital Improvement—Trimming a Digital Temperature Sensor with EEPROM Reprogrammable Fuses
by Anca Mihaela Vasile (Dragan), Alina Negut, Adrian Tache and Gheorghe Brezeanu
Sensors 2021, 21(5), 1700; https://doi.org/10.3390/s21051700 - 02 Mar 2021
Cited by 2 | Viewed by 2428
Abstract
An EEPROM (electrically erasable programmable read-only memory) reprogrammable fuse for trimming a digital temperature sensor is designed in a 0.18-µm CMOS EEPROM. The fuse uses EEPROM memory cells, which allow multiple programming cycles by modifying the stored data on the digital trim codes [...] Read more.
An EEPROM (electrically erasable programmable read-only memory) reprogrammable fuse for trimming a digital temperature sensor is designed in a 0.18-µm CMOS EEPROM. The fuse uses EEPROM memory cells, which allow multiple programming cycles by modifying the stored data on the digital trim codes applied to the thermal sensor. By reprogramming the fuse, the temperature sensor can be adjusted with an increased trim variation in order to achieve higher accuracy. Experimental results for the trimmed digital sensor showed a +1.5/−1.0 ℃ inaccuracy in the temperature range of −20 to 125 ℃ for 25 trimmed DTS samples at 1.8 V by one-point calibration. Furthermore, an average mean of 0.40 ℃ and a standard deviation of 0.70 ℃ temperature error were obtained in the same temperature range for power supply voltages from 1.7 to 1.9 V. Thus, the digital sensor exhibits similar performances for the entire power supply range of 1.7 to 3.6 V. Full article
(This article belongs to the Special Issue Integrated Circuits and Systems for Smart Sensory Applications)
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19 pages, 4998 KiB  
Article
A Highly Accurate, Polynomial-Based Digital Temperature Compensation for Piezoresistive Pressure Sensor in 180 nm CMOS Technology
by Imran Ali, Muhammad Asif, Khuram Shehzad, Muhammad Riaz Ur Rehman, Dong Gyu Kim, Behnam Samadpoor Rikan, YoungGun Pu, Sang Sun Yoo and Kang-Yoon Lee
Sensors 2020, 20(18), 5256; https://doi.org/10.3390/s20185256 - 14 Sep 2020
Cited by 12 | Viewed by 4306
Abstract
Recently, piezoresistive-type (PRT) pressure sensors have been gaining attention in variety of applications due to their simplicity, low cost, miniature size and ruggedness. The electrical behavior of a pressure sensor is highly dependent on the temperature gradient which seriously degrades its reliability and [...] Read more.
Recently, piezoresistive-type (PRT) pressure sensors have been gaining attention in variety of applications due to their simplicity, low cost, miniature size and ruggedness. The electrical behavior of a pressure sensor is highly dependent on the temperature gradient which seriously degrades its reliability and reduces measurement accuracy. In this paper, polynomial-based adaptive digital temperature compensation is presented for automotive piezoresistive pressure sensor applications. The non-linear temperature dependency of a pressure sensor is accurately compensated for by incorporating opposite characteristics of the pressure sensor as a function of temperature. The compensation polynomial is fully implemented in a digital system and a scaling technique is introduced to enhance its accuracy. The resource sharing technique is adopted for minimizing controller area and power consumption. The negative temperature coefficient (NTC) instead of proportional to absolute temperature (PTAT) or complementary to absolute temperature (CTAT) is used as the temperature-sensing element since it offers the best temperature characteristics for grade 0 ambient temperature operating range according to the automotive electronics council (AEC) test qualification ACE-Q100. The shared structure approach uses an existing analog signal conditioning path, composed of a programmable gain amplifier (PGA) and an analog-to-digital converter (ADC). For improving the accuracy over wide range of temperature, a high-resolution sigma-delta ADC is integrated. The measured temperature compensation accuracy is within ±0.068% with full scale when temperature varies from −40 °C to 150 °C according to ACE-Q100. It takes 37 µs to compute the temperature compensation with a clock frequency of 10 MHz. The proposed technique is integrated in an automotive pressure sensor signal conditioning chip using a 180 nm complementary metal–oxide–semiconductor (CMOS) process. Full article
(This article belongs to the Special Issue Integrated Circuits and Systems for Smart Sensory Applications)
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21 pages, 11804 KiB  
Article
A Highly Reliable, 5.8 GHz DSRC Wake-Up Receiver with an Intelligent Digital Controller for an ETC System
by Imran Ali, Muhammad Asif, Muhammad Riaz Ur Rehman, Danial Khan, Huo Yingge, Sung Jin Kim, YoungGun Pu, Sang-Sun Yoo and Kang-Yoon Lee
Sensors 2020, 20(14), 4012; https://doi.org/10.3390/s20144012 - 19 Jul 2020
Cited by 4 | Viewed by 3976
Abstract
In this article, a highly reliable radio frequency (RF) wake-up receiver (WuRx) is presented for electronic toll collection (ETC) applications. An intelligent digital controller (IDC) is proposed as the final stage for improving WuRx reliability and replacing complex analog blocks. With IDC, high [...] Read more.
In this article, a highly reliable radio frequency (RF) wake-up receiver (WuRx) is presented for electronic toll collection (ETC) applications. An intelligent digital controller (IDC) is proposed as the final stage for improving WuRx reliability and replacing complex analog blocks. With IDC, high reliability and accuracy are achieved by sensing and ensuring the successive, configurable number of wake-up signal cycles before enabling power-hungry RF transceiver. The IDC and range communication (RC) oscillator current consumption is reduced by a presented self-hibernation technique during the non-wake-up period. For accommodating wake-up signal frequency variation and enhancing WuRx accuracy, a digital hysteresis is incorporated. To avoid uncertain conditions during poor and false wake-up, a watch-dog timer for IDC self-recovery is integrated. During wake-up, the digital controller consumes 34.62 nW power and draws 38.47 nA current from a 0.9 V supply. In self-hibernation mode, its current reduces to 9.7 nA. It is fully synthesizable and needs 809 gates for its implementation in a 130 nm CMOS process with a 94 × 82 µm2 area. The WuRx measured power consumption is 2.48 µW, has −46 dBm sensitivity, and a 0.484 mm² chip area. Full article
(This article belongs to the Special Issue Integrated Circuits and Systems for Smart Sensory Applications)
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Review

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36 pages, 8154 KiB  
Review
A Review of Microelectronic Systems and Circuit Techniques for Electrical Neural Recording Aimed at Closed-Loop Epilepsy Control
by Reza Ranjandish and Alexandre Schmid
Sensors 2020, 20(19), 5716; https://doi.org/10.3390/s20195716 - 08 Oct 2020
Cited by 11 | Viewed by 5418
Abstract
Closed-loop implantable electronics offer a new trend in therapeutic systems aimed at controlling some neurological diseases such as epilepsy. Seizures are detected and electrical stimulation applied to the brain or groups of nerves. To this aim, the signal recording chain must be very [...] Read more.
Closed-loop implantable electronics offer a new trend in therapeutic systems aimed at controlling some neurological diseases such as epilepsy. Seizures are detected and electrical stimulation applied to the brain or groups of nerves. To this aim, the signal recording chain must be very carefully designed so as to operate in low-power and low-latency, while enhancing the probability of correct event detection. This paper reviews the electrical characteristics of the target brain signals pertaining to epilepsy detection. Commercial systems are presented and discussed. Finally, the major blocks of the signal acquisition chain are presented with a focus on the circuit architecture and a careful attention to solutions to issues related to data acquisition from multi-channel arrays of cortical sensors. Full article
(This article belongs to the Special Issue Integrated Circuits and Systems for Smart Sensory Applications)
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Other

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13 pages, 5361 KiB  
Letter
An Ultra-Wide Load Range Voltage Converter Using Proactive Phase Frequency Modulation for IoT Sensors
by Saad Arslan, Syed Asmat Ali Shah and HyungWon Kim
Sensors 2020, 20(21), 6279; https://doi.org/10.3390/s20216279 - 04 Nov 2020
Cited by 1 | Viewed by 1934
Abstract
Modern sensor nodes have multiple operating states, which causes a conventional voltage converter to perform poorly over a wide load range of the operating states. This paper proposes a voltage converter whose switching frequency and output voltage are proactively adjusted to maintain high [...] Read more.
Modern sensor nodes have multiple operating states, which causes a conventional voltage converter to perform poorly over a wide load range of the operating states. This paper proposes a voltage converter whose switching frequency and output voltage are proactively adjusted to maintain high conversion efficiency. This allows the converter to exploit a wider frequency range to cover a wide load range. In addition, the proposed converter uses multiple smaller capacitor banks and employs multiphase operation to provide low output ripple voltage. A distributed topology for non-overlapping signal generation is proposed and used in the converter to minimize the number of wires running from connecting the controller to the converter. The proposed voltage converter has been implemented in a chip using a 0.13 um CMOS process. The measurement results demonstrate the ability to support a wide load range of 10 µA to 10 mA, for switching frequencies ranging from 100 kHz to 200 MHz, while providing an efficiency of above 80%. Full article
(This article belongs to the Special Issue Integrated Circuits and Systems for Smart Sensory Applications)
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