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Article

A Low-Power Spiking Neural Network Chip Based on a Compact LIF Neuron and Binary Exponential Charge Injector Synapse Circuits

1
Department of Electronics Engineering, Chungbuk National University, Chungdae-ro 1, Seowon-gu, Cheongju 28644, Korea
2
Department of Electrical and Computer Engineering, Abbottabad Campus, COMSATS University Islamabad, University Road, Tobe Camp, Abbottabad 22044, Pakistan
3
Department of Electrical and Computer Engineering, COMSATS University Islamabad, Park Road, Tarlai Kalan, Islamabad 45550, Pakistan
*
Author to whom correspondence should be addressed.
Academic Editor: Marcin Woźniak
Sensors 2021, 21(13), 4462; https://doi.org/10.3390/s21134462
Received: 12 June 2021 / Revised: 23 June 2021 / Accepted: 24 June 2021 / Published: 29 June 2021
(This article belongs to the Special Issue Integrated Circuits and Systems for Smart Sensory Applications)
To realize a large-scale Spiking Neural Network (SNN) on hardware for mobile applications, area and power optimized electronic circuit design is critical. In this work, an area and power optimized hardware implementation of a large-scale SNN for real time IoT applications is presented. The analog Complementary Metal Oxide Semiconductor (CMOS) implementation incorporates neuron and synaptic circuits optimized for area and power consumption. The asynchronous neuronal circuits implemented benefit from higher energy efficiency and higher sensitivity. The proposed synapse circuit based on Binary Exponential Charge Injector (BECI) saves area and power consumption, and provides design scalability for higher resolutions. The SNN model implemented is optimized for 9 × 9 pixel input image and minimum bit-width weights that can satisfy target accuracy, occupies less area and power consumption. Moreover, the spiking neural network is replicated in full digital implementation for area and power comparisons. The SNN chip integrated from neuron and synapse circuits is capable of pattern recognition. The proposed SNN chip is fabricated using 180 nm CMOS process, which occupies a 3.6 mm2 chip core area, and achieves a classification accuracy of 94.66% for the MNIST dataset. The proposed SNN chip consumes an average power of 1.06 mW—20 times lower than the digital implementation. View Full-Text
Keywords: spiking neural network; leaky integrate and fire; neuromorphic; artificial neural networks; artificial intelligence; image classification; CMOS spiking neural network; leaky integrate and fire; neuromorphic; artificial neural networks; artificial intelligence; image classification; CMOS
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MDPI and ACS Style

Asghar, M.S.; Arslan, S.; Kim, H. A Low-Power Spiking Neural Network Chip Based on a Compact LIF Neuron and Binary Exponential Charge Injector Synapse Circuits. Sensors 2021, 21, 4462. https://doi.org/10.3390/s21134462

AMA Style

Asghar MS, Arslan S, Kim H. A Low-Power Spiking Neural Network Chip Based on a Compact LIF Neuron and Binary Exponential Charge Injector Synapse Circuits. Sensors. 2021; 21(13):4462. https://doi.org/10.3390/s21134462

Chicago/Turabian Style

Asghar, Malik S., Saad Arslan, and Hyungwon Kim. 2021. "A Low-Power Spiking Neural Network Chip Based on a Compact LIF Neuron and Binary Exponential Charge Injector Synapse Circuits" Sensors 21, no. 13: 4462. https://doi.org/10.3390/s21134462

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