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18 pages, 6152 KiB

Open AccessArticle

0.5 V, Low-Power Bulk-Driven Current Differencing Transconductance Amplifier

by Montree Kumngern, Fabian Khateb and Tomasz Kulej

Sensors 2024, 24(21), 6852; https://doi.org/10.3390/s24216852 - 25 Oct 2024

Viewed by 787

This paper presents a novel low-power low-voltage current differencing transconductance amplifier (CDTA). To achieve a low-voltage low-power CDTA, the BD-MOST (bulk-driven MOS transistor) technique operating in a subthreshold region is used. The proposed CDTA is designed in 0.18 µm CMOS technology, can operate [...] Read more.

This paper presents a novel low-power low-voltage current differencing transconductance amplifier (CDTA). To achieve a low-voltage low-power CDTA, the BD-MOST (bulk-driven MOS transistor) technique operating in a subthreshold region is used. The proposed CDTA is designed in 0.18 µm CMOS technology, can operate with a supply voltage of 0.5 V, and consumes 1.05 μW of power. The proposed CDTA is used to realize a current-mode universal filter. The filter can realize five standard transfer functions of low-pass, band-pass, high-pass and band-stop, and all-pass from the same circuit. Neither component-matching conditions nor input signals of the inverse type are required to realize these filter functions. The current-mode filter offers low-input and high-output impedance and uses grounded capacitors. The natural frequency and quality factor of the filters can be orthogonally controlled. The proposed CDTA and its applications are simulated using SPICE to confirm the feasibility and functionality of the new circuits. Full article

(This article belongs to the Special Issue CMOS Integrated Circuits for Sensor Applications)

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21 pages, 12495 KiB

Open AccessArticle

Direct Current to Digital Converter (DIDC): A Current Sensor

by Saeid Karimpour, Michael Sekyere, Isaac Bruce, Emmanuel Nti Darko, Degang Chen, Colin C. McAndrew, Doug Garrity, Xiankun Jin, Ilhan Hatirnaz and Chen He

Sensors 2024, 24(21), 6789; https://doi.org/10.3390/s24216789 - 22 Oct 2024

Viewed by 986

Abstract

This paper introduces a systematic approach to the design of Direct Current-to-Digital Converter (DIDC) specifically engineered to overcome the limitations of traditional current measurement methodologies in System-on-Chip (SoC) designs. The proposed DIDC addresses critical challenges such as high power consumption, large area requirements, [...] Read more.

This paper introduces a systematic approach to the design of Direct Current-to-Digital Converter (DIDC) specifically engineered to overcome the limitations of traditional current measurement methodologies in System-on-Chip (SoC) designs. The proposed DIDC addresses critical challenges such as high power consumption, large area requirements, and the need for intermediate analog signals. By incorporating a current mirror in a cascode topology and managing the current across multiple binary-sized branches with the Successive Approximation Register (SAR) logic, the design achieves precise current measurement. A simple comparator, coupled with an isolation circuit, ensures accurate and reliable sensing. Fabricated using the TSMC 180 nm process, the DIDC achieves 8-bit precision without the need for nonlinearity calibration, showcasing remarkable energy efficiency with an energy per conversion of 1.52 pJ, power consumption of 117 µW, and a compact area of 0.016 mm². This innovative approach not only reduces power consumption and area, but also provides a scalable and efficient solution for next-generation semiconductor technologies. The ability to conduct online measurements during both standard operations and in-field conditions significantly enhances the performance and reliability of SoCs, making this DIDC a promising advancement in the field. Full article

(This article belongs to the Special Issue CMOS Integrated Circuits for Sensor Applications)

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17 pages, 7887 KiB

Open AccessArticle

Integrated Precision High-Frequency Signal Conditioner for Variable Impedance Sensors

by Miodrag Brkić, Jelena Radić, Kalman Babković and Mirjana Damnjanović

Sensors 2024, 24(20), 6501; https://doi.org/10.3390/s24206501 - 10 Oct 2024

Viewed by 799

Abstract

In this paper, a signal conditioner intended for use in variable impedance sensors is presented. First, an inductive linear displacement sensor design is described, and the signal conditioner discrete realization is presented. Second, based on this system’s requirements, the integrated conditioner is proposed. [...] Read more.

In this paper, a signal conditioner intended for use in variable impedance sensors is presented. First, an inductive linear displacement sensor design is described, and the signal conditioner discrete realization is presented. Second, based on this system’s requirements, the integrated conditioner is proposed. The conditioner comprises an amplifier, a tunable band-pass filter, and a precision high-frequency AC-DC converter. It is designed in a low-cost AMS 0.35 µm CMOS process. The presented conditioner measures the sensor’s impedance magnitude by using a simplified variation of the sensor voltage and current vector measurement. It can be used for the real-time measurement of fast sensors, having small output impedance. The post-layout simulation results show that the integrated conditioner has an inductance measurement range from 10 nH to 550 nH with a nonlinearity of 1.2%. The operating frequency in this case was 8 MHz, but the circuit can be easily adjusted to different operating frequencies (due to the tunable filter). The designed IC area is 500 × 330 μm², and the total power consumption is 93.8 mW. Full article

(This article belongs to the Special Issue CMOS Integrated Circuits for Sensor Applications)

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14 pages, 5703 KiB

Open AccessArticle

A Reconfigurable, Nonlinear, Low-Power, VCO-Based ADC for Neural Recording Applications

by Reza Shokri, Yarallah Koolivand, Omid Shoaei, Daniele D. Caviglia and Orazio Aiello

Sensors 2024, 24(19), 6161; https://doi.org/10.3390/s24196161 - 24 Sep 2024

Viewed by 1208

Abstract

Neural recording systems play a crucial role in comprehending the intricacies of the brain and advancing treatments for neurological disorders. Within these systems, the analog-to-digital converter (ADC) serves as a fundamental component, converting the electrical signals from the brain into digital data that [...] Read more.

Neural recording systems play a crucial role in comprehending the intricacies of the brain and advancing treatments for neurological disorders. Within these systems, the analog-to-digital converter (ADC) serves as a fundamental component, converting the electrical signals from the brain into digital data that can be further processed and analyzed by computing units. This research introduces a novel nonlinear ADC designed specifically for spike sorting in biomedical applications. Employing MOSFET varactors and voltage-controlled oscillators (VCOs), this ADC exploits the nonlinear capacitance properties of MOSFET varactors, achieving a parabolic quantization function that digitizes the noise with low resolution and the spikes with high resolution, effectively suppressing the background noise present in biomedical signals. This research aims to develop a reconfigurable, nonlinear voltage-controlled oscillator (VCO)-based ADC, specifically designed for implantable neural recording systems used in neuroprosthetics and brain–machine interfaces. The proposed design enhances the signal-to-noise ratio and reduces power consumption, making it more efficient for real-time neural data processing. By improving the performance and energy efficiency of these devices, the research contributes to the development of more reliable medical technologies for monitoring and treating neurological disorders. The quantization step of the ADC spans from 44.8 mV in the low-amplitude range to 1.4 mV in the high-amplitude range. The circuit was designed and simulated utilizing a 180 nm CMOS process; however, no physical prototype has been fabricated at this stage. Post-layout simulations confirm the expected performance. Occupying a silicon area is 0.09 mm². Operating at a sampling frequency of 16 kS/s and a supply voltage of 1 volt, this ADC consumes 62.4 µW. Full article

(This article belongs to the Special Issue CMOS Integrated Circuits for Sensor Applications)

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26 pages, 4522 KiB

Open AccessArticle

an-QNA: An Adaptive Nesterov Quasi-Newton Acceleration-Optimized CMOS LNA for 65 nm Automotive Radar Applications

by Unal Aras, Lee Sun Woo, Tahesin Samira Delwar, Abrar Siddique, Anindya Jana, Yangwon Lee and Jee-Youl Ryu

Sensors 2024, 24(18), 6141; https://doi.org/10.3390/s24186141 - 23 Sep 2024

Viewed by 927

Abstract

An adaptive Nesterov quasi-Newton acceleration (an-QNA)-optimized low-noise amplifier (LNA) is proposed in this paper. An optimized single-ended-to-differential two-stage LNA circuit is presented. It includes an improved post-linearization (I_PL) technique to enhance the linearity. Traditional methods like conventional quasi-Newton (c-QN) often suffer [...] Read more.

An adaptive Nesterov quasi-Newton acceleration (an-QNA)-optimized low-noise amplifier (LNA) is proposed in this paper. An optimized single-ended-to-differential two-stage LNA circuit is presented. It includes an improved post-linearization (I_PL) technique to enhance the linearity. Traditional methods like conventional quasi-Newton (c-QN) often suffer from slow convergence and the tendency to get trapped in local minima. However, the proposed an-QNA method significantly accelerates the convergence speed. Furthermore, in this paper, modifications have been made to the an-QNA algorithm using a quadratic estimation to guarantee global convergence. The optimized an-QNA-based LNA, using standard 65 nm CMOS technology, achieves a simulated gain of 17.5 dB, a noise figure (NF) of 3.7 dB, and a 1 dB input compression point (IP₁dB) of −13.1 dBm. It is also noted that the optimized LNA achieves a measured gain of 12.9 dB and an NF of 4.98 dB, and the IP₁dB is −17.8 dB. The optimized LNA has a chip area of 0.67 mm². Full article

(This article belongs to the Special Issue CMOS Integrated Circuits for Sensor Applications)

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12 pages, 3900 KiB

Open AccessArticle

Wide Voltage Swing Potentiostat with Dynamic Analog Ground to Expand Electrochemical Potential Windows in Integrated Microsystems

by Ehsan Ashoori, Derek Goderis, Anna Inohara and Andrew J. Mason

Sensors 2024, 24(9), 2902; https://doi.org/10.3390/s24092902 - 1 May 2024

Cited by 1 | Viewed by 3442

Abstract

Electrochemical measurements are vital to a wide range of applications such as air quality monitoring, biological testing, food industry, and more. Integrated circuits have been used to implement miniaturized and low-power electrochemical potentiostats that are suitable for wearable devices. However, employing modern integrated [...] Read more.

Electrochemical measurements are vital to a wide range of applications such as air quality monitoring, biological testing, food industry, and more. Integrated circuits have been used to implement miniaturized and low-power electrochemical potentiostats that are suitable for wearable devices. However, employing modern integrated circuit technologies with low supply voltage precludes the utilization of electrochemical reactions that require a higher potential window. In this paper, we present a novel circuit architecture that utilizes dynamic voltage at the working electrode of an electrochemical cell to effectively enhance the supported voltage range compared to traditional designs, increasing the cell voltage range by 46% and 88% for positive and negative cell voltages, respectively. In return, this facilitates a wider range of bias voltages in an electrochemical cell, and, therefore, opens integrated microsystems to a broader class of electrochemical reactions. The circuit was implemented in 180 nm technology and consumes 2.047 mW of power. It supports a bias potential range of 1.1 V to −2.12 V and cell potential range of 2.41 V to −3.11 V that is nearly double the range in conventional designs. Full article

(This article belongs to the Special Issue CMOS Integrated Circuits for Sensor Applications)

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16 pages, 7806 KiB

Open AccessArticle

Smart Temperature Sensor Design and High-Density Water Temperature Monitoring in Estuarine and Coastal Areas

by Bozhi Wang, Huayang Cai, Qi Jia, Huimin Pan, Bo Li and Linxi Fu

Sensors 2023, 23(17), 7659; https://doi.org/10.3390/s23177659 - 4 Sep 2023

Cited by 2 | Viewed by 2512

Abstract

Acquiring in situ water temperature data is an indispensable and important component for analyzing thermal dynamics in estuarine and coastal areas. However, the long-term and high-density monitoring of water temperature is costly and technically challenging. In this paper, we present the design, calibration, [...] Read more.

Acquiring in situ water temperature data is an indispensable and important component for analyzing thermal dynamics in estuarine and coastal areas. However, the long-term and high-density monitoring of water temperature is costly and technically challenging. In this paper, we present the design, calibration, and application of the smart temperature sensor TS-V1, a low-power yet low-cost temperature sensor for monitoring the spatial–temporal variations of surface water temperatures and air temperatures in estuarine and coastal areas. The temperature output of the TS-V1 sensor was calibrated against the Fluke-1551A sensor developed in the United States and the CTD-Diver sensor developed in the Netherlands. The results show that the accuracy of the TS-V1 sensor is 0.08 °C, while sensitivity tests suggest that the TS-V1 sensor (comprising a titanium alloy shell with a thermal conductivity of 7.6 W/(m °C)) is approximately 0.31~0.54 s/°C slower than the CTD-Diver sensor (zirconia shell with thermal conductivity of 3 W/(m °C)) in measuring water temperatures but 6.92~10.12 s/°C faster than the CTD-Diver sensor in measuring air temperatures. In addition, the price of the proposed TS-V1 sensor is only approximately 1 and 0.3 times as much as the established commercial sensors, respectively. The TS-V1 sensor was used to collect surface water temperature and air temperature in the western part of the Pearl River Estuary from July 2022 to September 2022. These data wells captured water and air temperature changes, frequency distributions, and temperature characteristics. Our sensor is, thus, particularly useful for the study of thermal dynamics in estuarine and coastal areas. Full article

(This article belongs to the Special Issue CMOS Integrated Circuits for Sensor Applications)

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12 pages, 4456 KiB

Open AccessCommunication

Design of a Current Sensing System with TIA Gain of 160 dBΩ and Input-Referred Noise of 1.8 pA_rms for Biosensor

by Donggyu Kim, Sungjun Byun, Younggun Pu, Hyungki Huh, Yeonjae Jung, Seokkee Kim and Kang-Yoon Lee

Sensors 2023, 23(6), 3019; https://doi.org/10.3390/s23063019 - 10 Mar 2023

Viewed by 3362

Abstract

This paper proposes a high-gain low-noise current signal detection system for biosensors. When the biomaterial is attached to the biosensor, the current flowing through the bias voltage is changed so that the biomaterial can be sensed. A resistive feedback transimpedance amplifier (TIA) is [...] Read more.

This paper proposes a high-gain low-noise current signal detection system for biosensors. When the biomaterial is attached to the biosensor, the current flowing through the bias voltage is changed so that the biomaterial can be sensed. A resistive feedback transimpedance amplifier (TIA) is used for the biosensor requiring a bias voltage. Current changes in the biosensor can be checked by plotting the current value of the biosensor in real time on the self-made graphical user interface (GUI). Even if the bias voltage changes, the input voltage of the analog to digital converter (ADC) does not change, so it is designed to plot the current of the biosensor accurately and stably. In particular, for multi-biosensors with an array structure, a method of automatically calibrating the current between biosensors by controlling the gate bias voltage of the biosensors is proposed. Input-referred noise is reduced using a high-gain TIA and chopper technique. The proposed circuit achieves 1.8 pA_rms input-referred noise with a gain of 160 dBΩ and is implemented in a TSMC 130 nm CMOS process. The chip area is 2.3 mm², and the power consumption of the current sensing system is 12 mW. Full article

(This article belongs to the Special Issue CMOS Integrated Circuits for Sensor Applications)

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