Negative Capacitance Field-Effect Transistors
A special issue of Micromachines (ISSN 2072-666X). This special issue belongs to the section "E：Engineering and Technology".
Deadline for manuscript submissions: closed (31 August 2021) | Viewed by 318
Special Issue Editor
Special Issue Information
Dear Colleagues,
High-performance logic transistors require a large on-state current in order to guarantee fast operation, and, simultaneously, a suppressed off-state current in order to reduce the stand-by power consumption. Unfortunately, the subthreshold swing—the efficiency of a transistor switching between on and off states—is limited to 60 mV/dec by the so-called Boltzmann tyranny. One possible solution to circumvent this fundamental physics limit, as proposed by S. Salahuddin and S. Datta in 2008, is to build negative capacitance field-effect transistors (NC-FET) by introducing a ferroelectric dielectric material into the gate stack. The experimental progress of demonstrating a sub-60 mV/dec steep-slope NC-FET has only seen a boom in the last several years, and yet, it is in the spotlight for future CMOS technology nodes. Furthermore, versatile ferroelectric materials with a novel functionality have also recently been explored, such as neuromorphic devices and non-volatile memory. Yet, many technical issues of NC-FET are still being debated, such as domain dynamics, operation speed, and device reliability. This Special Issue calls for research papers, communications, and review articles that focus on the following: (1) experimental progress in NC-FET with innovative materials, device structures, and fabrication processes; (2) exploration of novel functionality using NC-FET and ferroelectricity in general; and (3) critical examination of the microscopic mechanisms of ferroelectric switching and the impact on FET operations.
Dr. Gang Qiu
Guest Editor
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Keywords
- steep-slope transistors
- ferroelectricity
- CMOS scaling
- low power consumption
- neural network
- non-volatile memory
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