Search for Articles:
Title / Keyword
Author / Affiliation / Email
Journal
Article Type
 
 
Advanced Search
 
Section
Special Issue
Volume
Issue
Number
Page
 
4.7
3.4
Journals
Micromachines
Special Issues
Microcontrollers and Microprocessors: The Advanced System on the Chip
share announcement

Microcontrollers and Microprocessors: The Advanced System on the Chip

A special issue of Micromachines (ISSN 2072-666X). This special issue belongs to the section "E：Engineering and Technology".

Deadline for manuscript submissions: closed (30 November 2023) | Viewed by 9016

Special Issue Editor

Prof. Dr. Muhammad Rashid

E-Mail Website
Guest Editor
Department of Computer Engineering, Umm Al-Qura University, Makkah 21421, Saudi Arabia
Interests: blockchain

Special Issue Information

Dear Colleagues,

Due to an ever-increasing growth in component technologies (very large-scale integration), design/development flow (top-down, bottom-up, and meet-in-the-middle), and programming frameworks, modern microprocessors-based systems have touched new horizons. In other words, novel system-on-a-chip (SoC) solutions, in terms of applications as well as architecture, are emerging. From an application point of view, this includes but is not limited to the Internet of Things (IoT), hardware security (classical as well as post-quantum), intrusion detection in networks, acceleration of machine learning algorithms, cloud computing, ambient intelligence, and edge computing. From an architectural and development point of view, it includes but is not limited to hardware/software co-design, hardware and software co-verification, platform-based design, high-level synthesis, model-driven development, virtual prototyping, reconfigurable computing, application-specific processors, FPGA prototyping, and so on. Furthermore, the critical SoC design performance parameters are lower power, high speed, and reduced area. Accordingly, this Special Issue seeks to showcase research papers, communications, and review articles that focus on novel developments in advanced SoC, revolving around microprocessors and microcontrollers. 

Prof. Dr. Muhammad Rashid
Guest Editor

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Micromachines is an international peer-reviewed open access monthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 2600 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • system-on-a-chip
  • Internet of Things
  • microprocessor-based systems
  • device technologies
  • programming paradigms
  • architectures for machine learning
  • architectures for machine network security
  • architectures for hardware security
  • ASICs
  • ASIPs
  • FPGA
  • GPU

Published Papers (5 papers)

Download All Papers
Order results
Result details
Show export options expand_more Show export options expand_less
Select all
Export citation of selected articles as:

Research

15 pages, 4490 KiB  
Article
Novel Second-Order Fully Differential All-Pass Filter Using CNTFETs
by Muhammad I. Masud, Iqbal A. Khan, Syed Abdul Moiz and Waheed A. Younis
Micromachines 2023, 14(10), 1873; https://doi.org/10.3390/mi14101873 - 29 Sep 2023
Viewed by 837
Abstract
In this paper, a new carbon nanotube field effect transistor (CNTFET)-based second-order fully differential all-pass filter circuit is presented. The realized filter uses CNTFET-based transconductors and grounded capacitors. An active-only second-order fully differential all-pass filter circuit topology is also presented by replacing the [...] Read more.
In this paper, a new carbon nanotube field effect transistor (CNTFET)-based second-order fully differential all-pass filter circuit is presented. The realized filter uses CNTFET-based transconductors and grounded capacitors. An active-only second-order fully differential all-pass filter circuit topology is also presented by replacing the grounded capacitance with a CNTFET-based varactor to achieve filter tunability. By controlling the varactor capacitance, active-only second-order fully differential all-pass filter tunability in the range of 15 GHz to 27.5 GHz is achieved. The proposed active-only circuit works on -oltage, low-power dissipation and high tunable pole frequency. The realized circuit operations are verified through the HPSPICE simulation tool. Deng’s CNTFET model is utilized to verify the filter performances at the 16 nm technology node. It is seen that the proposed filter simulation justifies the theoretical predictions and works efficiently in the deep-submicron technology. Full article
(This article belongs to the Special Issue Microcontrollers and Microprocessors: The Advanced System on the Chip)
►▼ Show Figures

Figure 1

14 pages, 911 KiB  
Article
RisCO2: Implementation and Performance Evaluation of RISC-V Processors for Low-Power CO2 Concentration Sensing
by Ricardo Núñez-Prieto, David Castells-Rufas and Lluís Terés-Terés
Micromachines 2023, 14(7), 1371; https://doi.org/10.3390/mi14071371 - 04 Jul 2023
Viewed by 2018
Abstract
In the field of embedded systems, energy efficiency is a critical requirement, particularly for battery-powered devices. RISC-V processors have gained popularity due to their flexibility and open-source nature, making them an attractive choice for embedded applications. However, not all RISC-V processors are equally [...] Read more.
In the field of embedded systems, energy efficiency is a critical requirement, particularly for battery-powered devices. RISC-V processors have gained popularity due to their flexibility and open-source nature, making them an attractive choice for embedded applications. However, not all RISC-V processors are equally energy-efficient, and evaluating their performance in specific use cases is essential. This paper presents RisCO2, an RISC-V implementation optimized for energy efficiency. It evaluates its performance compared to other RISC-V processors in terms of resource utilization and energy consumption in a signal processing application for nondispersive infrared (NDIR) CO2 sensors.The processors were implemented in the PULPino SoC and synthesized using Vivado IDE. RisCO2 is based on the RV32E_Zfinx instruction set and was designed from scratch by the authors specifically for low-power signal demodulation in CO2 NDIR sensors. The other processors are Ri5cy, Micro-riscy, and Zero-riscy, developed by the PULP team, and CV32E40P (derived from Ri5cy) from the OpenHW Group, all of them widely used in the RISC-V community. Our experiments showed that RisCO2 had the lowest energy consumption among the five processors, with a 53.5% reduction in energy consumption compared to CV32E40P and a 94.8% reduction compared to Micro-riscy. Additionally, RisCO2 had the lowest FPGA resource utilization compared to the best-performing processors, CV32E40P and Ri5cy, with a 46.1% and a 59% reduction in LUTs, respectively. Our findings suggest that RisCO2 is a highly energy-efficient RISC-V processor for NDIR CO2 sensors that require signal demodulation to enhance the accuracy of the measurements. The results also highlight the importance of evaluating processors in specific use cases to identify the most energy-efficient option. This paper provides valuable insights for designers of energy-efficient embedded systems using RISC-V processors. Full article
(This article belongs to the Special Issue Microcontrollers and Microprocessors: The Advanced System on the Chip)
►▼ Show Figures

Figure 1

19 pages, 24709 KiB  
Article
Hardware Trojan Mitigation Technique in Network-on-Chip (NoC)
by Musharraf Hussain, Naveed Khan Baloach, Gauhar Ali, Mohammed ElAffendi, Imed Ben Dhaou, Syed Sajid Ullah and Mueen Uddin
Micromachines 2023, 14(4), 828; https://doi.org/10.3390/mi14040828 - 08 Apr 2023
Cited by 2 | Viewed by 2731
Abstract
Due to globalization in the semiconductor industry, malevolent modifications made in the hardware circuitry, known as hardware Trojans (HTs), have rendered the security of the chip very critical. Over the years, many methods have been proposed to detect and mitigate these HTs in [...] Read more.
Due to globalization in the semiconductor industry, malevolent modifications made in the hardware circuitry, known as hardware Trojans (HTs), have rendered the security of the chip very critical. Over the years, many methods have been proposed to detect and mitigate these HTs in general integrated circuits. However, insufficient effort has been made for hardware Trojans (HTs) in the network-on-chip. In this study, we implement a countermeasure to congeal the network-on-chip hardware design in order to prevent changes from being made to the network-on-chip design. We propose a collaborative method which uses flit integrity and dynamic flit permutation to eliminate the hardware Trojan inserted into the router of the NoC by a disloyal employee or a third-party vendor corporation. The proposed method increases the number of received packets by up to 10% more compared to existing techniques, which contain HTs in the destination address of the flit. Compared to the runtime HT mitigation method, the proposed scheme also decreases the average latency for the hardware Trojan inserted in the flit’s header, tail, and destination field up to 14.7%, 8%, and 3%, respectively. Full article
(This article belongs to the Special Issue Microcontrollers and Microprocessors: The Advanced System on the Chip)
►▼ Show Figures

Figure 1

14 pages, 1207 KiB  
Article
A Heterogeneity-Aware Replacement Policy for the Partitioned Cache on Asymmetric Multi-Core Architectures
by Juan Fang, Han Kong, Huijing Yang, Yixiang Xu and Min Cai
Micromachines 2022, 13(11), 2014; https://doi.org/10.3390/mi13112014 - 18 Nov 2022
Viewed by 1087
Abstract
In an asymmetric multi-core architecture, multiple heterogeneous cores share the last-level cache (LLC). Due to the different memory access requirements among heterogeneous cores, the LLC competition is more intense. In the current work, we propose a heterogeneity-aware replacement policy for the partitioned cache [...] Read more.
In an asymmetric multi-core architecture, multiple heterogeneous cores share the last-level cache (LLC). Due to the different memory access requirements among heterogeneous cores, the LLC competition is more intense. In the current work, we propose a heterogeneity-aware replacement policy for the partitioned cache (HAPC), which reduces the mutual interference between cores through cache partitioning, and tracks the shared reuse state of each cache block within the partition at runtime to guide the replacement policy to keep cache blocks shared by multiple cores in multithreaded programs. In the process of updating the reuse state, considering the difference of memory accesses to LLC by heterogeneous cores, the cache replacement policy tends to keep cache blocks required by big cores, to better improve the LLC access efficiency of big cores. Compared with LRU and the SRCP, which are the state-of-the-art cache replacement algorithms, the performance of big cores can be significantly improved by HAPC when running multithreaded programs, while the impact on little cores is almost negligible, thus improving the overall performance of the system. Full article
(This article belongs to the Special Issue Microcontrollers and Microprocessors: The Advanced System on the Chip)
►▼ Show Figures

Figure 1

29 pages, 11669 KiB  
Article
Anticipative QoS Control: A Self-Reconfigurable On-Chip Communication
by Wen-Chung Tsai, Hsiao-En Lin, Ying-Cherng Lan and Sao-Jie Chen
Micromachines 2022, 13(10), 1669; https://doi.org/10.3390/mi13101669 - 04 Oct 2022
Viewed by 1015
Abstract
A self-reconfigurable Network-on-Chip (NoC) architecture that supports anticipative Quality of Service (QoS) control with penetrative switch ability is proposed to enhance the performance of bidirectional-channel NoC communication while supporting prioritized packet transmission services. The anticipative QoS control not only allows each communication channel [...] Read more.
A self-reconfigurable Network-on-Chip (NoC) architecture that supports anticipative Quality of Service (QoS) control with penetrative switch ability is proposed to enhance the performance of bidirectional-channel NoC communication while supporting prioritized packet transmission services. The anticipative QoS control not only allows each communication channel to be dynamically self-configured to transmit flits in either direction for a better channel utilization of on-chip hardware resources, but also enhances the latency performance for QoS services. The proposed anticipative control is based on penetratingly observing channel direction requests of routers that is two hops away from the current one. The added ability enables a router to allocate high-priority packets to a dedicated virtual channel and then rapidly bypass it to the next destination router. The provided flexibility of packet switch promises better channel bandwidth utilization, lower packet delivery latency, and furthermore guarantees the high-priority packets being served with a better QoS. Accordingly, in this paper, an enhanced NoC architecture supporting the hybrid anticipative QoS, penetrative switch, and bidirectional-channel control, namely Anticipative QoS Bidirectional-channel NoC (AQ-BiNoC) is presented. Tested with cycle-accurate synthetic traffic patterns, significant performance enhancement has been observed when the proposed AQ-BiNoC architecture is compared against conventional NoC designs. Full article
(This article belongs to the Special Issue Microcontrollers and Microprocessors: The Advanced System on the Chip)
►▼ Show Figures

Figure 1

Show export options expand_more Show export options expand_less
Select all
Export citation of selected articles as:
 
Displaying articles 1-5
Back to TopTop