A Ka-Band SiGe BiCMOS Quasi-F − 1 Power Ampliﬁer Using a Parasitic Capacitance Cancellation Technique †

: This paper deals with the design, analysis, and implementation of a Ka-band, single-stage, quasi-inverse class F power ampliﬁer (PA). A detailed methodology for the evaluation of the active device’s output capacitance is described, enabling the designing of a second-harmonically tuned load and resulting in enhanced performance. A simpliﬁed model for the extraction of time-domain intrinsic voltage and current waveforms at the output of the main active core is introduced, enforcing the implementation process of the proposed quasi-inverse class F technique. The PA is fabricated in a 130 nm SiGe BiCMOS technology with f T / f max = 250/370 GHz and it is suitable for 5G applications. It achieves 33% peak power-added efﬁciency ( PAE ), 18.8 dBm saturation output power P sat , and 14.7 dB maximum large-signal power gain G at the operating frequency of 38 GHz. The PA’s response is also tested under a modulated-signal excitation and simulation results are denoted in this paper. The chip size is 0.605 × 0.712 mm 2 including all pads.


Introduction
The surge in consumer demand for mobile data, as well as their preference for superior performance, enhanced quality, and increased reliability, has led to a continual rise in the need for elevated data rates and reduced latency [1]. This demand has been a major driver for Federal Communication Committee (FCC) to announce procedures for mm-wave auctions and define the 5G new radio specifications [2]. Ka-band (26.5-40 GHz) is one of the mm-wave bands of interest, since it can support higher data rate communication, lower latency, and smaller equipment size [3]. The final scope behind the efforts of the research community in the Ka-band circuit technologies is to enable various applications, such as space telescope, close-range targeting radars, satellite communications, and fifth-generation enhanced mobile broadband applications (eMBB) [4,5].
The power amplifier (PA) is an essential component in the mm-wave transmitter chain, as it contributes significantly to power consumption and linearity [6]. In 5G wireless systems, the utilization of complex modulated signals that possess a high peak-to-average power ratio (PAPR) necessitates the power amplifiers to sustain high efficiency while operating over a broad range of power at back-off. This requirement arises because the PAs need to operate in such a way that they can accommodate the high variations in signal power that are inherent in signals with high PAPR. This is important in order to ensure that the system can operate with a high level of performance, even under challenging conditions [7]. However, developing highly efficient silicon-based mm-wave PAs that can offer satisfactory PAE even at power back-off (PBO) is a challenging task. The reason behind this challenge is not only the inherent trade-off between break-down voltages

Ideal Quasi-F −1 Power Amplifier
A conventional inverse class F PA is defined as ideal if the ideal harmonic-impedance conditions are realized at the output node of the active device under test. More specifically, not only a proper transistor's biasing is required, but also an infinite number of oddharmonic and even-harmonic tank resonators are necessary to be included in the output network of an ideal inverse class F PA. In such a case, control of an infinite number of even and odd harmonics are realized, resulting in zero overlapping of the square current and half-sinusoidal voltage waveforms across the active device [12]. The latter impose 100% efficiency and, thus, zero power dissipation. However, it is noteworthy to highlight that only a finite number of harmonics will be present at the transistor's load in practice. The above restriction comes from the band-limiting behavior of the passive output network as well as the chip area limitations [13]. As follows, nonideal square current and halfsinusoidal voltage waveforms are present across the active device under test and, thus, power proportional to the V-I overlap is dissipated. An interesting solution to enhance the power profile of higher harmonics is presented in [14], where cascaded p-n junctions for carrier injection engineering with poly-silicon are used. Table 1 summarizes the theoretical maximum efficiencies that can be achieved for various combinations of voltage and current harmonic components that are present at transistor's load. The analysis and calculation of the presented efficiencies can be found in [10]. Due to the restrictions mentioned above, most of the inverse class F PAs realized in practice limit the harmonics control up to the third of a fundamental frequency, setting the upper limit of their maximum efficiency at 75% [13,[15][16][17]. A quasi-inverse class F power amplifier imitates by half the behavior of a conventional inverse class F power amplifier concerning the harmonically tuned output termination. The distinctive feature of the proposed PA class is its ability to regulate only the second harmonic component of the voltage output across the active device, which streamlines the design process for the output-matching network. Unlike conventional inverse class F power amplifiers, the proposed PA class does not utilize a third harmonic resonator in the output current, avoiding the insertion of additional losses during high-frequency operation. The limited quality factor (Q) of passive components frequently causes the third harmonic resonator to cancel the expected improvement in efficiency. According to Table 1, the upper limit of the proposed quasi-inverse class F is 66.7%. However, this efficiency limit is reduced even more, as it happens in the case of the conventional inverse class F PA, due to finite knee and breakdown voltages of the active device as well as the resistive losses of the passive load network.

Modelling of the Active Device
To achieve an accurate modeling of a mm-wave PA, it is crucial to thoroughly examine the main amplifying core or active module of each stage, as well as the electromagnetic (EM) characterization of its passive structures. By considering the active module as a voltage-dependent current source with an input and output admittance Y in = G in + jB in and Y out = G out + jB out , respectively (Figure 1a) [18], a "loop gain" analysis can be performed at node X not only to assess stability, but also to estimate the output admittance. This analysis involves "breaking" the circuit at the desired node while still maintaining overall performance. The result of the described process can provide insight into the output admittance (Y out ). Such an analysis is beneficial in the circuit design flow, especially for multiple-stage PAs with or without feedback loops (Figure 1b) compared to the conventional large-signal S-parameter analysis (LSSP), which is not able to provide information regarding the input and output impedances of the intermediate stages, since it calculates the coefficients related only to the defined terminations.
The amplifying core model of the proposed single-stage PA is depicted in Figure 1c, and it incorporates the cascode topology as a single active device (AD). By separating the AD from the output-matching network (OMN), the output capacitance (C out ) can be determined as: where ω is the angular frequency. The presented ideal RF choke provides a transparent dc current path. As follows, we can determine the input and output impedances of the device under test while the input power is being varied. For that purpose, we can perform a harmonic balance simulation in which the proposed nonlinear circuit is represented as a superposition of harmonic components and the steady-state behavior of each harmonic component is analyzed separately. Once the steady-state behavior of each harmonic component has been determined, the output admittance can be calculated by dividing the harmonic voltage across the desired nodes by the corresponding harmonic current at each harmonic frequency. This allows us to accurately capture the changes in the device's output capacitance in relation to its driving power, thereby enhancing the precision of the design process. capacitance in relation to its driving power, thereby enhancing the precision of the design process. The results of the harmonic balance "loop gain" analysis, performed over a frequency range of 37-40 GHz, are presented in Figure 2. The figure displays the variation in the output capacitance of our active device with respect to the input power ( ) sweep. It should be mentioned that the active device under test includes all the layout parasitics imposed by transistors' via and the interconnects between the common-emitter (CE) and common-base (CB) HBT of the cascode structure. To ensure stability at the desired frequency band, ideal conjugate matching is employed at the input of the active device and a 15 Ω series resistor is inserted to the base of the CE HBT 1 . The results indicate that is approximately 115 fF at low input power, while, at the operating point where the power gain is 1-dB compressed (~ 4 − 5 dBm), is found to be in the range of 120 − 125 fF.  The results of the harmonic balance "loop gain" analysis, performed over a frequency range of 37-40 GHz, are presented in Figure 2. The figure displays the variation in the output capacitance C out of our active device with respect to the input power (P in ) sweep. It should be mentioned that the active device under test includes all the layout parasitics imposed by transistors' via and the interconnects between the common-emitter (CE) and common-base (CB) HBT of the cascode structure. To ensure stability at the desired frequency band, ideal conjugate matching is employed at the input of the active device and a 15 Ω series resistor is inserted to the base of the CE HBT Q 1 . The results indicate that C out is approximately 115 fF at low input power, while, at the operating point where the power gain is 1-dB compressed ( ∼ 4-5 dBm), C out is found to be in the range of 120-125 fF. capacitance in relation to its driving power, thereby enhancing the precision of the design process. The results of the harmonic balance "loop gain" analysis, performed over a frequency range of 37-40 GHz, are presented in Figure 2. The figure displays the variation in the output capacitance of our active device with respect to the input power ( ) sweep. It should be mentioned that the active device under test includes all the layout parasitics imposed by transistors' via and the interconnects between the common-emitter (CE) and common-base (CB) HBT of the cascode structure. To ensure stability at the desired frequency band, ideal conjugate matching is employed at the input of the active device and a 15 Ω series resistor is inserted to the base of the CE HBT 1 . The results indicate that is approximately 115 fF at low input power, while, at the operating point where the power gain is 1-dB compressed (~ 4 − 5 dBm), is found to be in the range of 120 − 125 fF. vs. the available input power . Figure 2. Output capacitance C out vs. the available input power P in .
The validity of the above results can be straightforwardly confirmed by verifying that the extracted output capacitance is effectively cancelled out by the required inductance [19]: By conducting a swept power load pull analysis at 38 GHz, it was found that the power contours at the 1dB compression point have a center located at impedance Z Load = 13.9 + j22.4 Ω. However, after replacing the rf choke component with an ideal inductance of approximately 146 pH, the load pull contours are centered around the real axis at the optimum load Z Load = 50 + j0 Ω, as depicted in Figure 3 and discussed in [8]. This change in load impedance can be mathematically explained using the established equations for converting series to parallel impedance: The validity of the above results can be straightforwardly confirmed by verifying that the extracted output capacitance is effectively cancelled out by the required inductance [19]: By conducting a swept power load pull analysis at 38 GHz, it was found that the power contours at the 1dB compression point have a center located at impedance = 13.9 + 22.4 Ω. However, after replacing the rf choke component with an ideal inductance of approximately 146 , the load pull contours are centered around the real axis at the optimum load ′ = 50 + 0 Ω , as depicted in Figure 3 and discussed in [8]. This change in load impedance can be mathematically explained using the established equations for converting series to parallel impedance: Considering the load Pull analysis as a benchmark for validating the discovery process of , it is important to highlight that the proposed method based on the loop gain analysis of a single harmonic balance (HB) simulation has been found to produce more accurate results in comparison to the conventional large-signal s-parameter (LSSP) simulation. This novel method for investigating provides the ability to create a highly accurate model of PA classes that are harmonically tuned and highly efficient, such as Class F, F −1 , and E, as referenced in [20]. Figure 4 depicts the proposed single-stage, second-harmonically tuned, 37-40 GHz, quasi-F −1 power amplifier. The circuit features a cascode topology as the selected active device, a simple but effective cascode current mirror serving as a bias network, and a Ttype input-matching network. Additionally, the PA schematic incorporates an output harmonically tuned load to achieve an optimal 50 Ω fundamental impedance and an open- Considering the load Pull analysis as a benchmark for validating the discovery process of C out , it is important to highlight that the proposed method based on the loop gain analysis of a single harmonic balance (HB) simulation has been found to produce more accurate results in comparison to the conventional large-signal s-parameter (LSSP) simulation. This novel method for investigating C out provides the ability to create a highly accurate model of PA classes that are harmonically tuned and highly efficient, such as Class F, F −1 , and E, as referenced in [20]. Figure 4 depicts the proposed single-stage, second-harmonically tuned, 37-40 GHz, quasi-F −1 power amplifier. The circuit features a cascode topology as the selected active device, a simple but effective cascode current mirror serving as a bias network, and a T-type input-matching network. Additionally, the PA schematic incorporates an output harmonically tuned load to achieve an optimal 50 Ω fundamental impedance and an open-circuit second harmonic load. Both the input and output ports are terminated with a 50 Ω impedance. circuit second harmonic load. Both the input and output ports are terminated with a 50 Ω impedance. In the following subsections, each part of the circuit is analyzed in both schematic and physical layout levels.

Proposed Quasi-Inverse Class F Power Amplifier
It is worth mentioning that the design steps that followed for the present work form a robust methodology for designing and fabricating harmonically tuned PAs in various technology nodes for potential performance improvements. For instance, scaling down to a smaller technology node, such as 90 nm SiGe BiCMOS process, can offer improved response in terms of higher cutoff frequency, lower noise figure, and increased power density. This can translate into higher overall performance (output power and power gain) and efficiency for the PA. However, there are also some potential trade-offs to consider, such as increased device mismatch and increased power dissipation. On the one hand, device mismatch can be a significant issue when scaling down to a smaller technology node, as the smaller devices can exhibit greater variation in their electrical characteristics. This can lead to reduced gain, higher noise figure, and decreased linearity in the PA. On the other hand, smaller devices can lead to higher power density, which, in turn, can result in higher temperatures and increased power dissipation and reliability issues.

Supply Voltage
Aiming for a maximum output power at the saturation point of 20 dBm on a 50 Ω load, which is considered as the input impedance of SISO transmitter antenna, the required voltage amplitude at the fundamental is: According to [13], the maximum PA efficiency is achieved when the voltage amplitude at second harmonic is 2 ≈ 0.354 • and is given by: The quasi-F −1 PA was designed and fabricated in Infineon's 130 nm SiGe BiCMOS process. The process includes high-speed NPN HBTs with a unity gain frequency of f T = 250 GHz and a maximum frequency of oscillation f max = 370 GHz. The breakdown voltages of the provided HBTs are BV CEO = 1.8 V and BV CBO = 5.3 V. The layer stackup profile includes six copper metal layers and a 1.0 µm aluminum layer serving as the top metal. In the following subsections, each part of the circuit is analyzed in both schematic and physical layout levels.
It is worth mentioning that the design steps that followed for the present work form a robust methodology for designing and fabricating harmonically tuned PAs in various technology nodes for potential performance improvements. For instance, scaling down to a smaller technology node, such as 90 nm SiGe BiCMOS process, can offer improved response in terms of higher cutoff frequency, lower noise figure, and increased power density. This can translate into higher overall performance (output power and power gain) and efficiency for the PA. However, there are also some potential trade-offs to consider, such as increased device mismatch and increased power dissipation. On the one hand, device mismatch can be a significant issue when scaling down to a smaller technology node, as the smaller devices can exhibit greater variation in their electrical characteristics. This can lead to reduced gain, higher noise figure, and decreased linearity in the PA. On the other hand, smaller devices can lead to higher power density, which, in turn, can result in higher temperatures and increased power dissipation and reliability issues.

Supply Voltage V cc
Aiming for a maximum output power at the saturation point of 20 dBm on a 50 Ω load, which is considered as the input impedance of SISO transmitter antenna, the required voltage amplitude at the fundamental is: According to [13], the maximum PA efficiency is achieved when the voltage amplitude at second harmonic is V 2nd ≈ 0.354·V f und and is given by: where V knee is the knee voltage of the active device and V CC the supply voltage. After taking a 700 mV knee voltage margin into consideration due to cascode configuration of our active device, Equation (8) implies that, in maximizing V cc , the maximum efficiency increases too. Consequently, a 3.3 V supply voltage is selected, since, as it is imposed from the particular technology rules, it is the maximum allowable supply voltage for safe and reliable operation. It should be noticed that the AD's collector will experience a maximum of approximately 7.2 V of sinusoidal peaking. This peak will not cause any issues, as the base node of the selected AD will be terminated with a finite resistance through a DC bias network, providing a path for discharging the base to ground and preventing base charge accumulation. This, in turn, will avoid early collector impact ionization. The breakdown voltage of the active device will realistically be limited by BV CBO , which is exceptionally high in the case of a cascode topology composed of SiGe HBTs. Furthermore, the supply voltage is fed into our circuit via an aluminum pad, while diode circuits provide the required ESD protection.

Cascode Topology
The cascode topology has been selected as the main amplifying core for its numerous advantages. One of the key factors that motivated this choice was the higher gain and reduction in the Miller's effect, which enhances the stability of the active device, as highlighted in references [18,21].
The size of Q 1,2 has been carefully selected to deliver an output power of more than 18 dBm when biased in a deep class AB point, also known as the "sweet spot" [10]. This bias point allows the HBT to produce a maximum current at the first harmonic, similar to when it is biased in a class A point, while also reducing the maximum collector current of the third harmonic [18]. The bases of Q 1,2 are biased at approximately 0.81 V and 1.65 V, respectively, resulting in a cascode branch that conducts approximately 12 mA of quiescent collector current. The effective emitter length of the selected double-emitter HBTs (CBEBEBC) is 6 bl · 2 · 2.8 µm, resulting in a current density of approximately 11.5 mA/µm 2 at maximum f T = 250 GHz when the active device is driven close to 1 dB compression point (OP 1dB = 18.6 dBm). The described biasing leads to the AD conducting I DC = 52 mA at 1 dB compression point, maintaining a power gain of around 16 dB at 38 GHz.
It is worth mentioning that the intrinsic interconnects of the HBTs can be proven crucial not only to efficiency, but also to the optimal impedance matching at the input and output of our AD. Thus, the via interconnects were EM simulated and their effects were taken into consideration for an accurate modeling of the HBTs.

Bias Circuit
The proposed bias network is depicted in Figure 4 with a dot line. It is a simple yet effective current mirror that consists of the transistors Q b1 , Q b2 , TaN resistors R bias , R 1−4 , MIM capacitors C 1,2 , and a large inductor L bias . The size of the included HBTs and resistors determine the dc voltages used for biasing of the cascode AD. More specifically, = 15, generating the aforementioned dc voltages 0.81 V and 1.65 V at the bases of Q 1 , Q 2 , respectively. Furthermore, a large octagonal inductor L bias realized in top metal isolates the bias circuit from the active device and the rf path, while the decoupling capacitors C 1 = 5 pF and C 2 = 1 pF provide a low impedance path to the ground at the Ka-band.
It is noteworthy to highlight that a parasitic extraction process has been conducted on all elements contributing to the direct current path, including HBTs and resistors, while components contributing to the rf path have been EM simulated.

Output-Matching Network
The implementation of the proposed OMN is based on [15] and adopts a harmonically tuned circuitry, offering a transparent current path for the first harmonic as well as an effective short circuit of the second harmonic.
The identification of the parasitic capacitance C p of the active device is vital for determining the optimal values of the components that form the output network. This capacitance can be derived and authenticated through the techniques described in Section 2 with ease. Cancelling out the parasitic capacitance C p via the inductor L p1 , the optimum load impedance is transferred close to the real axis of the Smith Chart.
Upon the completion of the parasitic capacitance C p extraction process, the calculation of the optimal inductances and capacitances of the output-matching network becomes a matter of simple procedure. At the fundamental operating frequency f 0 , the short-circuit termination located at one end of the quarter-wavelength line (λ⁄4) transforms into an open circuit at its opposite end. As a result, the OMN transforms into a series configuration consisting of the shunt L p1 -C p tank in conjunction with L s = L s1 + L s2 and C s , thereby constituting a dual f 0 resonator (as depicted in Figure 5a). It is worth noting that the inductor L p2 cancels out the parasitic capacitance C PAD = 60 fF that is inherent to the output rf pad. Moreover, the inductor L p1 resonates out the parasitic capacitance C p , while the series resonator L s -C s provides a clear pathway for the transmission of the fundamental component of the current from the generator device (Q 1 , Q 2 ) to the 50 Ω load.

Output-Matching Network
The implementation of the proposed OMN is based on [15] and adopts a harmoni cally tuned circuitry, offering a transparent current path for the first harmonic as well a an effective short circuit of the second harmonic.
The identification of the parasitic capacitance of the active device is vital for de termining the optimal values of the components that form the output network. This ca pacitance can be derived and authenticated through the techniques described in Section with ease. Cancelling out the parasitic capacitance via the inductor 1 , the optimum load impedance is transferred close to the real axis of the Smith Chart.
Upon the completion of the parasitic capacitance extraction process, the calcula tion of the optimal inductances and capacitances of the output-matching network be comes a matter of simple procedure. At the fundamental operating frequency 0 , th short-circuit termination located at one end of the quarter-wavelength line (λ⁄4) trans forms into an open circuit at its opposite end. As a result, the OMN transforms into a serie configuration consisting of the shunt 1 -tank in conjunction with = 1 + 2 and , thereby constituting a dual 0 resonator (as depicted in Figure 5a). It is worth noting that the inductor 2 cancels out the parasitic capacitance = 60 that is inheren to the output rf pad. Moreover, the inductor 1 resonates out the parasitic capacitanc , while the series resonator -provides a clear pathway for the transmission of th fundamental component of the current from the generator device ( 1 , 2 ) to the 50 Ω load. At the second harmonic frequency, the quarter-wavelength line transforms into short circuit, thereby disconnecting the PA from the output load. This transformation i effectively depicted in Figure 5b and results in the conversion of the load network into parallel second harmonic resonator composed of 1 in conjunction with 1 and thereby providing the active device's transistors with an extremely high impedance ( 2 = ∞) at the second harmonic. Table 2 provides a concise summary of the values of the pas sive components of the OMN utilized in this study, as well as the corresponding Q-factor at the fundamental. High Q-factors of the passive components are desirable in order to minimize the resistive losses of the output path and, thus, moderate the PA's efficiency degradation. For that purpose, T-line inductors constitute both f0 and 2f0 resonators, sinc their quality factors are significantly higher (typical ~30-35) compared to on-chip spira inductors (typical ~20-25).  At the second harmonic frequency, the quarter-wavelength line transforms into a short circuit, thereby disconnecting the PA from the output load. This transformation is effectively depicted in Figure 5b and results in the conversion of the load network into a parallel second harmonic resonator composed of L p1 in conjunction with L s1 and C p , thereby providing the active device's transistors with an extremely high impedance (Z 2 = ∞) at the second harmonic. Table 2 provides a concise summary of the values of the passive components of the OMN utilized in this study, as well as the corresponding Q-factors at the fundamental. High Q-factors of the passive components are desirable in order to minimize the resistive losses of the output path and, thus, moderate the PA's efficiency degradation. For that purpose, T-line inductors constitute both f 0 and 2f 0 resonators, since their quality factors are significantly higher (typical~30-35) compared to on-chip spiral inductors (typical~20-25).  Figure 6 demonstrates the 3D final layout view of the proposed output-matching network. In order to reduce the resistive losses and the capacitive coupling to ground, the top metal (M6) is used for the inductors and the signal path of the λ/4 transmission line, while the reference plane of the transmission line is realized in M4. Finally, the whole structure is EM simulated and phenomena such as capacitive coupling to ground, cross-talk, and mutual inductance have been taken into consideration. Figure 6 demonstrates the 3D final layout view of the proposed output-matching network. In order to reduce the resistive losses and the capacitive coupling to ground, the top metal (M6) is used for the inductors and the signal path of the 4 ⁄ transmission line, while the reference plane of the transmission line is realized in M4. Finally, the whole structure is EM simulated and phenomena such as capacitive coupling to ground, crosstalk, and mutual inductance have been taken into consideration.

Input-Matching Network
The designed input-matching network (IMN) shown in Figure 4 is a simple T-type network consisting of a 200 μm open stub and a 410 μm series transmission line, as well as an MIM capacitor = 110 fF. The above matching network achieves a narrowband matching around 38 GHz between the source load and the main amplifier. The final 3D view of the proposed IMN is presented in Figure 7. As previously, the 50 Ω transmission lines are realized with M6 and M4 and the whole network is EM simulated.

Intrinsic Voltage and Current Waveforms
The intrinsic collector current and voltage waveforms in the time domain, after the compensation of parasitic capacitance , provide valuable insights into the performance of the active device when it is connected to a harmonically tuned load. The schematic model utilized to obtain the voltage and current waveforms at the output of the

Input-Matching Network
The designed input-matching network (IMN) shown in Figure 4 is a simple T-type network consisting of a 200 µm open stub and a 410 µm series transmission line, as well as an MIM capacitor C in = 110 fF. The above matching network achieves a narrowband matching around 38 GHz between the source load and the main amplifier. The final 3D view of the proposed IMN is presented in Figure 7. As previously, the 50 Ω transmission lines are realized with M6 and M4 and the whole network is EM simulated. metal (M6) is used for the inductors and the signal path of the 4 ⁄ transmission line, while the reference plane of the transmission line is realized in M4. Finally, the whole structure is EM simulated and phenomena such as capacitive coupling to ground, crosstalk, and mutual inductance have been taken into consideration.

Input-Matching Network
The designed input-matching network (IMN) shown in Figure 4 is a simple T-type network consisting of a 200 μm open stub and a 410 μm series transmission line, as well as an MIM capacitor = 110 fF. The above matching network achieves a narrowband matching around 38 GHz between the source load and the main amplifier. The final 3D view of the proposed IMN is presented in Figure 7. As previously, the 50 Ω transmission lines are realized with M6 and M4 and the whole network is EM simulated.

Intrinsic Voltage and Current Waveforms
The intrinsic collector current and voltage waveforms in the time domain, after the compensation of parasitic capacitance , provide valuable insights into the performance of the active device when it is connected to a harmonically tuned load. The schematic model utilized to obtain the voltage and current waveforms at the output of the

Intrinsic Voltage and Current Waveforms
The intrinsic collector current and voltage waveforms in the time domain, after the compensation of parasitic capacitance C out , provide valuable insights into the performance of the active device when it is connected to a harmonically tuned load. The schematic model utilized to obtain the voltage and current waveforms at the output of the cascode topology is presented in Figure 8, as a direct access to the intrinsic current source node of the provided HBT model was not available. Our model consists of a multitone voltage source, which models the magnitude and phase components of the voltage (extracted from a harmonic balance analysis) at the collector node of the common base HBT Q 2 and an ideal capacitor, C out , that represents the behavior of the AD's output parasitic capacitance over frequency. As C out changes by less than 4% at higher harmonics, a constant capacitance of C out = 120 fF was selected to simplify the model. cascode topology is presented in Figure 8, as a direct access to the intrinsic current source node of the provided HBT model was not available. Our model consists of a multitone voltage source, which models the magnitude and phase components of the voltage (extracted from a harmonic balance analysis) at the collector node of the common base HBT 2 and an ideal capacitor, , that represents the behavior of the AD's output parasitic capacitance over frequency. As changes by less than 4% at higher harmonics, a constant capacitance of = 120 fF was selected to simplify the model. An ammeter placed between the voltage source and the parallel combination of and OMN, measures the intrinsic current of our active topology. Moreover, in order to produce an accurate representation of the two waveforms, it is necessary to add the V--I DC components, as they have been extracted from a harmonic balance simulation of the proposed PA. It should be clarified that the active device constitutes the provided PDK transistor models along with the EM models that represent the metal interconnects for the performed harmonic balance simulation. The time-domain collector current and voltage waveforms at the 1 dB gain compression point operating at 38 GHz are displayed in Figure  9c and correspond to a PAE performance of approximately 40%. The strong presence of the second harmonic in the intrinsic collector voltage waveform (Figure 9a) results in a waveform that can be approximated as half-sinusoidal, while the weak and moderate presence of the second and third components of the current waveform results in an approximately square waveform (Figure 9b). These waveform shapes imply reduced V-I overlap and, therefore, improved efficiency. An ammeter placed between the voltage source and the parallel combination of C out and OMN, measures the intrinsic current of our active topology. Moreover, in order to produce an accurate representation of the two waveforms, it is necessary to add the V-I DC components, as they have been extracted from a harmonic balance simulation of the proposed PA. It should be clarified that the active device constitutes the provided PDK transistor models along with the EM models that represent the metal interconnects for the performed harmonic balance simulation. The time-domain collector current and voltage waveforms at the 1 dB gain compression point operating at 38 GHz are displayed in Figure 9c and correspond to a PAE performance of approximately 40%. The strong presence of the second harmonic in the intrinsic collector voltage waveform (Figure 9a) results in a waveform that can be approximated as half-sinusoidal, while the weak and moderate presence of the second and third components of the current waveform results in an approximately square waveform (Figure 9b). These waveform shapes imply reduced V-I overlap and, therefore, improved efficiency.
node of the provided HBT model was not available. Our model consists of a multitone voltage source, which models the magnitude and phase components of the voltage (extracted from a harmonic balance analysis) at the collector node of the common base HBT 2 and an ideal capacitor, , that represents the behavior of the AD's output parasitic capacitance over frequency. As changes by less than 4% at higher harmonics, a constant capacitance of = 120 fF was selected to simplify the model. An ammeter placed between the voltage source and the parallel combination of and OMN, measures the intrinsic current of our active topology. Moreover, in order to produce an accurate representation of the two waveforms, it is necessary to add the V--I DC components, as they have been extracted from a harmonic balance simulation of the proposed PA. It should be clarified that the active device constitutes the provided PDK transistor models along with the EM models that represent the metal interconnects for the performed harmonic balance simulation. The time-domain collector current and voltage waveforms at the 1 dB gain compression point operating at 38 GHz are displayed in Figure  9c and correspond to a PAE performance of approximately 40%. The strong presence of the second harmonic in the intrinsic collector voltage waveform (Figure 9a) results in a waveform that can be approximated as half-sinusoidal, while the weak and moderate presence of the second and third components of the current waveform results in an approximately square waveform (Figure 9b). These waveform shapes imply reduced V-I overlap and, therefore, improved efficiency.  Figure 10 depicts a photograph of the bare die chip. The total area of the fabricated chip is 0.605 × 0.712 mm 2 , including all pads. In order to assess the performance of the designed quasi-inverse class F power amplifier, probe station measurements were conducted. A VNA analyzer was used for measuring PA's response during small-signal exci-  Figure 10 depicts a photograph of the bare die chip. The total area of the fabricated chip is 0.605 × 0.712 mm 2 , including all pads. In order to assess the performance of the designed quasi-inverse class F power amplifier, probe station measurements were conducted. A VNA analyzer was used for measuring PA's response during small-signal excitation, while the large-signal measurements were carried out using an rf signal generator and a power meter. It should be mentioned that the rf cable loss was thoroughly characterized over the frequency range of interest and any necessary adjustments were made to account for this loss through de-embedding.  Figure 10 depicts a photograph of the bare die chip. The total area of the fabricated chip is 0.605 × 0.712 mm 2 , including all pads. In order to assess the performance of th designed quasi-inverse class F power amplifier, probe station measurements were con ducted. A VNA analyzer was used for measuring PA's response during small-signal exci tation, while the large-signal measurements were carried out using an rf signal generato and a power meter. It should be mentioned that the rf cable loss was thoroughly charac terized over the frequency range of interest and any necessary adjustments were made to account for this loss through de-embedding.  ). The above dc conditions result in almost 35 mW power consumption under dc operation. Furthermore, the s-parameter results indicated that the measured 21 parameter exceeded 13 dB over the frequency range of 37-4 GHz, reaching a peak value of 15.6 dB at 37 GHz, while the 11 parameter remained les than −10 dB over the frequency range of 38-40 GHz. Further broadening of input reflec tion coefficient is possible using more complex matching networks at the expense of are consumption. Moreover, Figure 11 depicts a moderate discrepancy between the 2 measurement and simulation results over the frequency range 30-37 GHz. That inaccu racy is caused by calibration error due to the defective calibration substrate used in the s parameter measurement. However, the aforementioned difference between the 22 meas urement and simulation results becomes negligible over the frequency range of ou  Figure 11 displays the small-signal s-parameter measurement and simulation results of the proposed power amplifier. It should be noted that PA's dc operating conditions during small-signal measurement and simulations were a 3.3 V supply voltage (V cc ) as well as a 2.1 V bias voltage (V bias ). The above dc conditions result in almost 35 mW power consumption under dc operation. Furthermore, the s-parameter results indicated that the measured S 21 parameter exceeded 13 dB over the frequency range of 37-40 GHz, reaching a peak value of 15.6 dB at 37 GHz, while the S 11 parameter remained less than −10 dB over the frequency range of 38-40 GHz. Further broadening of input reflection coefficient is possible using more complex matching networks at the expense of area consumption. Moreover, Figure 11 depicts a moderate discrepancy between the S 22 measurement and simulation results over the frequency range 30-37 GHz. That inaccuracy is caused by calibration error due to the defective calibration substrate used in the s-parameter measurement. However, the aforementioned difference between the S 22 measurement and simulation results becomes negligible over the frequency range of our interest (37-40 GHz). Additionally, the PA demonstrates stability throughout the entire frequency range, as depicted in Figure 12 through the k-factor measurement.

Simulation and Measurement Results
Regarding the large-signal measurement, as depicted in Figure 13, the proposed quasiinverse class F power amplifier demonstrates remarkable performance, with a large-signal power gain of more than 14 dB at its operating frequency of 38 GHz. Additionally, the output 1 dB compression point, represented by OP 1dB , is approximately 17.6 dBm, while the saturated output power P sat is around 19 dBm and the maximum PAE reaches 33%. It should be noted that the linear response of the proposed Ka-band PA is essential for maintaining high signal fidelity and minimizing interference, distortion, or nonlinear effects in wireless communication systems. Further improvement of the linearity of the presented PA is possible if a linearization technique is applied. Some of the commonly used linearization techniques in mm-wave PAs include predistortion, feedback, feedforward, digital predistortion, and envelope tracking [18].
33%. It should be noted that the linear response of the proposed Ka-band PA is essential for maintaining high signal fidelity and minimizing interference, distortion, or nonlinear effects in wireless communication systems. Further improvement of the linearity of the presented PA is possible if a linearization technique is applied. Some of the commonly used linearization techniques in mm-wave PAs include predistortion, feedback, feedforward, digital predistortion, and envelope tracking [18].   while the saturated output power is around 19 dBm and the maximum reaches 33%. It should be noted that the linear response of the proposed Ka-band PA is essential for maintaining high signal fidelity and minimizing interference, distortion, or nonlinear effects in wireless communication systems. Further improvement of the linearity of the presented PA is possible if a linearization technique is applied. Some of the commonly used linearization techniques in mm-wave PAs include predistortion, feedback, feedforward, digital predistortion, and envelope tracking [18].   Examining Figure 14, which plots the 1 and over the frequency range of 37-40 GHz, it becomes evident that the PA maintains high performance, with 1 greater than 16 dBm and higher than 30% throughout the entire band of interest. Other crucial specifications determined through our measurements include the 1 , which is approximately 9 dBm, and the AM-to-PM conversion, which is less than 13° for all the swept input powers (−20~8 dBm). The AM-to-PM conversion holds its maximum of 13° when the proposed PA operates in saturation. Efficiency (%) at 3 dB and 6 dB power Examining Figure 14, which plots the OP 1dB and PAE over the frequency range of 37-40 GHz, it becomes evident that the PA maintains high performance, with OP 1dB greater than 16 dBm and PAE higher than 30% throughout the entire band of interest. Other crucial specifications determined through our measurements include the IP 1dB , which is approximately 9 dBm, and the AM-to-PM conversion, which is less than 13 • for all the swept input powers (−20~8 dBm). The AM-to-PM conversion holds its maximum of 13 • when the proposed PA operates in saturation. Efficiency (%) at 3 dB and 6 dB power back-off have been extracted from the results of the performed large-signal measurements at 38 GHz and they are highlighted in Figure 15. In particular, the designed quasi-inverse class F power amplifier achieves a 3 dB back-off collector's efficiency of around 27.8% and a 6 dB back-off efficiency of 19.3%. Finally, the dc current drawn by our active device versus the output power deliver to the load is plotted in Figure 16. It should be mentioned that the dc current consumption under no input excitation is around 10 mA (P dc = 33 mW), while the designed PA draws 52 mA dc current when the output power reaches 1 dB compression point. Further improvement of the quiescent power consumption P dc is possible by reducing the bias voltage V bias of the common-emitter HBT driving our active module close to a class B operating point. However, such a modification leads to a reduction in the achievable power gain. Examining Figure 14, which plots the 1 and over the frequency range of 37-40 GHz, it becomes evident that the PA maintains high performance, with 1 greater than 16 dBm and higher than 30% throughout the entire band of interest. Other crucial specifications determined through our measurements include the 1 , which is approximately 9 dBm, and the AM-to-PM conversion, which is less than 13° for all the swept input powers (−20~8 dBm). The AM-to-PM conversion holds its maximum of 13° when the proposed PA operates in saturation. Efficiency (%) at 3 dB and 6 dB power back-off have been extracted from the results of the performed large-signal measurements at 38 GHz and they are highlighted in Figure 15. In particular, the designed quasi-inverse class F power amplifier achieves a 3 dB back-off collector's efficiency of around 27.8% and a 6 dB back-off efficiency of 19.3%. Finally, the dc current drawn by our active device versus the output power deliver to the load is plotted in Figure 16. It should be mentioned that the dc current consumption under no input excitation is around 10 mA ( = 33 mW), while the designed PA draws 52 mA dc current when the output power reaches 1 dB compression point. Further improvement of the quiescent power consumption is possible by reducing the bias voltage of the common-emitter HBT driving our active module close to a class B operating point. However, such a modification leads to a reduction in the achievable power gain.

Complex Waveform Simulations
Key top-level specifications that arise from the large-signal measurement results of the fabricated quasi-inverse class F power amplifier and have been presented above are incorporated in a simulation model in order to examine PA's response to modulated-signal excitation. The amplifier's model is created through Keysight's Pathwave System Design tool "SystemVue" that offers an advanced prototyping and design platform for complex RF systems. It is noteworthy to highlight that the following simulations and modeling require no extra RF instrumentation, forming an approximation based on the singletone large-signal measurement results that have been already performed.
Keeping as reference the large-signal measurement at 38 GHz, the following entries have synthesized the amplifier's model: Concerning PA's excitation, a pseudo random binary sequence generator along with an arbitrary digital modulation source generate the modulated signals at a carrier frequency of 38 GHz. Keeping the input signal's bandwidth constant at 25 MHz in each test, Figure 16. Measurement of the DC current (%) vs. output power.

Complex Waveform Simulations
Key top-level specifications that arise from the large-signal measurement results of the fabricated quasi-inverse class F power amplifier and have been presented above are incorporated in a simulation model in order to examine PA's response to modulated-signal excitation. The amplifier's model is created through Keysight's Pathwave System Design tool "SystemVue" that offers an advanced prototyping and design platform for complex RF systems. It is noteworthy to highlight that the following simulations and modeling require no extra RF instrumentation, forming an approximation based on the single-tone large-signal measurement results that have been already performed.
Keeping as reference the large-signal measurement at 38 GHz, the following entries have synthesized the amplifier's model: Concerning PA's excitation, a pseudo random binary sequence generator along with an arbitrary digital modulation source generate the modulated signals at a carrier frequency of 38 GHz. Keeping the input signal's bandwidth constant at 25 MHz in each test, an attempt is made to examine PA's response to QPSK and 16 QAM signals having different peak-to-average power ratios. It should be noted that, after a raised cosine filtering with 0.2 roll-off factor, the maximum available bandwidth is 30 MHz, while adjacent channel power ratio (ACPR) is measured at 27 MHz offset from the 38 GHz carrier frequency, as is depicted in Figure 17. The aforementioned simulation scenarios result in the bit rates of 50 Mbps and 200 Mbps for the QPSK and 16 QAM signals, respectively.
As is highlighted in Figure 18, the increase in average power efficiency entails increase in the error vector magnitude metric. Moreover, due to the fact that QPSK is the least PAPR modulation format, the PA's average power efficiency is slightly higher for a given EVM. Referring to Figure 19, the resulting EVM at PA's 1 dB compression point (OP 1dB = 17.6 dBm) is around 6% for the QPSK signal and 8% for the 16 QAM signal, while, for output powers that correspond to the linear region of the designed PA, the EVM is lower than 4% for both modulation schemes. an attempt is made to examine PA's response to QPSK and 16 QAM signals having different peak-to-average power ratios. It should be noted that, after a raised cosine filtering with 0.2 roll-off factor, the maximum available bandwidth is 30 MHz, while adjacent channel power ratio (ACPR) is measured at 27 MHz offset from the 38 GHz carrier frequency, as is depicted in Figure 17. The aforementioned simulation scenarios result in the bit rates of 50 Mbps and 200 Mbps for the QPSK and 16 QAM signals, respectively. As is highlighted in Figure 18, the increase in average power efficiency entails increase in the error vector magnitude metric. Moreover, due to the fact that QPSK is the least PAPR modulation format, the PA's average power efficiency is slightly higher for a given EVM. Referring to Figure 19, the resulting EVM at PA's 1 dB compression point ( 1 = 17.6 dBm ) is around 6% for the QPSK signal and 8% for the 16 QAM signal, while, for output powers that correspond to the linear region of the designed PA, the EVM is lower than 4% for both modulation schemes.   As is highlighted in Figure 18, the increase in average power efficiency entails increase in the error vector magnitude metric. Moreover, due to the fact that QPSK is the least PAPR modulation format, the PA's average power efficiency is slightly higher for a given EVM. Referring to Figure 19, the resulting EVM at PA's 1 dB compression point ( 1 = 17.6 dBm ) is around 6% for the QPSK signal and 8% for the 16 QAM signal, while, for output powers that correspond to the linear region of the designed PA, the EVM is lower than 4% for both modulation schemes.  Based on the information provided in Figure 20, it can be observed that the adjacent channel power ratio (ACPR) exhibits a value of −40 dBc when the power amplifier (PA) model is stimulated with QPSK or 16 QAM signals, which have weak peak-to-average power ratios. It is important to note that, as the average output power of the PA increases, the ACPR also experiences an increase, which is a commonly expected phenomenon. Based on the information provided in Figure 20, it can be observed that the adjacent channel power ratio (ACPR) exhibits a value of −40 dBc when the power amplifier (PA) model is stimulated with QPSK or 16 QAM signals, which have weak peak-to-average power ratios. It is important to note that, as the average output power of the PA increases, the ACPR also experiences an increase, which is a commonly expected phenomenon. When our PA reaches its 1 dB compression point, the ACPR is approximately −25 dBc for both input excitations. Finally, the ACPR requirement for 3GPP NR carrier [22] is depicted in Figure 20. The ACPR limit has been set at −26 dBc for the FR2 frequency range 37-52.6 GHz. As follows, the proposed PA model complies with the ACPR requirements of the 3GPP NR standards until its output almost reaches the OP 1dB . Based on the information provided in Figure 20, it can be observed that the adja channel power ratio (ACPR) exhibits a value of −40 dBc when the power amplifier model is stimulated with QPSK or 16 QAM signals, which have weak peak-to-ave power ratios. It is important to note that, as the average output power of the PA incre the ACPR also experiences an increase, which is a commonly expected phenome When our PA reaches its 1 dB compression point, the ACPR is approximately −25 for both input excitations. Finally, the ACPR requirement for 3GPP NR carrier [22] i picted in Figure 20. The ACPR limit has been set at −26 dBc for the FR2 frequency r 37-52.6 GHz. As follows, the proposed PA model complies with the ACPR requirem of the 3GPP NR standards until its output almost reaches the 1 . Figure 20. Adjacent channel power ratio vs. average output power for QPSK and 16 QAM si with different peak-to-average power ratios. Table   Table 3 includes a summary of the various parameters of the designed Ka-band q inverse class F power amplifier, as they have been extracted from the performed mea ments. Moreover, it provides the specifications of other state-of-the-art Ka-band p amplifiers integrated in SiGe BiCMOS technologies, making the comparison with  Table   Table 3 includes a summary of the various parameters of the designed Ka-band quasi-inverse class F power amplifier, as they have been extracted from the performed measurements. Moreover, it provides the specifications of other state-of-the-art Ka-band power amplifiers integrated in SiGe BiCMOS technologies, making the comparison with the proposed one feasible. It is noteworthy to highlight that the fabricated PA presented in this paper exhibits a very good compromise between the maximum output power it can deliver to the load, the achievable power gain, as well as the maximum PAE. Further improvement of the PAE and the corresponding power consumption is possible if additional harmonic tanks are incorporated in the designed output-matching network for a higher order harmonic component control. The performance metrics of Table 3 demonstrate that the proposed PA based on the quasi-inverse class F technique is competitive to other high-efficiency techniques that adopt high-order multi-resonance harmonic filter loads. A Figure of Merit (FoM) has been introduced by the authors of this article for performance comparison of the various Ka-band SiGe PAs. The FoM is calculated using the following formula: FoM = P sat (dBm) + OP 1dB (dBm) + 10 log(PAE(%)) + 20 log(Frequency(GHz)) − 10 log(P dc (mW)) (9) As is clearly depicted in Table 3, the present work achieves the highest FoM (68) among state-of-the-art integrated Ka-band SiGe PAs, verifying the effectiveness of the proposed design and highlighting its potential for future applications in high-frequency communication systems.

Conclusions
In this paper, a SiGe BiCMOS power amplifier is successfully implemented and demonstrated at the Ka-band. The designed PA is based on a quasi-inverse class F technique that adopts a second-harmonically tuned load providing the required impedances to the cascode amplifying core. This paper fully discusses the potential and limitations of the proposed quasi-inverse class F technique, as well as its distinctive feature from the conventional inverse class F technique. In order for the quasi-inverse class F approach to be implemented, it is crucial to thoroughly examine and calculate the parasitic components of the PA's main active device. In this work, the cascode configuration is treated as a single active device, with its output capacitance being identified as a critical parasitic component. A detailed methodology is described for the discovery of the active device's output parasitic capacitance enforcing the accuracy of the main core modeling and enabling the designing of the harmonically tuned load. Furthermore, a comprehensive description of the design steps that were followed for the schematic and physical design of each part that constitute the proposed PA is presented. Afterwards, a simplified model for the extraction of time-domain intrinsic voltage and current waveforms is introduced, enforcing the process for the implementation of the proposed quasi-inverse class F technique. The major top-level specifications that have been identified based on the large-signal measurement outcomes of the quasi-inverse class F PA are included in a simulation model. This model is utilized to analyze the performance of PA when it is subjected to modulated-signal excitation. According to small-and large-signal measurements and the comparison table that includes other state-of-the-art Ka-band PAs, the designed single-stage amplifier achieves one of the highest output powers while maintaining a high level of efficiency.