Special Issue "Low Power Wireless Sensing and Internet of Things"

A special issue of Journal of Low Power Electronics and Applications (ISSN 2079-9268).

Deadline for manuscript submissions: closed (30 September 2014)

Special Issue Editor

Guest Editor
Prof. Robert E. Kinicki

Computer Science Department; Worcester Polytechnic Institute, Worcester, MA 01609-2280, USA
Website | E-Mail
Interests: power-aware wireless protocols; rate adaptation algorithms for wireless networks; infrastructure wireless LAN performance; home wireless networks; performance of multimedia applications over networks

Special Issue Information

Dear Colleagues,

Low-power, economical wireless sensor networks (WSNs) is the technology that will bring shared intelligence to objects in the Internet of Things (IoT). To meet the scalability requirements for ubiquitous IoT connectivity, ultra-low-power radios are needed and suitable interoperable protocols must be standardized to assure safe, secure and efficient machine-to-machine coordination. Additionally these low-layer radio and MAC layer protocols must be integrated into lightweight operating systems and serve as the foundation for Web-based applications that utilize IPv6 over the Internet. This special issue focuses on concepts that connect and enhance low-power wireless sensing with the Internet of Things.

Circuit technology that support the timing mechanisms for sensor platform operations and efficient, secure radio communication among smart objects are the subject of this issue. Papers that consider standardized protocol developments that work with sensor platforms are encouraged. Also, concepts at the interface between MAC layer protocols that support IoT applications and the underlying low-power circuitry are highly encouraged.

Professor Robert E. Kinicki
Guest Editor

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All papers will be peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Journal of Low Power Electronics and Applications is an international peer-reviewed open access quarterly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 350 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.


  • controlled machine-to-machine communication
  • low-power sensor platforms and operating systems
  • IPv6 protocol stacks
  • smart devices and the smart grid
  • internet of things applications
  • circuit and system level design for sensor network applications
  • security issues in sensor communications

Published Papers (1 paper)

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Open AccessArticle 39 fJ/bit On-Chip Identification ofWireless Sensors Based on Manufacturing Variation
J. Low Power Electron. Appl. 2014, 4(3), 252-267; https://doi.org/10.3390/jlpea4030252
Received: 8 July 2014 / Revised: 18 August 2014 / Accepted: 4 September 2014 / Published: 12 September 2014
Cited by 1 | PDF Full-text (425 KB) | HTML Full-text | XML Full-text
A 39 fJ/bit IC identification system based on FET mismatch is presented and implemented in a 130 nm CMOS process. ID bits are generated based on the ΔVT between identically drawn NMOS devices due to manufacturing variation, and the ID cell structure allows [...] Read more.
A 39 fJ/bit IC identification system based on FET mismatch is presented and implemented in a 130 nm CMOS process. ID bits are generated based on the ΔVT between identically drawn NMOS devices due to manufacturing variation, and the ID cell structure allows for the characterization of ID bit reliability by characterizing ΔVT . An addressing scheme is also presented that allows for reliable on-chip identification of ICs in the presence of unreliable ID bits. An example implementation is presented that can address 1000 unique ICs, composed of 31 ID bits and having an error rate less than 10-6, with up to 21 unreliable bits. Full article
(This article belongs to the Special Issue Low Power Wireless Sensing and Internet of Things)

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J. Low Power Electron. Appl. EISSN 2079-9268 Published by MDPI AG, Basel, Switzerland RSS E-Mail Table of Contents Alert
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