Low Power Analog to Digital Converter
A special issue of Journal of Low Power Electronics and Applications (ISSN 2079-9268).
Deadline for manuscript submissions: closed (31 December 2018) | Viewed by 360
Special Issue Editor
Interests: power semiconductor devices; low power IoT devices, RF circuit reliability; deep learning and neuromorphic computing; hardware security
Special Issue Information
Dear Colleagues,
Low power devices are crucial to the Internet of Things (IoT), with more than 9 billion connected IoT devices in use at the end of 2017. In wearable devices and other IoT applications, integrated sensor interface circuits are required to prepare the analog sensor output for digital signal processing. Often the sensor nodes are powered by batteries, and hence power dissipation in the interface circuitry is of great concern. The interfaces usually require high-accuracy ultra-low-power analog-to-digital converters (ADCs). While many design techniques use energy efficient SAR architectures, where possible for moderate resolution and speed, higher resolution is consistently enabled by delta-sigma architecture and faster operation is realized by pipeline architecture. Precision is further enabled by techniques, such as hardware re-use, calibration, dynamic element matching, chopping, and correlated double-sampling.
Now, the focus of research on low-power ADC design itself, however, has shifted to the hybrid of architectures and sophisticated calibration methods. The main reason for this shift is further reduction of power consumption as well as high speed. Power, linearity, bandwidth, area, and process form complex trade-offs in ADC design. Circuit nonlinearity, process variation and mismatch between activate and passive devices are a few examples of challenges in today’s ADCs, which, if not carefully accounted for, could lead to gain error and/or nonlinearity in the ADC system. These issues can be resolved in the analog or digital domain. Analog-domain solutions for the above issues include using larger capacitors for better matching or using high loop gain, wide bandwidth, and low-distortion amplifiers or using feedback loops. Unfortunately, all the above techniques are power-hungry and becoming increasingly difficult to design with deep submicron or nano-micrometer CMOS processes. On the other hand, reduced gate delays and ease of portability across processes make digital calibration for analog imperfections very attractive in modern CMOS processes. Most of the existing calibration techniques try to account for linear gain errors. However, there are only a handful of digital calibration techniques which can help reduce nonlinearity in ADCs.
In this special issue, we focus on the latest development in low power ADCs. It will reflect a wide spectrum of research topics from architecture design, analog/digital module design and calibration algorithm design. Authors are invited to submit regular papers following the Journal of Low Power Electronics and Applications submission guidelines. Suggested topics include but are not limited to:
- Nyquist rate ADCs
- Oversampling ADCs
- Hybrid architecture for ADCs
- Power efficient linearity and SNR enhancement techniques
- Foreground/background calibration algorithm
- Low power key modules for ADCs
- Emerging technology ADCs
Prof. Jiann-Shiun Yuan
Guest Editor
Manuscript Submission Information
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