Energy Aware Scientific Computing in Distributed Architectures, Low Power Processors and HPC Hybrid Systems

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Electrical and Computer Engineering, Utah State University, Logan, UT 84322-4120, USA
Interests: AI hardware design; low power computing; computer systems
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Special Issue Information

Dear Colleagues,

Modern society is witnessing a sea change in ubiquitous computing, whereby people have embraced a slew of computing systems as indispensable parts of day-to-day existence. The computational, storage, and communication abilities of smartphones, for example, have undergone monumental changes in the past decade itself. With these changes, came a rapid and ongoing proliferation of edge computing systems and applications. Energy consumption is a growing problem of these computing platforms. There is a critical need for energy-aware architectures in many core systems, GPUs, hardware accelerators, and edge computing devices. This Special Issue will provide a selection of papers on energy-aware and low-power computing in system-on-chips, hardware accelerators, GPUs, embedded systems, or edge computing systems. Advances in algorithms for hardware systems design and novel architectures for low power are encouraged.

Prof. Dr. Sanghamitra Roy
Guest Editor

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Journal of Low Power Electronics and Applications is an international peer-reviewed open access quarterly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 1800 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • low power processors
  • distributed architectures
  • hardware accelerators
  • AI hardware

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Published Papers (1 paper)

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Research

16 pages, 667 KiB  
Article
Voltage Stacking: A First-Order Modelization of an m × n Asynchronous Array for Chip and Architectural Design Exploration
by Baudouin Chauviere and Kenneth S. Stevens
J. Low Power Electron. Appl. 2024, 14(3), 44; https://doi.org/10.3390/jlpea14030044 - 27 Aug 2024
Viewed by 883
Abstract
Voltage stacking is a technique in which multiple integrated circuits are stacked in series between the supply voltage instead of in parallel, thus improving the energy efficiency of the power distribution network. Unfortunately, voltage stacking presents stability challenges for integrated circuits within the [...] Read more.
Voltage stacking is a technique in which multiple integrated circuits are stacked in series between the supply voltage instead of in parallel, thus improving the energy efficiency of the power distribution network. Unfortunately, voltage stacking presents stability challenges for integrated circuits within the stack. A first-order model to quantify variability, stability, and power metrics for an array of voltage-stacked asynchronous integrated circuits is presented. Voltage variability and power consumption are accounted for and discussed. Limitations of the model are identified outside of the nominal behavior. The number of columns in the architecture, chip leakage, and supply voltage are shown to be the key contributors to the stability, performance, and energy efficiency of a system of voltage-stacked asynchronous processors. A higher leakage to active power ratio, though usually avoided by chip designers, is shown to improve stability and be key in designing stacks without external balancing. Outputs of the model enable system and chip designers to evaluate first-order trade-offs in energy efficiency, performance, and system cost. These fundamental data allow designers to make informed design and optimization trade-offs between asynchronous voltage-stacked architectures and the integrated circuits used therein. Analysis of this model shows that various voltage-stacked configurations, such as one with a 48 V supply using 100 rows and 11 columns, can be designed with less than 10% voltage variation per chip, mitigating the need for external voltage balancing. Full article
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