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Electronics
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VLSI Design, Testing, and Applications
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VLSI Design, Testing, and Applications

A special issue of Electronics (ISSN 2079-9292). This special issue belongs to the section "Circuit and Signal Processing".

Deadline for manuscript submissions: closed (15 November 2022) | Viewed by 12290

Special Issue Editor

Dr. Xiang Chen

E-Mail Website
Guest Editor
School of Engineering, George Mason University, Fairfax, VA 22030, USA
Interests: mobile embedded system; mobile computing; deep learning; VLSI

Special Issue Information

Dear Colleagues,

The focus of this Special Issue is on the research challenges related to the design of emerging microelectronics and VLSI circuits and related systems that meet the demanding specifications of innovative applications. This Special Issue considers challenges in the fields of low power consumption, small integration areas, testing and security, without, however, being limited to them. Authors are encouraged to submit works related to emerging research topics and applications, such as hardware security, low-power IoT devices, high-performance processing cores, etc.

Dr. Xiang Chen
Guest Editor

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Electronics is an international peer-reviewed open access semimonthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 2400 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • device modeling
  • emerging technologies
  • CAD for VLSI design
  • hardware/software co-design
  • testing and verification
  • FPGA-based design
  • embedded systems
  • IP cores
  • low-power circuits and systems
  • hardware security
  • emerging applications
  • VLSI for AI and ML algorithms

Published Papers (6 papers)

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Research

15 pages, 7189 KiB  
Article
High-Speed Grouping and Decomposition Multiplier for Binary Multiplication
by Khamalesh Kumar Padmanabhan, Umadevi Seerengasamy and Abraham Sudharson Ponraj
Electronics 2022, 11(24), 4202; https://doi.org/10.3390/electronics11244202 - 16 Dec 2022
Cited by 1 | Viewed by 1920
Abstract
In the computation systems that are frequently utilized in Digital Signal Processing (DSP)- and Fast Fourier transform (FFT)-based applications, binary multipliers play a crucial role. Multipliers are one of the basic arithmetic components used, and they require more hardware resources and computational time. [...] Read more.
In the computation systems that are frequently utilized in Digital Signal Processing (DSP)- and Fast Fourier transform (FFT)-based applications, binary multipliers play a crucial role. Multipliers are one of the basic arithmetic components used, and they require more hardware resources and computational time. Due to this, numerous studies have been performed so as to decrease the computational time and hardware requirements. In this research study on reducing the necessary computational time, a high-speed binary multiplier known as the Grouping and Decomposition (GD) multiplieris proposed. The proposed multiplier aims to achieve competency in processing algorithms over existing multiplier architectures through a combination of the parallel grouping of partial products of the same size and the decomposition of each grouped partial-product bit, with the final summation performed using a 5:2 logic adder (5LA). The usage of parallel processing and decomposition logic reduces the number of computation steps and hence achieves a higher speed in multiplication. The front-end and physical design implementation of the proposed GD multiplier have been executed in the 180 nm technology library using the Cadence® Virtuoso and Cadence® Virtuoso Assura tools. From the front-end design of the 8 × 8 proposed GD multiplier, it was observed that the GD multiplier achieves a reduction of approximately 56% in computation time and a reduction of 53% in power–delay product when compared to existing multiplier architectures. A further reduction in the power–delay product is achieved by the physical design implementation of the proposed multiplier due to the internal routing of subsystems with the shortest-path algorithm. The proposed multiplier works better with higher-order multiplication and is suitable for high-end applications. Full article
(This article belongs to the Special Issue VLSI Design, Testing, and Applications)
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23 pages, 2985 KiB  
Article
A Script-Based Cycle-True Verification Framework to Speed-Up Hardware and Software Co-Design: Performance Evaluation on ECC Accelerator Use-Case
by Luca Zulberti, Stefano Di Matteo, Pietro Nannipieri, Sergio Saponara and Luca Fanucci
Electronics 2022, 11(22), 3704; https://doi.org/10.3390/electronics11223704 - 12 Nov 2022
Cited by 9 | Viewed by 1528
Abstract
Digital designs complexity has exponentially increased in the last decades. Heterogeneous Systems-on-Chip integrate many different hardware components which require a reliable and scalable verification environment. The effort to set up such environments has increased as well and plays a significant role in digital [...] Read more.
Digital designs complexity has exponentially increased in the last decades. Heterogeneous Systems-on-Chip integrate many different hardware components which require a reliable and scalable verification environment. The effort to set up such environments has increased as well and plays a significant role in digital design projects, taking more than 50% of the total project time. Several solutions have been developed with the goal of automating this task, integrating various steps of the Very Large Scale Integration design flow, but without addressing the exploration of the design space on both the software and hardware sides. Early in the co-design phase, designers break down the system into hardware and software parts taking into account different choices to explore the design space. This work describes the use of a framework for automating the verification of such choices, considering both hardware and software development flows. The framework automates compilation of software, cycle-true simulations and analyses on synthesised netlists. It accelerates the design space exploration exploiting the GNU Make tool, and we focus on ensuring consistency of results and providing a mechanism to obtain reproducibility of the design flow. In design teams, the last feature increases cooperation and knowledge sharing from single expert to the whole team. Using flow recipes, designers can configure various third-party tools integrated into the modular structure of the framework, and make workflow execution customisable. We demonstrate how the developed framework can be used to speed up the setup of the evaluation flow of an Elliptic-Curve-Cryptography accelerator, performing post-synthesis analyses. The framework can be easily configured taking approximately 30 min, instead of few days, to build up an environment to assess the accelerator performance and its resistance to simple power analysis side-channel attacks. Full article
(This article belongs to the Special Issue VLSI Design, Testing, and Applications)
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16 pages, 1309 KiB  
Article
TORRES: A Resource-Efficient Inference Processor for Binary Convolutional Neural Networks Based on Locality-Aware Operation Skipping
by Su-Jung Lee, Gil-Ho Kwak and Tae-Hwan Kim
Electronics 2022, 11(21), 3534; https://doi.org/10.3390/electronics11213534 - 29 Oct 2022
Cited by 4 | Viewed by 1468
Abstract
A binary convolutional neural network (BCNN) is a neural network promising to realize analysis of visual imagery in low-cost resource-limited devices. This study presents an efficient inference processor for BCNNs, named TORRES. TORRES performs inference efficiently, skipping operations based on the spatial locality [...] Read more.
A binary convolutional neural network (BCNN) is a neural network promising to realize analysis of visual imagery in low-cost resource-limited devices. This study presents an efficient inference processor for BCNNs, named TORRES. TORRES performs inference efficiently, skipping operations based on the spatial locality inherent in feature maps. The training process is regularized with the objective of skipping more operations. The microarchitecture is designed to skip operations and generate addresses efficiently with low resource usage. A prototype inference system based on TORRES has been implemented in a 28 nm field-programmable gate array, and its functionality has been verified for practical inference tasks. Implemented with 2.31 K LUTs, TORRES achieves the inference speed of 291.2 GOP/s, exhibiting the resource efficiency of 126.06 MOP/s/LUT. The resource efficiency of TORRES is 1.45 times higher than that of the state-of-the-art work. Full article
(This article belongs to the Special Issue VLSI Design, Testing, and Applications)
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24 pages, 7795 KiB  
Article
HW-Flow-Fusion: Inter-Layer Scheduling for Convolutional Neural Network Accelerators with Dataflow Architectures
by Emanuele Valpreda, Pierpaolo Morì, Nael Fasfous, Manoj Rohit Vemparala, Alexander Frickenstein, Lukas Frickenstein, Walter Stechele, Claudio Passerone, Guido Masera and Maurizio Martina
Electronics 2022, 11(18), 2933; https://doi.org/10.3390/electronics11182933 - 16 Sep 2022
Cited by 2 | Viewed by 2418
Abstract
Energy and throughput efficient acceleration of convolutional neural networks (CNN) on devices with a strict power budget is achieved by leveraging different scheduling techniques to minimize data movement and maximize data reuse. Several dataflow mapping frameworks have been developed to explore the optimal [...] Read more.
Energy and throughput efficient acceleration of convolutional neural networks (CNN) on devices with a strict power budget is achieved by leveraging different scheduling techniques to minimize data movement and maximize data reuse. Several dataflow mapping frameworks have been developed to explore the optimal scheduling of CNN layers on reconfigurable accelerators. However, previous works usually optimize each layer singularly, without leveraging the data reuse between the layers of CNNs. In this work, we present an analytical model to achieve efficient data reuse by searching for efficient scheduling of communication and computation across layers. We call this inter-layer scheduling framework HW-Flow-Fusion, as we explore the fused map-space of multiple layers sharing the available resources of the same accelerator, investigating the constraints and trade-offs of mapping the execution of multiple workloads with data dependencies. We propose a memory-efficient data reuse model, tiling, and resource partitioning strategies to fuse multiple layers without recomputation. Compared to standard single-layer scheduling, inter-layer scheduling can reduce the communication volume by 51% and 53% for selected VGG16-E and ResNet18 layers on a spatial array accelerator, and reduce the latency by 39% and 34% respectively, while also increasing the computation to communication ratio which improves the memory bandwidth efficiency. Full article
(This article belongs to the Special Issue VLSI Design, Testing, and Applications)
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19 pages, 415 KiB  
Article
A Systematic Method to Generate Effective STLs for the In-Field Test of CAN Bus Controllers
by Felipe Augusto da Silva, Riccardo Cantoro, Said Hamdioui, Sandro Sartoni, Christian Sauer and Matteo Sonza Reorda
Electronics 2022, 11(16), 2481; https://doi.org/10.3390/electronics11162481 - 09 Aug 2022
Cited by 1 | Viewed by 1635
Abstract
In order to match the strict reliability requirements mandated by regulations and standards adopted in the automotive sector, as well as other domains where safety is a major concern, the in-field testing of the most critical devices, including microcontrollers and systems on chip, [...] Read more.
In order to match the strict reliability requirements mandated by regulations and standards adopted in the automotive sector, as well as other domains where safety is a major concern, the in-field testing of the most critical devices, including microcontrollers and systems on chip, is a crucial task. Since the controller area network (CAN) bus is widely used in the automotive domain, the corresponding controller ubiquitously appears in all these devices. This paper presents a generic and systematic methodology to develop an effective in-field test procedure for CAN controllers based on a functional approach (i.e., on the adoption of self-test libraries). The method can be customized to match the requirements coming from different scenarios, and allows the test engineer to maximize the achieved fault coverage in terms of structural faults in the different cases. The experimental results we gathered on a representative CAN controller model show that, given two typical testing scenarios, we are able to detect 84.28% and 87.62% of stuck-at faults, respectively, hence demonstrating the effectiveness of the proposed approach. Full article
(This article belongs to the Special Issue VLSI Design, Testing, and Applications)
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13 pages, 5643 KiB  
Article
Leakage Current Stability Analysis for Subthreshold SRAM
by Na Bai, Zhiqiang Hu, Yi Wang and Yaohua Xu
Electronics 2022, 11(8), 1196; https://doi.org/10.3390/electronics11081196 - 09 Apr 2022
Cited by 2 | Viewed by 1923
Abstract
Low-power memories typically operate in the subthreshold region of the device; however, as the supply voltage continues to decrease, the impact of leakage current on SRAM stability becomes more significant. The traditional method of measuring static noise tolerance only considers the effect of [...] Read more.
Low-power memories typically operate in the subthreshold region of the device; however, as the supply voltage continues to decrease, the impact of leakage current on SRAM stability becomes more significant. The traditional method of measuring static noise tolerance only considers the effect of voltage, and the measurement results are not accurate enough. Therefore, this paper proposes a leakage-current-based stability analysis that provides better metrics, reads current noise tolerance (RINM) and writes current noise tolerance (WINM) to measure the stability of subthreshold SRAMs. Both currents and voltages were taken into account. The results demonstrate that the method is more accurate than the conventional method under subthreshold levels. Full article
(This article belongs to the Special Issue VLSI Design, Testing, and Applications)
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