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Electronics
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VLSI Architectures for Wireless Communications and Digital Signal Processing
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VLSI Architectures for Wireless Communications and Digital Signal Processing

A special issue of Electronics (ISSN 2079-9292). This special issue belongs to the section "Circuit and Signal Processing".

Deadline for manuscript submissions: closed (31 August 2022) | Viewed by 15618

Special Issue Editors

Prof. Dr. Byeong Yong Kong

E-Mail Website
Guest Editor
Division of Electrical, Electronic, and Control Engineering, Kongju National University, Cheonan 31080, Korea
Interests: VLSI signal processing; digital systems; system on chip (SoC); wireless communications
Prof. Dr. Hoyoung Yoo

E-Mail Website
Guest Editor
Department of Electronics Engineering, Chungnam National University, Daejeon 34134, Republic of Korea
Interests: VLSI design for error-correction codes; VLSI design for 5G communication; reverse engineering for FPGA

Special Issue Information

Dear Colleagues,

Due to the relentless growth of computational complexity, state-of-the-art technologies cannot be realized unless they are accelerated by very-large-scale-integration (VLSI) circuits. For instance, 5G telecommunications necessitate application-specific integrated circuits (ASICs) to achieve data rates over tens of gigabits per second. The Internet-of-Things (IoT) systems connecting a massive number of edge devices also demand highly efficient hardware to accommodate data transfer within a few milliseconds under a limited power budget. Computer-vision applications based on deep neural networks are so computationally intensive that they incur orders-of-magnitude more operations than ever before. To facilitate the realization of such cutting-edge technologies, considerable attention should be paid to the development of efficient VLSI architectures.

This Special Issue solicits original and unpublished papers on high-performance and low-power VLSI architectures and the relevant algorithmic optimizations in the field of wireless communications and digital signal processing.

The topics of interest include but are not limited to:

  • VLSI architectures for 5G and 6G telecommunications;
  • FPGA and ASIC implementations of signal-processing systems;
  • Baseband signal processing for communication systems;
  • Circuits and systems for the Internet-of-Things (IoT);
  • VLSI architectures for machine learning and artificial intelligence;
  • Application-specific instruction-set processors for digital signal processing;
  • Hardware-friendly algorithms and optimization techniques;
  • Embedded systems on chip (SoCs) for signal-processing applications.

Prof. Dr. Byeong Yong Kong
Prof. Dr. Hoyoung Yoo
Guest Editors

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Electronics is an international peer-reviewed open access semimonthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 2400 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Published Papers (4 papers)

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23 pages, 6559 KiB  
Article
CONNA: Configurable Matrix Multiplication Engine for Neural Network Acceleration
by Sang-Soo Park and Ki-Seok Chung
Electronics 2022, 11(15), 2373; https://doi.org/10.3390/electronics11152373 - 29 Jul 2022
Cited by 4 | Viewed by 5606
Abstract
Convolutional neural networks (CNNs) have demonstrated promising results in various applications such as computer vision, speech recognition, and natural language processing. One of the key computations in many CNN applications is matrix multiplication, which accounts for a significant portion of computation. Therefore, hardware [...] Read more.
Convolutional neural networks (CNNs) have demonstrated promising results in various applications such as computer vision, speech recognition, and natural language processing. One of the key computations in many CNN applications is matrix multiplication, which accounts for a significant portion of computation. Therefore, hardware accelerators to effectively speed up the computation of matrix multiplication have been proposed, and several studies have attempted to design hardware accelerators to perform better matrix multiplications in terms of both speed and power consumption. Typically, accelerators with either a two-dimensional (2D) systolic array structure or a single instruction multiple data (SIMD) architecture are effective only when the input matrix has shapes that are close to or similar to a square. However, several CNN applications require multiplications of non-squared matrices with various shapes and dimensions, and such irregular shapes lead to poor utilization efficiency of the processing elements (PEs). This study proposes a configurable engine for neural network acceleration, called CONNA, whose computation engine can conduct matrix multiplications with highly utilized computing units, regardless of the access patterns, shapes, and dimensions of the input matrices by changing the shape of matrix multiplication conducted in the physical array. To verify the functionality of the CONNA accelerator, we implemented CONNA as an SoC platform that integrates a RISC-V MCU with CONNA on Xilinx VC707 FPGA. SqueezeNet on CONNA achieved an inference performance of 100 frames per second (FPS) with 2.36 mm2 and 83.55 mW in a 65 nm process, improving efficiency by up to 34.1 times better than existing accelerators in terms of FPS, silicon area, and power consumption. Full article
(This article belongs to the Special Issue VLSI Architectures for Wireless Communications and Digital Signal Processing)
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22 pages, 848 KiB  
Article
Partial Order-Based Decoding of Rate-1 Nodes in Fast Simplified Successive-Cancellation List Decoders for Polar Codes
by Lucas Johannsen, Claus Kestel, Oliver Griebel, Timo Vogt and Norbert Wehn
Electronics 2022, 11(4), 560; https://doi.org/10.3390/electronics11040560 - 12 Feb 2022
Cited by 3 | Viewed by 1767
Abstract
Polar codes are the first family of error-correcting codes that can achieve channel capacity. Among the known decoding algorithms, Successive-Cancellation List (SCL) decoding supported by a Cyclic Redundancy Check (CRC) shows the best error-correction performance at the cost of a high decoding complexity. [...] Read more.
Polar codes are the first family of error-correcting codes that can achieve channel capacity. Among the known decoding algorithms, Successive-Cancellation List (SCL) decoding supported by a Cyclic Redundancy Check (CRC) shows the best error-correction performance at the cost of a high decoding complexity. The decoding of Rate-1 nodes belongs to the most complex tasks in SCL decoding. In this paper, we present a new algorithm that largely reduces the number of considered candidates in a Rate-1 node and generate all required candidates in parallel. For this purpose, we use a partial order of the candidate paths to prove that only a specified number of candidates needs to be considered. Further complexity reductions are achieved by an extended threshold-based path exclusion scheme at the cost of negligible error-correction performance loss. We present detailed Application-Specific Integrated Circuit (ASIC) implementation data on a 28 nm Fully Depleted Silicon on Insulator (FD-SOI) Complementary Metal-Oxide-Semiconductor (CMOS) technology for decoders with code length 128. We show that the new decoders outperform state-of-the-art reference decoders. For list size 8, improvements of up to 158.8% and 62.5% in area and energy efficiency are observed, respectively. Full article
(This article belongs to the Special Issue VLSI Architectures for Wireless Communications and Digital Signal Processing)
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23 pages, 630 KiB  
Article
Algorithmic Structures for Realizing Short-Length Circular Convolutions with Reduced Complexity
by Aleksandr Cariow and Janusz P. Paplinski
Electronics 2021, 10(22), 2800; https://doi.org/10.3390/electronics10222800 - 15 Nov 2021
Cited by 1 | Viewed by 1509
Abstract
A set of efficient algorithmic solutions suitable to the fully parallel hardware implementation of the short-length circular convolution cores is proposed. The advantage of the presented algorithms is that they require significantly fewer multiplications as compared to the naive method of implementing this [...] Read more.
A set of efficient algorithmic solutions suitable to the fully parallel hardware implementation of the short-length circular convolution cores is proposed. The advantage of the presented algorithms is that they require significantly fewer multiplications as compared to the naive method of implementing this operation. During the synthesis of the presented algorithms, the matrix notation of the cyclic convolution operation was used, which made it possible to represent this operation using the matrix–vector product. The fact that the matrix multiplicand is a circulant matrix allows its successful factorization, which leads to a decrease in the number of multiplications when calculating such a product. The proposed algorithms are oriented towards a completely parallel hardware implementation, but in comparison with a naive approach to a completely parallel hardware implementation, they require a significantly smaller number of hardwired multipliers. Since the wired multiplier occupies a much larger area on the VLSI and consumes more power than the wired adder, the proposed solutions are resource efficient and energy efficient in terms of their hardware implementation. We considered circular convolutions for sequences of lengths N= 2, 3, 4, 5, 6, 7, 8, and 9. Full article
(This article belongs to the Special Issue VLSI Architectures for Wireless Communications and Digital Signal Processing)
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24 pages, 3854 KiB  
Article
Flexible 5G New Radio LDPC Encoder Optimized for High Hardware Usage Efficiency
by Vladimir L. Petrović, Dragomir M. El Mezeni and Andreja Radošević
Electronics 2021, 10(9), 1106; https://doi.org/10.3390/electronics10091106 - 08 May 2021
Cited by 19 | Viewed by 4225
Abstract
Quasi-cyclic low-density parity-check (QC–LDPC) codes are introduced as a physical channel coding solution for data channels in 5G new radio (5G NR). Depending on the use case scenario, this standard proposes the usage of a wide variety of codes, which imposes the need [...] Read more.
Quasi-cyclic low-density parity-check (QC–LDPC) codes are introduced as a physical channel coding solution for data channels in 5G new radio (5G NR). Depending on the use case scenario, this standard proposes the usage of a wide variety of codes, which imposes the need for high encoder flexibility. LDPC codes from 5G NR have a convenient structure and can be efficiently encoded using forward substitution and without computationally intensive multiplications with dense matrices. However, the state-of-the-art solutions for encoder hardware implementation can be inefficient since many hardware processing units stay idle during the encoding process. This paper proposes a novel partially parallel architecture that can provide high hardware usage efficiency (HUE) while achieving encoder flexibility and support for all 5G NR codes. The proposed architecture includes a flexible circular shifting network, which is capable of shifting a single large bit vector or multiple smaller bit vectors depending on the code. The encoder architecture was built around the shifter in a way that multiple parity check matrix elements can be processed in parallel for short codes, thus providing almost the same level of parallelism as for long codes. The processing schedule was optimized for minimal encoding time using the genetic algorithm. The optimized encoder provided high throughputs, low latency, and up-to-date the best HUE. Full article
(This article belongs to the Special Issue VLSI Architectures for Wireless Communications and Digital Signal Processing)
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