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Electronics
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Recent Advances in CMOS Logic Circuits
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Recent Advances in CMOS Logic Circuits

A special issue of Electronics (ISSN 2079-9292). This special issue belongs to the section "Circuit and Signal Processing".

Deadline for manuscript submissions: closed (31 August 2022) | Viewed by 4034

Special Issue Editors

Dr. Yuan-Ho Chen

E-Mail Website
Guest Editor
Department of Electronics Engineering, Chang Gung University, Taoyuan 333, Taiwan
Interests: AI chip design; bio-signal processing chip design; arithmetic logic design; video transform for HEVC
Special Issues, Collections and Topics in MDPI journals
Dr. Shin-Chi Lai

E-Mail Website
Guest Editor
Department of Computer Science and Engineering, Nanhua University, Chiayi 62249, Taiwan
Interests: biomedical signal processing; biomedical system design; fast algorithm; transform; data compression; DSP chip; VLSI; hardware accelerator; digital calibration of ADC

Special Issue Information

Dear Colleagues,

With the rapid development of process technology, CMOS digital logic circuits have also made new developments. Facing the current diversified world, artificial intelligence, the Internet of Things, biomedical chips, communication signal processing chips, electronic equipment for autonomous vehicles, and other related research topics will become the focus of current research. In ASIC design, many advanced designs are required in terms of area, speed, throughput, and power consumption. Therefore, this Special Issue will invite outstanding researchers on CMOS digital logic circuits from all over the world to submit the most advanced research topics. Although this Special Issue covers the topics of CMOS digital logic circuits, artificial intelligence, Internet of Things, biomedical chips, and advanced digital signal processing chips, some specific topics include but are not limited to:

  • Artificial Intelligence Chip;
  • IoT chip;
  • Biomedical chip;
  • Advanced digital signal processing chip;
  • Communication signal processing chip;
  • Video/image signal processing chip.

Prof. Dr. Yuan-Ho Chen
Dr. Shin-Chi Lai
Guest Editors

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Electronics is an international peer-reviewed open access semimonthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 2400 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • Digital logic circuits
  • Artificial Intelligence chip
  • Advanced digital signal processing chip
  • Biomedical chip
  • VLSI
  • Hardware accelerator

Published Papers (2 papers)

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14 pages, 4931 KiB  
Article
Efficient and Accurate CORDIC Pipelined Architecture Chip Design Based on Binomial Approximation for Biped Robot
by Rih-Lung Chung, Yen Hsueh, Shih-Lun Chen and Patricia Angela R. Abu
Electronics 2022, 11(11), 1701; https://doi.org/10.3390/electronics11111701 - 26 May 2022
Cited by 4 | Viewed by 1498
Abstract
Recently, much research has focused on the design of biped robots with stable and smooth walking ability, identical to human beings, and thus, in the coming years, biped robots will accomplish rescue or exploration tasks in challenging environments. To achieve this goal, one [...] Read more.
Recently, much research has focused on the design of biped robots with stable and smooth walking ability, identical to human beings, and thus, in the coming years, biped robots will accomplish rescue or exploration tasks in challenging environments. To achieve this goal, one of the important problems is to design a chip for real-time calculation of moving length and rotation angle of the biped robot. This paper presents an efficient and accurate coordinate rotation digital computer (CORDIC)-based efficient chip design to calculate the moving length and rotation angle for each step of the biped robot. In a previous work, the hardware cost of the accurate CORDIC-based algorithm of biped robots was primarily limited by the scale-factor architecture. To solve this problem, a binomial approximation was carefully employed for computing the scale-factor. In doing so, the CORDIC-based architecture can achieve similar accuracy but with fewer iterations, thus reducing hardware cost. Hence, incorporating CORDIC-based architecture with binomial approximation, pipelined architecture, and hardware sharing machines, this paper proposes a novel efficient and accurate CORDIC-based chip design by using an iterative pipelining architecture for biped robots. In this design, only low-complexity shift and add operators were used for realizing efficient hardware architecture and achieving the real-time computation of lengths and angles for biped robots. Compared with current designs, this work reduced hardware cost by 7.2%, decreased average errors by 94.5%, and improved average executing performance by 31.5%, when computing ten angles of biped robots. Full article
(This article belongs to the Special Issue Recent Advances in CMOS Logic Circuits)
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19 pages, 5349 KiB  
Article
An Accuracy-Improved Fixed-Width Booth Multiplier Enabling Bit-Width Adaptive Truncation Error Compensation
by Song-Nien Tang, Jen-Chien Liao, Chen-Kai Chiu, Pei-Tong Ku and Yen-Shuo Chen
Electronics 2021, 10(20), 2511; https://doi.org/10.3390/electronics10202511 - 15 Oct 2021
Cited by 2 | Viewed by 1681
Abstract
Fixed-width Booth multipliers (FWBMs) generate a product with the same bit width as the operand and have been extensively employed in many digital systems. Various truncation error compensation (TEC) schemes have been presented for FWBM designs, aiming to reduce hardware costs while preserving [...] Read more.
Fixed-width Booth multipliers (FWBMs) generate a product with the same bit width as the operand and have been extensively employed in many digital systems. Various truncation error compensation (TEC) schemes have been presented for FWBM designs, aiming to reduce hardware costs while preserving operation accuracy. In general, the existing TEC methods function adequately for an exact bit width of the operand but fail to consider the TEC effect for FWBM inputs with various bit-width levels. To address this issue, we propose a bit-width adaptive TEC (BWATEC) scheme for providing high-accuracy TEC functions that are adaptive to the multiple L′-bit numerical ranges of input data for an L-bit FWBM (L′ ≤ L). We also present adjustable architecture for a 16-bit FWBM to enable the proposed BWATEC scheme and evaluate the hardware performance, using the TSMC 40 nm standard cell library. Relative to the contrast 16-bit FWBM approaches that use state-of-the-art TEC methods, the proposed BWATEC-enabled FWBM design can achieve reductions in the area-delay-error product of 7.9–50.9%, 17.1–69.5%, 29.9–82.2%, and 100% for the 14-bit, 12-bit, 10-bit, and 8-bit inputs, respectively. Moreover, the resultant 16-bit FWBM with BWATEC was verified by using the field-programmable gate array for convolutional neural network acceleration. Full article
(This article belongs to the Special Issue Recent Advances in CMOS Logic Circuits)
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